JPS60152040A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60152040A
JPS60152040A JP807884A JP807884A JPS60152040A JP S60152040 A JPS60152040 A JP S60152040A JP 807884 A JP807884 A JP 807884A JP 807884 A JP807884 A JP 807884A JP S60152040 A JPS60152040 A JP S60152040A
Authority
JP
Japan
Prior art keywords
film
insulating film
silicon
wiring layer
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP807884A
Other languages
Japanese (ja)
Inventor
Masashi Konno
今野 雅志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP807884A priority Critical patent/JPS60152040A/en
Publication of JPS60152040A publication Critical patent/JPS60152040A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form flatly an interlayer insulating film with no step difference by a method wherein three layers consisting of a second insulating film, a silicon compound applied forming coated film and a third insulating film are formed on a first insulating film formed on the surface of a substrate, an aperture in common to these three layers is provided and an aluminum film is evaporated on the whole surface. CONSTITUTION:A silicon dioxide film 2 is formed on the surface of a silicon substrate 1, and three layers of a silicon nitriding film 6, a silicon compound applied forming coated film 7 and a silicon dioxide film 8 are formed thereon. Apertures are provided in order on the three layers 8, 7 and 6. An aluminum film 3 is formed by evaporation on the whole surface. When the films 7 and 8 are removed by dissolution, the aluminum film 3 in the aperture of the silicon nitriding film 6 is left in a nearly non-step difference condition to the surrounding silicon nitriding films 6. A silicon nitriding film 4, which is used as an interlayer insulating film, is formed, covering the aluminum film 3 and the silicon nitriding films 6. Then, an aluminum film 3, which is used as a second wiring layer, is formed by evaporation.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、多層配線層を有する半導体装置の製造方法、
詳しくは、多層配線層間の絶縁膜を平坦に形成する製造
方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device having multilayer wiring layers;
Specifically, the present invention relates to a manufacturing method for forming a flat insulating film between multilayer wiring layers.

従来例の構成とその問題点 IC,LSIなどの高集積化半導体装置では、配線層を
多層構造にすることが多い。ところが。
Conventional configurations and their problems In highly integrated semiconductor devices such as ICs and LSIs, wiring layers often have a multilayer structure. However.

多層構造で配線層を形成する場合には、層間配線層の段
差を小さくすることが必要である。
When forming wiring layers in a multilayer structure, it is necessary to reduce the level difference between the interlayer wiring layers.

第1図は、従来例の二層配線構造を有する半導体装置の
断面図であシ、半導体基板1上に絶縁膜2が密着してお
シ、この上に、第1配線層3.眉間絶縁膜4および第2
配線層5を形成したものである。眉間絶縁膜4は、通常
、異方性成長の少ない窒化シリコン気相成長膜が用いら
れるが、多くの場合、第1配線層3の側端部で大きな段
差があシ、この上に形成された第2配線層6が段差部に
おいてくびれ部分を生じ、ここで断線を起し易いという
問題点をもっていた。
FIG. 1 is a sectional view of a conventional semiconductor device having a two-layer wiring structure, in which an insulating film 2 is in close contact with a semiconductor substrate 1, and a first wiring layer 3. Glabella insulating film 4 and second
A wiring layer 5 is formed thereon. The glabella insulating film 4 is usually a silicon nitride vapor-grown film with little anisotropic growth, but in many cases there is a large step at the side end of the first wiring layer 3, and the film is formed on top of this. The second wiring layer 6 has a constricted portion at the stepped portion, and there is a problem in that the wire is easily broken at this constricted portion.

発明の目的 本発明は、層間絶縁膜を段差なく、平坦に形成するだめ
の半導体装置の製造方法を提供するものである。
OBJECTS OF THE INVENTION The present invention provides a method for manufacturing a semiconductor device in which an interlayer insulating film is formed flat without any steps.

発明の構成 本発明は、要約するに、半導体表面に密着した第1絶縁
膜」二に、第2絶縁膜、シリコン化合物塗布形成被膜お
よび第3絶縁膜を順次形成する工程、前記第3絶縁膜上
にフォトレジヌト膜マスクパターンを形成して、このマ
スクパターン形状に沿って、前記第3絶縁膜、前記シリ
コン化合物塗布形成被膜、前記第2絶縁膜のそれぞれを
順次食刻開口する工程、前記開口部および前記第3絶縁
膜をおおって、第1配線層材を被着形成する工程、前記
第3絶縁膜および前記シリコン化合物塗布形成被膜の除
去により、前記第2絶縁膜の開口部に前記第1配線層利
を残置する工程、および前記第1配線層材と前記第2絶
縁膜とをおおって、層間絶縁膜を形成する工程をそなえ
た半導体装置の製造方法である。これにより、第2絶縁
膜の開口部に埋設される第1配線層材の厚さを、前記第
2絶縁膜の厚さと同じにすることで、これらの上面をお
おって形成される層間絶縁膜に段差が形成されず同層間
絶縁膜の表面が平坦になる。
Structure of the Invention The present invention can be summarized as follows: a first insulating film in close contact with a semiconductor surface; second, a step of sequentially forming a second insulating film, a silicon compound coating and a third insulating film; and a step of sequentially forming the third insulating film. forming a photoresin film mask pattern thereon, and sequentially etching openings in each of the third insulating film, the silicon compound coating film, and the second insulating film along the shape of the mask pattern; and a step of depositing and forming a first wiring layer material covering the third insulating film, and removing the third insulating film and the silicon compound coating to form the first wiring layer material in the opening of the second insulating film. The method of manufacturing a semiconductor device includes a step of leaving a wiring layer and a step of forming an interlayer insulating film covering the first wiring layer material and the second insulating film. Thereby, by making the thickness of the first wiring layer material embedded in the opening of the second insulating film the same as the thickness of the second insulating film, an interlayer insulating film is formed covering the upper surface of these. No step is formed between the two layers, and the surface of the interlayer insulating film becomes flat.

実施例の説明 第2図(a)〜(d)は、本発明実施例の工程順断面図
であり、以下、この図を参照して、本発明の詳細な説明
する。
DESCRIPTION OF THE EMBODIMENTS FIGS. 2(a) to 2(d) are sectional views of the embodiment of the present invention in the order of steps. Hereinafter, the present invention will be described in detail with reference to these figures.

まず、第2図(IL)のように、半導体基板、たとえば
、シリコン基板1の表面に二酸化シリコン膜2を形成し
、この上に、窒化シリコン膜6、シリコン化合物塗布形
成被膜7および最上層の二酸化シリコン膜8を形成して
、フォトレジヌト膜マスクパターンを用いて、二酸化シ
リコン膜8.シリコン化合物塗布形成被膜7および窒化
シリコン膜6に順次開口部を形成する。シリコン基板1
上の第1絶縁膜としての二酸化シリコン膜2は、表面安
定化被膜であり、たとえは、燐含有被膜である場合もあ
る。第2絶縁膜としての窒化シリコン膜6は、厚さ約1
μmに形成される。まだ、シリコン化合物塗布形成被膜
7は、通常、シラノールを希釈剤で調製して、回転塗布
法で被膜形成したのち乾燥および焼成して得られ、厚さ
約0.4μmに形成される。そして、第3絶縁膜として
の二酸化シリコン膜8は、気相成長法で形成される被膜
(Si02)であり、庁さ約0.6μmが適当である。
First, as shown in FIG. 2 (IL), a silicon dioxide film 2 is formed on the surface of a semiconductor substrate, for example, a silicon substrate 1, and a silicon nitride film 6, a silicon compound coating 7 and a top layer are formed on this. A silicon dioxide film 8 is formed, and a photoresin film mask pattern is used to form a silicon dioxide film 8. Openings are sequentially formed in the silicon compound coating film 7 and the silicon nitride film 6. Silicon substrate 1
The silicon dioxide film 2 as the upper first insulating film is a surface stabilizing film, and may be a phosphorus-containing film, for example. The silicon nitride film 6 as the second insulating film has a thickness of about 1
Formed in μm. The silicon compound coating 7 is usually obtained by preparing silanol with a diluent, forming a coating by spin coating, drying and baking, and is formed to a thickness of about 0.4 μm. The silicon dioxide film 8 as the third insulating film is a film (Si02) formed by vapor phase growth, and has a suitable thickness of about 0.6 μm.

ところで、最上層の二酸化シリコン膜8上にフォトレジ
スト脱マスクパターン(不図示)を形成して、これをマ
スクにして、二酸化シリコン膜8およびその直下のシリ
コン化合物産イD形成被膜7を同じ食刻液で食刻処理す
ると、下層のシリコン化合物塗布形成被膜7は、その食
刻速度が上層の二酸化シリコン膜8にくらべて約2倍で
あるから、上層の二酸化シリコン膜8が開口周辺で突き
出だ形状、いわゆるオーバハング状に食刻される。つづ
いて、窒化シリコン膜6を食刻処理するときには、シリ
コン化合物塗布形波膜7がマスクになり、このマスクパ
ターンに対応した開口が形成される。
By the way, a photoresist unmasking pattern (not shown) is formed on the uppermost silicon dioxide film 8, and using this as a mask, the silicon dioxide film 8 and the silicon compound D-forming film 7 immediately below it are exposed to the same etching pattern. When etched with an etching liquid, the etching rate of the lower silicon compound coating 7 is about twice that of the upper silicon dioxide film 8, so the upper silicon dioxide film 8 protrudes around the opening. It is etched in a so-called overhang shape. Subsequently, when etching the silicon nitride film 6, the silicon compound coated corrugated film 7 serves as a mask, and openings corresponding to this mask pattern are formed.

次に、第2図(b)に示すように、第1配線層拐として
、アルミニウム膜3を開口部内の厚さが約1−・ μm
になるように、蒸着形成する。このとき、アルミニウム
膜3は、二酸化シリコン膜B上とその開口部とで分離さ
れて形成される。
Next, as shown in FIG. 2(b), as a first wiring layer, an aluminum film 3 is deposited to a thickness of about 1-μm inside the opening.
It is formed by vapor deposition so that it becomes . At this time, the aluminum film 3 is formed separately on the silicon dioxide film B and its opening.

そこで、次にシリコン化合物塗布形成被膜7および二酸
化シリコン膜8を、たとえば、ふつ酸溶液を用いて、溶
解除去すると、この上のアルミニウム膜も、いわゆる、
リフトオフによって、剥離除去され、第2図(C)のよ
うK、窒化シリコン膜6の開口部のアルミニウム膜3が
、周囲の窒化シリコン膜6とほぼ無段差状態で残る。
Therefore, when the silicon compound coating 7 and the silicon dioxide film 8 are dissolved and removed using, for example, a hydrofluoric acid solution, the aluminum film thereon also becomes so-called.
The aluminum film 3 is peeled off by lift-off, and the aluminum film 3 in the opening of the silicon nitride film 6 remains in a substantially stepless state with respect to the surrounding silicon nitride film 6, as shown in FIG. 2(C).

ついで、第2図(tl)のように、アルミニウム膜3お
よび窒化シリコン膜6を覆って、層間絶縁膜としての窒
化シリコン膜4を形成する。この窒化シリコン膜4は、
通常の気相成長法により、厚さ約1μmに形成する。そ
して、この窒化シリコン膜4は、図示しないが、必要に
応じて、第1配線層のアルミニウム膜3と電気的接触を
得るための透孔を選択形成したのち、この上に、第2配
線層としてのアルミニウム膜3を蒸着形成する。この場
合、層間絶縁膜の窒化シリコン膜4が、下層のアルミニ
ウム膜3と窒化シリコン膜6七の間の無段谷を反映して
、はとんど平坦になっているので、第2配線層のアルミ
ニウム膜3も、同様に平坦な形状のものが得られる。
Then, as shown in FIG. 2 (tl), a silicon nitride film 4 is formed as an interlayer insulating film, covering the aluminum film 3 and the silicon nitride film 6. This silicon nitride film 4 is
It is formed to a thickness of about 1 μm by a normal vapor phase growth method. Although not shown in the drawings, this silicon nitride film 4 is selectively formed with a through hole for obtaining electrical contact with the aluminum film 3 of the first wiring layer, if necessary, and then a second wiring layer is formed on the silicon nitride film 4. An aluminum film 3 is formed by vapor deposition. In this case, since the silicon nitride film 4 of the interlayer insulating film is almost flat reflecting the stepless valley between the lower aluminum film 3 and the silicon nitride film 67, the second wiring layer Similarly, the aluminum film 3 can also have a flat shape.

なお、上述の実施例では、シリコン化合物塗布形成膜と
して、シラノール含有溶液の塗布形成膜を例示したが、
他のシリコン・オキシ誘導体を原料とした塗布形成被膜
でも、同様の作用が実現される。また、窒化シリコン膜
と二酸化シリコン膜とは、それぞれ、互いの配設位置を
置換しても、開口部にオーバハング形状を実現して、第
1配線層と第2絶縁膜との間に無段差状態を実現するこ
とが十分に可能である。
In the above-mentioned example, a film formed by coating a silanol-containing solution was exemplified as a film formed by coating a silicon compound.
Similar effects can be achieved with coatings formed using other silicon oxy derivatives as raw materials. In addition, even if the silicon nitride film and the silicon dioxide film are replaced with each other in their respective positions, an overhang shape is realized in the opening, and there is no step difference between the first wiring layer and the second insulating film. It is quite possible to realize the state.

発明の効果 本発明によれば、半導体表面の第1絶縁膜上に第2絶縁
膜、シリコン化合物塗布形成被膜および第3絶縁膜でな
る三層を形成したのち、この三層をフォトレジヌト膜マ
ヌクパターンを用いて第1配線層形成用開口部を形成す
ると、シリコン化合物塗布形成被膜の高食刻速度性によ
って、第3絶縁膜の開口部がオーバハング形状になり、
この開口部に蒸着形成された第1配線層を第2絶縁膜の
開口部と無段差に形成することができ、したがって、こ
の上に形成される層間絶縁膜ならびに第2配線層が平坦
性よく実現できる。
Effects of the Invention According to the present invention, after forming three layers consisting of a second insulating film, a silicon compound coating, and a third insulating film on a first insulating film on a semiconductor surface, these three layers are formed into a photoresin film manuk pattern. When the opening for forming the first wiring layer is formed using the silicon compound, the opening in the third insulating film becomes overhanging due to the high etching speed of the silicon compound coating.
The first wiring layer deposited in this opening can be formed without any difference in level from the opening in the second insulating film, so that the interlayer insulating film and the second wiring layer formed thereon have good flatness. realizable.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例の多層配線構造断面図、第2図(IL)
〜(+1)は本発明実施例の工程順断面図でおる。 1・・・・シリコン基板、2・・・・二酸化シリコン膜
、3・ −アルミニウム膜(第1配線層)、4・・・・
窒化シリコン膜、6・・・・アルミニウム膜(第2配4
91層)、6・・・・・・窒化シリコン膜、7・・・・
シリコン化合物塗布形成被膜、8・・・・・・二酸化シ
リコン膜。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第 2 図 (a−) 第2図 (b) (d−2
Figure 1 is a cross-sectional view of a conventional multilayer wiring structure, Figure 2 (IL)
-(+1) are sectional views in the order of steps of the embodiments of the present invention. 1...Silicon substrate, 2...Silicon dioxide film, 3.-aluminum film (first wiring layer), 4...
Silicon nitride film, 6...aluminum film (second layer 4
91 layers), 6... silicon nitride film, 7...
Silicon compound coating formed film, 8...Silicon dioxide film. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 (a-) Figure 2 (b) (d-2

Claims (1)

【特許請求の範囲】[Claims] 半導体表面に密着した第1絶縁膜に、第2絶縁膜、シリ
コン化合物塗布形成被膜および第3絶縁膜を順次形成す
る工程、前記第3絶縁膜上にフォトレジスト膜マヌクパ
ターンを形成して、このマスクパターン形状に沿って、
前記第3絶縁膜、前記シリコン化合物塗布形成被膜、前
記第2絶縁膜のそれぞれを順次食刻開口する工程、前記
開口部および前記第3絶縁膜上をおおって、第1配線層
材を被着形成する工程、前記第3絶縁膜および前記シリ
コン化合物塗布形成被膜の除去により、前記第2絶縁膜
の開口部に前記第1配線層材を残置する工程、および前
記第1配線層材と前記第2絶縁膜とをおおって、眉間絶
縁膜を形成する工程をそなえた半導体装置の製造方法。
a step of sequentially forming a second insulating film, a silicon compound coating, and a third insulating film on the first insulating film in close contact with the semiconductor surface; forming a photoresist film pattern on the third insulating film; Along the mask pattern shape,
Step of sequentially etching and opening each of the third insulating film, the silicon compound coating film, and the second insulating film, and covering the opening and the third insulating film with a first wiring layer material. a step of leaving the first wiring layer material in the opening of the second insulating film by removing the third insulating film and the silicon compound coating, and a step of leaving the first wiring layer material in the opening of the second insulating film; 2. A method for manufacturing a semiconductor device comprising the step of forming a glabella insulating film covering the second insulating film.
JP807884A 1984-01-19 1984-01-19 Manufacture of semiconductor device Pending JPS60152040A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP807884A JPS60152040A (en) 1984-01-19 1984-01-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP807884A JPS60152040A (en) 1984-01-19 1984-01-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60152040A true JPS60152040A (en) 1985-08-10

Family

ID=11683298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP807884A Pending JPS60152040A (en) 1984-01-19 1984-01-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60152040A (en)

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