JPS60152017A - Electron beam annealing device - Google Patents

Electron beam annealing device

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Publication number
JPS60152017A
JPS60152017A JP59007337A JP733784A JPS60152017A JP S60152017 A JPS60152017 A JP S60152017A JP 59007337 A JP59007337 A JP 59007337A JP 733784 A JP733784 A JP 733784A JP S60152017 A JPS60152017 A JP S60152017A
Authority
JP
Japan
Prior art keywords
electron
electron beam
sample
scanning
beams
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59007337A
Other languages
Japanese (ja)
Inventor
Kenji Shibata
健二 柴田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
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Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP59007337A priority Critical patent/JPS60152017A/en
Publication of JPS60152017A publication Critical patent/JPS60152017A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To realize a protruded type solid-liquid interface in relation to the advancing direction of an electron beam at electron beam annealing by a method wherein the chevron-shape beam is formed, and the beam thereof is scanned in the prescribed direction. CONSTITUTION:An electron beam radiated from a first electron gun 51 is deflected in a high speed according to a high-speed deflecting electrode 53 consisting of flat-board bodies of two sheets arranged facing mutually. An electron beam radiated from a second electron gun 52 is also deflected in a high speed according to a second high-speed deflecting electrode 54, and the linear beams are obtained. The two beams are deflected respectively in a chevron-shape according to beam connecting deflectors 55, 56. Accordingly, the solid-liquid interface of a sample to be annealed can be formed in a protruded type in the beam scanning direction, generation of a crystal grain boundary is suppressed to the utmost owing thereto, and formation in a single crystal can be attained easily.

Description

【発明の詳細な説明】 （発明の技術分野） 本発明は、電子ビームアニール装置に係わり、＼ 特にビーム形状をくの字形としてアニール条件の最適化
をはかった電子ビームアニール装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to an electron beam annealing apparatus, and particularly to an electron beam annealing apparatus in which the beam shape is doglegged and annealing conditions are optimized.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

近年、電子ビームやレーザー光等のエネルギービーム照
射装置によりＳ　ｉ、Ｇｅ、ＱａＡｓを始めとする半導
体或いはＡ１．ＭＯ，Ｗ等の金属や金属化合物を短時間
、局所的に熱処理することにより半導体デバイスの高速
化、高集積化、多機能化及び新機能、新構造なデバイス
の実現等の可能性が開けて来ている。この種の用途に用
いられる従来の電子ビームアニール装置は高電圧（５〜
３０ＫｅＶ）、大電流（１〜３０ＴｒＬＡ）の電子ビー
ムが取り出し可能な電子銃とその電源、ビームエネルギ
ーをコントロールする電気回路、ビームを偏向する電子
光学系及び試料ステージを備えたチャンバー等よりなり
、試料上・にビームを連続的に走査して熱処理、エピタ
キシャル成長及び溶融前帯の周辺から次々と発生し、中
心に向かって細長い結晶粒が成長する。所謂シェブロン
型の再結晶層となる。これは、第１図で示す用に再結晶
過程ｔにおいて結晶粒界が固液界面に直交して入るため
、であり、これを防ぐには第２図で示す様に再結晶“化
時の固液界面がビーム進行方向に対して凸型となるよう
にする必要がある。しかし、ガウス分布を持つ電子ビー
ムによるアニールでは上記進行方１向に対して凸型の固
液界面を形成することはできなかった。なお、図中Ａは
ビーム走査方向、Ｂは溶融領域、Ｃは結晶粒界、Ｄは再
結晶化領域をそれぞれ示している。In recent years, energy beam irradiation devices such as electron beams and laser beams have been used to irradiate semiconductors such as Si, Ge, and QaAs, or A1. By short-term, local heat treatment of metals and metal compounds such as MO and W, the possibility of realizing semiconductor devices with higher speed, higher integration, multifunctionality, new functions, and new structures is opened. It is coming. Conventional electron beam annealing equipment used for this type of application requires high voltage (5 to
It consists of an electron gun that can take out an electron beam of high current (1 to 30 TrLA), its power supply, an electric circuit that controls the beam energy, an electron optical system that deflects the beam, a chamber equipped with a sample stage, etc. By continuously scanning the beam upward and upward, elongated crystal grains are generated one after another from the periphery of the heat treatment, epitaxial growth, and pre-melting zone, and grow toward the center. This becomes a so-called chevron-type recrystallized layer. This is because the grain boundaries enter perpendicularly to the solid-liquid interface during the recrystallization process t, as shown in Figure 1.To prevent this, during recrystallization, as shown in Figure 2, It is necessary to form a solid-liquid interface that is convex in the direction of beam travel. However, in annealing using an electron beam with a Gaussian distribution, it is necessary to form a solid-liquid interface that is convex in one direction of travel. In the figure, A indicates the beam scanning direction, B indicates the melted region, C indicates the grain boundary, and D indicates the recrystallized region.

〔発明の目的］ 本発明の目的は、ビームの進行方向に対して凸型の固液
界面を形成することができ、特に絶縁膜上シリコンを広
い範囲に亘って容易に単結晶化し得る電子ビームアニー
ル装置を提供することにある。[Object of the Invention] The object of the present invention is to provide an electron beam that can form a solid-liquid interface that is convex in the direction of beam propagation, and that can easily single-crystallize silicon on an insulating film over a wide range. An object of the present invention is to provide an annealing device.

〔発明の概要〕[Summary of the invention]

本発明の骨子は、くの字形ビームを形成し、このビーム
を所定方向に走査することによって、前記ビームの進行
方向に対して凸型の固液界面を実現することにある。The gist of the present invention is to form a dogleg-shaped beam and scan this beam in a predetermined direction to realize a solid-liquid interface that is convex in the direction of travel of the beam.

ビームを線状化する方法としては、第３図（ａ）（ｂ）
に示す如くビーム１を試料上に集束させる最終段で対向
配置された高速偏向電極２により高速偏向して線状化す
る方法がある。ここで電極２に印加する電圧変動が１０
［ＫＨｚ］以下であるとビームは線状化できないが、周
波数の増大と共に線状化が進行する。第４図は周波数が
１００［ＫＨ２］と５０［ＭＨｚコの場合を代表的に示
したものであるが、１００［ＫＨｚ］ではおよそ６００
　［μｍ］　、５０　［ＭＨｚ］では９００［μｍ］長
ざまで線状化できることが実験で確かめられた。また、
本発明者等の鋭意研究によれば、上記のようにして線状
化したビームを２つ形成し、これらのビームを９０〜１
８０度の角度をもってつなげることにより、くの字形ビ
ームの形成が可能であることが判明した。The method of linearizing the beam is as shown in Fig. 3 (a) and (b).
As shown in FIG. 2, there is a method in which the beam 1 is focused on the sample and is deflected into a linear shape at high speed using high-speed deflection electrodes 2 placed opposite each other at the final stage. Here, the voltage fluctuation applied to electrode 2 is 10
If the frequency is below [KHz], the beam cannot be linearized, but linearization progresses as the frequency increases. Figure 4 shows typical cases where the frequency is 100 [KH2] and 50 [MHz], but at 100 [KHz], it is approximately 600 [KH2].
[μm], 50 [MHz], it was confirmed through experiments that linearization to a length of 900 [μm] was possible. Also,
According to intensive research by the present inventors, two linearized beams were formed as described above, and these beams were
It has been found that a doglegged beam can be formed by connecting them at an 80 degree angle.

本発明はこのような点に着目し、絶縁膜上のシリコン膜
等をアニール、して再結晶化する電子ビームアニール装
置において、電子ビームを放出する第１及び第２の電子
銃と、対向配置された２枚の平板体からなり、上記第１
及び第２の電子銃から放出された各電子ビームを高速偏
向してそれぞれ直線上のビームを形成する第１及び第２
の高速偏向電極と、上記２つの直線上ビームをそれぞれ
偏向制御し各ビームの一端を接続してくの字形ビームを
形成する第１及び第２のビーム接続用偏向器と、上記く
の字形ビームを被アニール試料上で前記各直線上ビーム
の接続点が前方となるように走査する手段とを設けるよ
うにしたものである。The present invention focuses on such points, and provides an electron beam annealing apparatus for annealing and recrystallizing a silicon film or the like on an insulating film, in which first and second electron guns that emit electron beams are arranged facing each other. It consists of two flat plate bodies, and the first
and a second electron gun that deflects each electron beam emitted from the electron gun at high speed to form a linear beam, respectively.
a high-speed deflection electrode, first and second beam connecting deflectors that respectively control the deflection of the two linear beams and connect one end of each beam to form a dogleg-shaped beam; A means for scanning the sample to be annealed so that the connection point of each of the linear beams is in the front is provided.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、２つの直線状ビームを接続したくの字
形の電子ビームを形成することができる。According to the present invention, a dogleg-shaped electron beam can be formed by connecting two linear beams.

このため、上記くの字形ビームを直線状ビームの接続点
が前方となるように被アニール試料上で走査することに
より、ビーム走査方向に対し凸型の固液界面を実現する
ことができる。従って、結晶粒界の発生を効果的に迎え
ることができ、絶縁膜上シリコン等を広範囲に亘って容
易に単結晶化することができる。Therefore, by scanning the dogleg-shaped beam over the sample to be annealed with the connecting point of the straight beam facing forward, it is possible to realize a solid-liquid interface that is convex in the beam scanning direction. Therefore, the generation of crystal grain boundaries can be effectively achieved, and silicon, etc. on the insulating film can be easily single-crystalized over a wide range.

〔発明の実施例〕[Embodiments of the invention]

第５図は本発明の一実施例に係わる電子ビームアニール
装置を示す概略構成図である。なお、この図ではビーム
を集束するレンズ系及び０Ｎ−ＯＦＦするブランキング
電極等は省略している。図中５１は第１の電子銃、５２
は第２の電子銃であり、第１の電子銃５１から放出され
た電子ビームは対向配置された２枚の平板体からなる高
速偏向電極５３により高速で偏向される。第１の電極５
３は前記第３図（ａ）に示した如く高周波電圧が印加さ
れており、これにより直線状のビームが１ｑられる。一
方、第２の電子銃５２が放出された電子ビームも第２の
高速偏向Ｎ極５４により高速偏向され、上記と同時に直
線状のビームが得られる。FIG. 5 is a schematic configuration diagram showing an electron beam annealing apparatus according to an embodiment of the present invention. In this figure, a lens system for focusing the beam, a blanking electrode for ON-OFF, etc. are omitted. In the figure, 51 is the first electron gun, 52
is a second electron gun, and the electron beam emitted from the first electron gun 51 is deflected at high speed by a high-speed deflection electrode 53 consisting of two flat plates arranged opposite to each other. first electrode 5
3, a high frequency voltage is applied as shown in FIG. 3(a), thereby producing a linear beam of 1q. On the other hand, the electron beam emitted by the second electron gun 52 is also deflected at high speed by the second high-speed deflection north pole 54, and a linear beam is obtained at the same time as described above.

上記２つの直線状ビームは第１及び第２のビーム接続用
偏向器５５．５６によりそれぞれ偏向される。そして、
直線状ビームの一端が角度　θ（９０’＜θく１８０°
）で接続されてくの字形ビームが形成されるものとなっ
ている。また、このくの字形ビームは前記偏向器５５．
５６により直線状ビームの接続点が前方となるように被
アニール試料上を走査されるものとなっている。The two linear beams are deflected by first and second beam connecting deflectors 55 and 56, respectively. and,
One end of the straight beam is at an angle θ (90'<θ>180°
) to form a dogleg-shaped beam. Further, this dogleg-shaped beam is formed by the deflector 55.
56, the sample to be annealed is scanned with the connecting point of the linear beam facing forward.

このような構成であれば、高速偏向電極５２゜５４及び
ビーム接続用偏向器５３．５６等の作用によりビーム形
状をくの字形とし、且つこのくの字形ビームを走査する
ことができる。このため、被アニール試料の固液界面を
ビーム走査方向に凸型に形成−することができ、これに
より結晶粒界発生を極力押え単結晶化を容易に行うこと
ができる。With this configuration, the beam shape can be made into a dogleg shape by the actions of the high-speed deflection electrodes 52, 54, the beam connecting deflectors 53, 56, etc., and this dogleg-shaped beam can be scanned. Therefore, the solid-liquid interface of the sample to be annealed can be formed into a convex shape in the beam scanning direction, thereby making it possible to easily form a single crystal while suppressing the generation of grain boundaries as much as possible.

次に上記実施例装置を２層ＭＯ８−ＬＳＩ製造に用いた
実験例について説明する。まず、第６図（ａ）に示す如
く例えばＰ型（１００）面方位の単結晶シリコン基板６
１の上に約１［μｍ］のＳｉ０２層６２を形成する。そ
の上に必要とあればＳｉＮ膜６膜管３成する。このＳｉ
Ｎ膜６膜管３の工程で多結晶あるいは非晶質シリコン層
を単結晶化させやすくするために形成するものであり、
必ずしも必要としない。またシリコン基板６１は既に所
望の素子が周知の工程を終で形成されているとする。次
いで、第６図（ｂ）に示す如く、ＳｉＮ膜６膜管３面に
例えば約６００Ｑ　［大コの多結晶シリコン層６４を被
着する。その上に約２０００　［人］のＳｉＯ２膜６５
膜形５する。この１・、 １、時の８＋０２膜６５は、後の工程で多結晶あるい、
は非晶質シリコン層を単結晶化させやすくするた１．１ めに形成するものでＳＩＮ膜等でもかまわない。Next, an experimental example in which the above embodiment apparatus was used to manufacture a two-layer MO8-LSI will be described. First, as shown in FIG. 6(a), for example, a single crystal silicon substrate 6 having a P type (100) plane orientation
A Si02 layer 62 of about 1 [μm] is formed on the substrate 1. If necessary, 6 SiN films and 3 film tubes are formed thereon. This Si
It is formed to facilitate single crystallization of a polycrystalline or amorphous silicon layer in the process of forming the N film 6 film tube 3.
Not necessarily necessary. It is also assumed that desired elements have already been formed on the silicon substrate 61 through a well-known process. Next, as shown in FIG. 6(b), a polycrystalline silicon layer 64 having a thickness of, for example, about 600 Q is deposited on the three surfaces of the six SiN film tubes. Approximately 2,000 [people] of SiO2 film 65 is placed on top of that.
Membrane shape 5. This 1., 1, time 8+02 film 65 will be made into polycrystalline or
1.1 is formed to facilitate single crystallization of the amorphous silicon layer, and may be a SIN film or the like.

次に、第６図（Ｃ）に示す如く前記第５図に示す装置を
用いて上部から電子ビーム熱処理をして上記シリコン層
６４を単結晶化する。その際、ビーム加速電圧は１０［
Ｋ、ｅｖ］、ビーム電流は５［ｍＡ］、ビーム線状化の
ための高速偏向では周波数５０［ＭＨｚ］、電極印加電
圧８０　［Ｖ］、ＳＩＮ波を用いて行った。また、試料
表面温度を５００　［’Ｃ］　、ビーム走査速ｆｆ１ｃ
ｃｍ／ｓ］で行った。実施例に用いた装置によればアニ
ール中に溶融するシリコン層の幅は２［ｓｌでそのうち
中央部の幅約１［ｍｍ］が完全に単結晶化された。ビー
ム走査を繰返してゆくと単結晶化の幅はさらに広がり５
　［８］　Ｘ　５　ＥｙｒｍＪが単結晶化できる様にな
った。Next, as shown in FIG. 6C, the silicon layer 64 is made into a single crystal by performing electron beam heat treatment from above using the apparatus shown in FIG. At that time, the beam acceleration voltage was 10[
K, ev], beam current was 5 [mA], high-speed deflection for beam linearization was performed using a frequency of 50 [MHz], an electrode applied voltage of 80 [V], and a SIN wave. In addition, the sample surface temperature was set to 500 ['C], and the beam scanning speed was set to ff1c.
cm/s]. According to the apparatus used in the example, the width of the silicon layer melted during annealing was 2 [sl], and the width of the central portion of about 1 [mm] was completely converted into a single crystal. As the beam scanning is repeated, the width of single crystallization further expands5.
[8] X 5 EyrmJ can now be made into a single crystal.

次に、第６図（ｄ）に示す如く、５１０２膜６５を除去
後電子ビーム熱処理によって単結晶化したシリコン層６
４−をバターニングして二層目の素子形成領域とし、そ
の後公知の技術にて素子間分離絶縁膜６６を形成し、素
子形成領域にグー１〜酸化膜６７を介して例えば多結晶
シリ゛コンからなるゲート電極６８を形成し、ソース・
ドレイン領域６９ａ、６９ｂを形成してＭｏ３　ｌ−ラ
ンリスタとする。次いで、第６図（ｅ）に示す如く全面
を絶縁ＩＩ　７０で覆った後、Ａ１による電極７１ａ。Next, as shown in FIG. 6(d), after removing the 5102 film 65, the silicon layer 6 is made into a single crystal by electron beam heat treatment.
4- is patterned to form a second layer element formation region, and then an element isolation insulating film 66 is formed using a known technique, and polycrystalline silicon, for example, is formed in the element formation region through the oxide film 67. A gate electrode 68 made of a conductor is formed, and a source electrode 68 is formed.
Drain regions 69a and 69b are formed to form a Mo3 l-run lister. Next, as shown in FIG. 6(e), after covering the entire surface with an insulator II 70, an electrode 71a made of A1 is formed.

〜、７１Ｃを形成して２層ＭＯ８−ＬＳＩを完成する。. . , 71C are formed to complete a two-layer MO8-LSI.

なお、本発明は上述した実施例に限定されたものではな
い。例えば、前記くの字形ビームの折れ角θは９０６〜
１８０°の範囲で、適宜定めればよい。また、くの字形
ビームを試料上で走査する手段として、前記ビーム接続
用偏向器の代りにこれより試料側にビーム走査用偏向器
を設けるようにしてもよい、また、実施例で述べたＭＯ
Ｓトランジスタの他に、Ｃ−Ｍｏ５ｔ〜ランジスタ、パ
イ−ポーラトランジスタ、ダイオード等あらゆる素子を
熱処理したシリコン層に形成して効果を挙げることは言
うまでもなく、本発明の効果を用いて、これらの素子を
３次元的に配列することにより、従来より高集積、高性
能、多機能等の３次元集積回路装置を実現することが可
能となる。さらに、シリコン以外の半導体、例えばＧｅ
やＧａＡｓ。Note that the present invention is not limited to the embodiments described above. For example, the bending angle θ of the doglegged beam is 906~
It may be determined as appropriate within the range of 180°. Furthermore, as a means for scanning the dogleg-shaped beam on the sample, a beam scanning deflector may be provided on the sample side instead of the beam connecting deflector.
In addition to S transistors, it goes without saying that all kinds of elements such as C-Mo5t transistors, bipolar transistors, diodes, etc. can be effectively formed on heat-treated silicon layers, and these elements can be formed using the effects of the present invention. By arranging them three-dimensionally, it becomes possible to realize a three-dimensional integrated circuit device with higher integration, higher performance, and more functions than ever before. Furthermore, semiconductors other than silicon, such as Ge
and GaAs.

ＧａＰ、ＩｎＰ、ＩｎＳｂ等の化合物半導体装置いても
十分な効果が期待できる。その他、本発明の要旨を逸脱
しない範囲で、種々変形して実施することができる。Sufficient effects can be expected even with compound semiconductor devices such as GaP, InP, and InSb. In addition, various modifications can be made without departing from the gist of the present invention.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のスポットビームによる再結晶化における
結晶粒界の現われ方を示づ模式図、第２図は固液界面を
ビーム進行方向に対して凸となる様にした時の結晶粒界
の現われ方を示す模式図、第３図（ａ）（ｂ）及び第４
図は本発明の詳細な説明するためのもので第３図（ａ）
（ｂ）はビームを線状化する方法を示す模式図、第４図
は周波数を１００　［ＫＨｚ］、５０　［ＭＨｚ］でビ
ームを線状化した時の印加電圧に対するビーム長さ、の
関係を示す特性図、第５図は本発明の一実施例に係わる
電子ビームアニール装置を示す概略構成図、第６図（ａ
、）〜（ｅ）は上記実隠例装置を用いて行った２層ＭＯ
３ＬＳＩ製造工程を示す断面図である。 ５１・・・第１の電子銃、５２・・・第２の電子銃、５
３・・・第１の高速偏向電極、５４・・・第２の高速偏
向電極、５５・・・第１のビーム接続用偏向器、５６・
・・第２のビーム接続用偏向器、５７・・・くの字形ビ
ーム、６１・・・シリコン基板、６２・・・Ｓｉ　０２
　ｆｔ！、６３・・・ＳｔＮ膜、６４・・・多結晶若し
くは非晶質シリコン層、６４−・・・単結晶化したシリ
コン層、６５・・・５ｉ０２１１１１６６・・・絶縁膜
、６７・・・ゲート酸化膜、６８・・・ゲート電極、６
９ａ、６９ｂ・・・ソース・ドレイン領域、７０・・・
絶縁膜、７１ａ、〜、７１Ｃ・・・Ａ１電極。 出願人　工業技術院長　用田裕部 第１図Figure 1 is a schematic diagram showing how grain boundaries appear in recrystallization using a conventional spot beam, and Figure 2 shows grain boundaries when the solid-liquid interface is convex with respect to the beam traveling direction. Schematic diagrams showing how this appears, Figures 3(a)(b) and 4
The drawings are for detailed explanation of the present invention, and are shown in Fig. 3(a).
(b) is a schematic diagram showing the method of linearizing the beam, and Figure 4 shows the relationship between the applied voltage and the beam length when the beam is linearized at frequencies of 100 [KHz] and 50 [MHz]. 5 is a schematic configuration diagram showing an electron beam annealing apparatus according to an embodiment of the present invention, and FIG. 6 (a) is a characteristic diagram shown in FIG.
, ) to (e) are two-layer MOs performed using the above real hidden example device.
It is a sectional view showing a 3LSI manufacturing process. 51...first electron gun, 52...second electron gun, 5
3... First high-speed deflection electrode, 54... Second high-speed deflection electrode, 55... First beam connection deflector, 56...
...Second beam connection deflector, 57...Dog-shaped beam, 61...Silicon substrate, 62...Si 02
ft! , 63... StN film, 64... Polycrystalline or amorphous silicon layer, 64-... Single crystal silicon layer, 65... 5i02111166... Insulating film, 67... Gate oxidation Film, 68... Gate electrode, 6
9a, 69b...source/drain region, 70...
Insulating film, 71a to 71C...A1 electrode. Applicant: Director of the Agency of Industrial Science and Technology Hirobe Yoda Figure 1

Claims (3)

【特許請求の範囲】[Claims] （１）電子ビームを放出する第１及び第２の電子銃と、
対向配置された２枚の平板体からなり、上記第１及び第
２の電子銃から放出された各電子ビームを高速偏向して
それぞれ直線上のビームを形成する第１及び第２の高速
偏向電極と、上記２つの直線上ビームをそれぞれ偏向制
御し各ビームの一端を接続してくの字形ビームを形成す
る第１及び第２のビーム接続用偏向器と、上記くの字形
ビームを被アニール試料上で前記各直線上ビームの接続
点が前方となるように走査する手段とを具備してなるこ
とを特徴とする電子ビームアニール装置。(1) first and second electron guns that emit electron beams;
First and second high-speed deflection electrodes, which are composed of two flat plates arranged opposite each other, and which deflect each electron beam emitted from the first and second electron guns at high speed to form linear beams, respectively. and first and second beam connecting deflectors that respectively control the deflection of the two linear beams and connect one end of each beam to form a dogleg-shaped beam, and direct the doglegged beam onto the sample to be annealed. and scanning means for scanning so that the connection point of each of the linear beams is in the front. （２）前記くの字形ビームを試料上で走査する手段は、
前記第１及び第２のビーム接続用偏向器により上記ビー
ムを走査することである特許請求の範囲第１項記載の電
子ビームアニール装置。(2) The means for scanning the dogleg-shaped beam on the sample,
2. The electron beam annealing apparatus according to claim 1, wherein said beam is scanned by said first and second beam connection deflectors. （３）前記くの字形ビームを試料上で走査する手段は、
前記第１及び第２のビーム接続用偏向器よりも試料側に
設けたビーム走査用偏向器により上記ビームを走査する
ことである特許請求の範囲第１項記載の電子ビームアニ
ールＶ装置。(3) The means for scanning the dogleg-shaped beam on the sample,
2. The electron beam annealing V apparatus according to claim 1, wherein the beam is scanned by a beam scanning deflector provided closer to the sample than the first and second beam connection deflectors.
JP59007337A 1984-01-20 1984-01-20 Electron beam annealing device Pending JPS60152017A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59007337A JPS60152017A (en) 1984-01-20 1984-01-20 Electron beam annealing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59007337A JPS60152017A (en) 1984-01-20 1984-01-20 Electron beam annealing device

Publications (1)

Publication Number Publication Date
JPS60152017A true JPS60152017A (en) 1985-08-10

Family

ID=11663127

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59007337A Pending JPS60152017A (en) 1984-01-20 1984-01-20 Electron beam annealing device

Country Status (1)

Country Link
JP (1) JPS60152017A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5839012A (en) * 1981-08-31 1983-03-07 Fujitsu Ltd Single-crystalization of non-single crystal semiconductor layer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5839012A (en) * 1981-08-31 1983-03-07 Fujitsu Ltd Single-crystalization of non-single crystal semiconductor layer

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