JPS63265419A - Manufacture of semiconductor crystal layer - Google Patents

Manufacture of semiconductor crystal layer

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Publication number
JPS63265419A
JPS63265419A JP9873187A JP9873187A JPS63265419A JP S63265419 A JPS63265419 A JP S63265419A JP 9873187 A JP9873187 A JP 9873187A JP 9873187 A JP9873187 A JP 9873187A JP S63265419 A JPS63265419 A JP S63265419A
Authority
JP
Japan
Prior art keywords
film
semiconductor
semiconductor film
opening
polycrystalline silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9873187A
Other languages
Japanese (ja)
Other versions
JPH0793262B2 (en
Inventor
Hidekazu Kawaguchi
川口 英一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP62098731A priority Critical patent/JPH0793262B2/en
Publication of JPS63265419A publication Critical patent/JPS63265419A/en
Publication of JPH0793262B2 publication Critical patent/JPH0793262B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To form a single crystal semiconductor film for shaping an upper layer element without giving thermal damage to a lower layer element while simplifying a manufacturing process for the semiconductor film, increasing the area of an element forming region and flattening a stepped section on an opening section in an insulating film on a substrate by forming the semiconductor film in the opening section to a recessed shape. CONSTITUTION:An silicon oxide film 12 is deposited onto a semiconductor substrate 11, and an opening section 13 is shaped to one part of the silicon oxide film 12. A polycrystalline silicon film 14 is deposited onto the whole surface. The whole surface of the polycrystalline silicon film 14 is etched until the surface of the silicon oxide film 12 is exposed. A polycrystalline silicon film 15 is deposited onto the whole surface again, and the surface of the polycrystalline silicon film 15 is formed to a recessed shape that the surface shape of the polycrystalline silicon film 14 as a first layer is reflected in the opening section 13. An silicon oxide film 16 is deposited onto the whole surface as a protective film, the substrate 11 is heated while quasi linear electron beams 17 are applied, and the polycrystalline silicon film 16 is melted and recrystallized. Accordingly, the polycrystalline silicon film 15 is changed into an excellent single crystal film by growth from the opening section 13.

Description

【発明の詳細な説明】 [発明の目的] (従来の技術) 近年、レーデビームや電子ビーム等によるアニールで絶
縁膜上に半導体単結晶膜を形成する、所謂SOI (5
111con on In5ulator )技術の開
発が盛んに行われている。また、この技術を利用して素
子を3次元的に形成する3次元ICの開発も進められて
いる。この3次元ICは、半導体ウェハ裏面に竪膚六れ
奔壷早CT層畳;)μf層間謁緬膜を形成したのち、 
SOI技術によ)単結晶半導体膜を形成し1次いで該単
結晶半導体膜に素子(上層素子)を形成することによシ
作成される。
[Detailed description of the invention] [Object of the invention] (Prior art) In recent years, so-called SOI (SOI
111con on In5ulator) technology is being actively developed. Furthermore, development of three-dimensional ICs in which elements are formed three-dimensionally using this technology is also underway. This 3D IC is produced by forming a 3-dimensional CT layer on the backside of a semiconductor wafer;
It is manufactured by forming a single crystal semiconductor film (by SOI technology) and then forming an element (upper layer element) on the single crystal semiconductor film.

ところで、上層素子形成用の単結晶半導体膜を形成する
には、その結晶方位を制御する技術が必要である。この
技術としては、結晶方位の制御が確実であり、単結晶化
面積を大きくできるラテラルシーディングエピタキシャ
ル成長法が広く使用されている。この成長法は、エネル
ギービームによって上層素子形成用の単結晶半導体膜を
形成する際に、層間絶縁膜の開口部よシ下部半導体単結
;、、%ラテラルシーディングエピタキシャル法によシ
ー゛単結晶半導体膜を作成する場合、従来の試料構造で
は、エネルギービームによシ半導体膜を融解する際に、
下層素子に熱的ダメ−)を与えずに層間絶縁族の開口部
の半導体膜を融解するのは困難である。この問題を解決
するために、ストライプ状開口部の分割化、開口部形状
の点状化等によって開口部面積を減少させる方法が検討
されてきた。
By the way, in order to form a single crystal semiconductor film for forming an upper layer element, a technique for controlling the crystal orientation is required. As this technique, the lateral seeding epitaxial growth method is widely used because it can reliably control the crystal orientation and can increase the area of single crystallization. In this growth method, when forming a single crystal semiconductor film for forming an upper layer element using an energy beam, the lower semiconductor single crystal is grown from the opening of the interlayer insulating film using a lateral seeding epitaxial method. When creating a semiconductor film, in the conventional sample structure, when the semiconductor film is melted by an energy beam,
It is difficult to melt the semiconductor film in the opening of the interlayer insulation group without causing thermal damage to the underlying elements. In order to solve this problem, methods of reducing the opening area by dividing the opening into stripes, making the opening into dots, etc. have been studied.

これによシ、開口部面積を単結晶半導体膜形成に必要な
最小限の大きさに制限し、開口部半導体膜の融解の容易
化が可能となっている。しかし、下層素子への熱の流れ
をよシ小さくシ、下層素子の熱的ダメージを十分に減少
させるには、層間絶縁層を1μm以上に厚くする必要が
あシ、この場合、開口部の半導体膜の融解は困難であっ
た。
This makes it possible to limit the area of the opening to the minimum size necessary for forming a single crystal semiconductor film and facilitate melting of the semiconductor film in the opening. However, in order to further reduce the flow of heat to the lower layer elements and to sufficiently reduce thermal damage to the lower layer elements, it is necessary to thicken the interlayer insulating layer to 1 μm or more. Melting of the membrane was difficult.

この対策としては、第3図に示す如く開口部の層間絶縁
膜に傾斜を作る方法や、開口部及びその周辺部の多結晶
或いは非晶質半導体膜を他の部分よシも厚くする方法が
提案され、一応の効果を発揮している。しかしながら、
この種の方法では工程の増加、開口部占有面積の増大化
による素子領追層間絶縁膜、13は開口部、15は多結
晶若しくは非晶質のシリコン膜、16は保護膜を示して
いる。
As a countermeasure for this problem, there are methods such as creating a slope in the interlayer insulating film at the opening and making the polycrystalline or amorphous semiconductor film thicker in the opening and its surrounding area than in other parts. It has been proposed and has shown some effectiveness. however,
In this type of method, the number of steps is increased and the area occupied by the opening is increased, resulting in an element-regulating interlayer insulating film, 13 is the opening, 15 is a polycrystalline or amorphous silicon film, and 16 is a protective film.

(発明が解決しようとする問題点) このように従来、エネルギービームにより”C下層素子
に熱的ダメージを与えずに上層素子形成用の単結晶半導
体膜を作成する際には、工程の増大、素子形成領域の減
少、更には多層構造を形成する際の開口部上の平坦化等
の問題があった。
(Problems to be Solved by the Invention) Conventionally, when creating a single crystal semiconductor film for forming an upper layer element using an energy beam without causing thermal damage to the C lower layer element, the number of steps increases, There have been problems such as a reduction in the element forming area and flattening of the opening when forming a multilayer structure.

本発明は上記事情を考慮してなされたもので。The present invention has been made in consideration of the above circumstances.

その目的とするところは、下層素子に熱的ダメージを与
んずに上層素子形成用単結晶半導体膜を作成することが
でき、且つその作成工程の簡略化。
The purpose is to be able to create a single crystal semiconductor film for forming upper layer elements without causing thermal damage to lower layer elements, and to simplify the manufacturing process.

素子形成領域面積の増大化及び開口部上の段差平坦化の
容易化をはかることができ、3次元ICの製造に好適す
る半導体結晶層の製造方法を提供することにある。
It is an object of the present invention to provide a method for manufacturing a semiconductor crystal layer, which can increase the area of an element formation region and facilitate flattening of steps on an opening, and is suitable for manufacturing a three-dimensional IC.

[発明の構成コ (問題点を解決するための手段) 本発明の骨子は、開口部における半導体膜を・凹型形状
にすることによシ、エネルギービーム照ゝ1: 射中の半導体膜の均一な溶解を可能としたことに、i 
? ・j1即ち本発明は、半導体基板上に一部開口部を有÷
る絶縁膜を形成したのち、絶縁膜上及び開口部−リ ・二に露出し死生導体基板上に多結晶若しくは非晶質し
゛ の半導体膜を堆積し、且つこの半導体膜を上記開口部に
おいて凹型に形成し、次いでエネルギービームを照射し
ながら走査することによシ上記半導体膜を単結晶化する
ようにした方法である。
[Structure of the Invention (Means for Solving Problems)] The gist of the present invention is to provide energy beam irradiation by forming the semiconductor film in the opening into a concave shape.1: Uniformity of the semiconductor film during irradiation The i
?・j1 That is, the present invention has a partial opening on the semiconductor substrate.
After forming an insulating film, a polycrystalline or amorphous semiconductor film is deposited on the insulating film and on the dead conductor substrate exposed in the opening, and this semiconductor film is formed into a concave shape in the opening. In this method, the semiconductor film is formed into a single crystal by scanning the semiconductor film while irradiating it with an energy beam.

(作用) 本発明によれば、開口部上に凹部を形成することKよシ
、開口部の半導体基板とエネルギービーム加熱部との距
離を従来法に比べて短くすることができ、層間絶縁膜を
厚くしても、開口部の半導体膜の溶解は容易Kmわれる
。従って、エネルギービームの照射量を従来よシも少な
くすることができ、下層素子に与える熱的ダメージを小
さくすることが可能となる。また、開口部の層間絶縁M
XKは傾斜部を設ける必要がなく、従って作成工程が簡
略化される。さらに、単結晶化された半導体膜の凹凸は
開口部上の小さな窪みのみであるため一往来より用りら
れて禽た騰1ふ平伯什T用帽不要となる。
(Function) According to the present invention, the distance between the semiconductor substrate in the opening and the energy beam heating part can be shortened compared to the conventional method, and the distance between the semiconductor substrate in the opening and the energy beam heating part can be shortened, and the interlayer insulating film Even if the thickness is increased, the semiconductor film in the opening is easily dissolved. Therefore, the amount of energy beam irradiation can be reduced compared to the conventional method, and thermal damage to lower layer elements can be reduced. In addition, the interlayer insulation M of the opening
XK does not require an inclined portion, and therefore the manufacturing process is simplified. Furthermore, since the unevenness of the single-crystal semiconductor film is only a small depression above the opening, it can be used for a long time, eliminating the need for a cap.

(実施例) 以下、本発明の詳細を1図示の実施例によって説明する
(Example) Hereinafter, the details of the present invention will be explained by referring to an example shown in one figure.

i第1図は本発明の一実施例方法に係わる単結晶ルIJ
:ryよ。、造工程、8オ断、図、あ、。まず、第1図
(−)に示す如く1両方位(100)の単結晶シリコン
基板(半導体基板)11上にLPCVD法によシ厚さ2
μmのシリコン酸化膜(層間絶縁膜)12を堆積し、こ
のシリコン酸化膜12の一部にRIE法によ?)2At
Iφの開口部13を形成する。続いて、全面に多結晶シ
リコン膜(半導体膜)14を2μmの厚さに堆積した。
Figure 1 shows a single crystal IJ according to an embodiment of the method of the present invention.
:ry. ,Building process, 8 ocution, figure, ah. First, as shown in FIG.
A silicon oxide film (interlayer insulating film) 12 with a thickness of μm is deposited, and a portion of this silicon oxide film 12 is coated by RIE. )2At
An opening 13 of Iφ is formed. Subsequently, a polycrystalline silicon film (semiconductor film) 14 was deposited on the entire surface to a thickness of 2 μm.

なお、シリコン基板11には所定の素子(下層素子)が
形成されているものとする。また、開口部13は第2図
(a)に示す如く点状に配列形成したものであるが、同
図伽)に示す如くストライプ状に形成してもよい。
Note that it is assumed that a predetermined element (lower layer element) is formed on the silicon substrate 11. Furthermore, although the openings 13 are arranged in dots as shown in FIG. 2(a), they may be formed in stripes as shown in FIG.

次いで、化学ドライエツチング(CDI )法を用い、
多結晶シリコン膜14をシリコン酸化膜12の表面が露
出するまで全面エツチングした。このとき、開口部13
内の多結晶シリコン膜14は、第1図(b)に示す如く
、凹型形状となった。なお、上記CDEO際には、エツ
チングガスとしてCF4と02との混合ガスを用いた。
Then, using a chemical dry etching (CDI) method,
The entire surface of the polycrystalline silicon film 14 was etched until the surface of the silicon oxide film 12 was exposed. At this time, the opening 13
The inner polycrystalline silicon film 14 had a concave shape as shown in FIG. 1(b). Incidentally, in the above-mentioned CDEO, a mixed gas of CF4 and 02 was used as an etching gas.

次いで、第1図(、)に示す如く、全面に再び多結晶シ
リコンWX15を0.81Arnの厚さに堆積した・こ
“庸 画形状を反映した凹型形状となりていた。
Next, as shown in FIG. 1(,), polycrystalline silicon WX15 was deposited again on the entire surface to a thickness of 0.81Ar, resulting in a concave shape reflecting the shape of the original.

1次いで、第1図(d)に示す如く、全面に保峡膜とし
てシリコン酸化膜16を0.5mの厚さに堆積したのち
、基板11を600℃に加熱すると共に疑似線状電子ビ
ーム11を照射して多結晶シリコン膜16の溶融再結晶
化を行った。ここで、疑似線状電子ビームとは、ビーム
走査方向と直交する方向に該ビームを高速偏向すること
によシ、仮想的に線状電子ビームとしたものである。ま
た、ビーム照射時の条件としては、加速電圧10kV、
ビーム長0.8μ巾、ビーム偏向周波数30 MHz 
、ビーム変調周波数10 kHz 、ビーム走査速度1
00+g@/s@eとした。
1. Next, as shown in FIG. 1(d), after depositing a silicon oxide film 16 to a thickness of 0.5 m on the entire surface as a protective film, the substrate 11 is heated to 600° C. and a pseudo linear electron beam 11 is deposited on the entire surface. was irradiated to melt and recrystallize the polycrystalline silicon film 16. Here, the pseudo-linear electron beam is a beam that is virtually made into a linear electron beam by deflecting the beam at high speed in a direction perpendicular to the beam scanning direction. In addition, the conditions for beam irradiation include an accelerating voltage of 10 kV,
Beam length 0.8 μ width, beam deflection frequency 30 MHz
, beam modulation frequency 10 kHz, beam scanning speed 1
00+g@/s@e.

その結果、多結晶シリコン膜15は開口部13からの成
長によシ良好な単結晶膜となった。ま九。
As a result, the polycrystalline silicon film 15 grew from the opening 13 and became a good single crystal film. Nine.

シリコン基板1ノに形成された下層素子には、ビームア
ニール時の熱的ダメージによ)その特性が劣化する等の
不都合は生じなかった。
The lower layer element formed on the silicon substrate 1 did not suffer any inconvenience such as deterioration of its characteristics (due to thermal damage during beam annealing).

かくして本実施例方法によれば、絶縁膜12上に良質の
単結晶シリコン膜を形成することができ、従来方法に比
べて格段の効果が得られる。即ち。
Thus, according to the method of this embodiment, a high-quality single-crystal silicon film can be formed on the insulating film 12, and a remarkable effect can be obtained compared to the conventional method. That is.

従来方法において、層間絶縁膜の開口部に傾斜を」った
。これに対し本実施例方法では、眉間絶縁膜が2綿の厚
さであっても多結晶シリコン膜の単結晶化が可能となっ
た。しかも、従来見られた開口部近傍のシリコン膜の剥
離は全く起こらなかった。
In the conventional method, the opening of the interlayer insulating film is sloped. In contrast, with the method of this embodiment, even if the glabella insulating film was 2 cm thick, it was possible to form a polycrystalline silicon film into a single crystal. Furthermore, the peeling of the silicon film near the opening, which has been observed in the past, did not occur at all.

また、本発明者等の実験によれば1層間絶縁膜の厚さが
4μmであっても同様の効果が得られるのが確認された
。開口部径についても、0.8μmφに縮小しても同様
の効果が得られた。さらに、開口部をストライプ状にし
ても同様の効果が得られた。
Further, according to experiments conducted by the present inventors, it has been confirmed that the same effect can be obtained even when the thickness of one interlayer insulating film is 4 μm. Similar effects were obtained even when the diameter of the opening was reduced to 0.8 μmφ. Furthermore, similar effects were obtained when the openings were formed into stripes.

なお1本発明は上述した実施例方法に限定されるもので
はない。例えば、前記エネルギービームとしては、疑似
線状電子ビームの代わシに、スポット状或いは線状の電
子ビームを用いることかでき、さらにレーデビーム或い
はストリップヒータを用いることも可能である。また、
単結晶化する半導体膜は、多結晶シリコンに限るもので
はなく。
Note that the present invention is not limited to the method of the embodiment described above. For example, as the energy beam, a spot or linear electron beam may be used instead of the quasi-linear electron beam, and a Lede beam or a strip heater may also be used. Also,
Semiconductor films that become monocrystalline are not limited to polycrystalline silicon.

非晶質シリコンであってもよい。さらに、シリコンの代
わシに、 Go 、 GaAa 、 GaP 、 In
P等を用いることも可能である。
It may also be amorphous silicon. Furthermore, in place of silicon, Go, GaAa, GaP, In
It is also possible to use P, etc.

また、開口部における半導体膜の凹屋形状、該1を用い
ることができる。同様に保!!膜としては、・I 、上記の絶縁膜は勿論のこと、W、TI、AA等の金°
属膜を用いることも可能である。その他、本発明の要旨
を逸脱しない範囲で1種々変形して実施することができ
る。
Further, the concave shape of the semiconductor film in the opening part 1 can be used. Keep it as well! ! As for the film, in addition to the above-mentioned insulating films, metal films such as W, TI, and AA can be used.
It is also possible to use membranes. In addition, various modifications can be made without departing from the gist of the present invention.

[発明の効果] 以上詳述したように本発明によれば、下層素子に熱的ダ
メージを与えることなく絶縁膜上に単結晶半導体膜を形
成することができ、且つ素子形成領域の増大化及び平坦
化工程の容易化をはかることができる。従って、3次元
ICの製造等に適用して大なる効果が得られる。
[Effects of the Invention] As detailed above, according to the present invention, a single crystal semiconductor film can be formed on an insulating film without causing thermal damage to underlying elements, and the element formation area can be increased and The planarization process can be facilitated. Therefore, great effects can be obtained when applied to the manufacture of three-dimensional ICs, etc.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例方法に係わる単結晶シリコン
の膜の製造工程を示す断面図、第2図は開口部形状を示
す模式図、第3図は従来方法を説明するための断面図で
ある。 11−・・単結晶シリコン基板(半導体基板)、12・
・・シリコン酸化II&(層間絶縁j!K)、13−・
・開口部、14.15・・・多結晶シリコン膜(半導体
M)。 11ζ16・−・保護Ms J y・・・電子ビーム(
エネルギービーム)。 −・1 2′  出願人 工業技術院長 飯 塚 幸 三第1図
FIG. 1 is a cross-sectional view showing the manufacturing process of a single-crystal silicon film according to a method according to an embodiment of the present invention, FIG. 2 is a schematic diagram showing the shape of an opening, and FIG. 3 is a cross-sectional view for explaining a conventional method. It is a diagram. 11-... Single crystal silicon substrate (semiconductor substrate), 12.
・・Silicon oxide II & (interlayer insulation j!K), 13−・
- Opening, 14.15... Polycrystalline silicon film (semiconductor M). 11ζ16...Protection Ms J y...Electron beam (
energy beam). -・1 2′ Applicant Kozo Iizuka, Director General of the Agency of Industrial Science and Technology Figure 1

Claims (4)

【特許請求の範囲】[Claims] (1)半導体基板上に一部開口部を有する絶縁膜を形成
する工程と、上記絶縁膜上及び開口部に露出した半導体
基板上に多結晶若しくは非晶質の半導体膜を堆積し、且
つこの半導体膜を上記開口部において凹型に形成する工
程と、エネルギービームを照射しながら走査することに
より上記半導体膜を単結晶化する工程とを含むことを特
徴とする半導体結晶層の製造方法。
(1) A step of forming an insulating film having a partial opening on a semiconductor substrate, depositing a polycrystalline or amorphous semiconductor film on the insulating film and the semiconductor substrate exposed in the opening, and A method for manufacturing a semiconductor crystal layer, comprising the steps of: forming a semiconductor film in a concave shape in the opening; and converting the semiconductor film into a single crystal by scanning while irradiating an energy beam.
(2)前記多結晶若しくは非晶質の半導体膜を形成する
工程として、まず第1層目の半導体膜を堆積したのち、
化学ドライエッチング法によりこの半導体膜を全面エッ
チングして該半導体膜を前記開口部内に凹型に残し、次
いで再度第2層目の半導体膜を堆積することを特徴とす
る特許請求の範囲第1項記載の半導体結晶層の製造方法
(2) As the step of forming the polycrystalline or amorphous semiconductor film, first, after depositing a first layer of semiconductor film,
Claim 1, characterized in that the entire surface of the semiconductor film is etched by a chemical dry etching method to leave the semiconductor film in a concave shape within the opening, and then a second layer of semiconductor film is deposited again. A method for manufacturing a semiconductor crystal layer.
(3)前記開口部を、点状に列をなして形成することを
特徴とする特許請求の範囲第1項記載の半導体結晶層の
製造方法。
(3) The method for manufacturing a semiconductor crystal layer according to claim 1, wherein the openings are formed in a dotted line.
(4)前記半導体膜の単結晶化工程の前に、前記半導体
膜上に、絶縁膜或いは金属膜を形成することを特徴とす
る特許請求の範囲第1項記載の半導体結晶層の製造方法
(4) The method for manufacturing a semiconductor crystal layer according to claim 1, wherein an insulating film or a metal film is formed on the semiconductor film before the single crystallization step of the semiconductor film.
JP62098731A 1987-04-23 1987-04-23 Method for manufacturing semiconductor crystal layer Expired - Lifetime JPH0793262B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62098731A JPH0793262B2 (en) 1987-04-23 1987-04-23 Method for manufacturing semiconductor crystal layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62098731A JPH0793262B2 (en) 1987-04-23 1987-04-23 Method for manufacturing semiconductor crystal layer

Publications (2)

Publication Number Publication Date
JPS63265419A true JPS63265419A (en) 1988-11-01
JPH0793262B2 JPH0793262B2 (en) 1995-10-09

Family

ID=14227661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62098731A Expired - Lifetime JPH0793262B2 (en) 1987-04-23 1987-04-23 Method for manufacturing semiconductor crystal layer

Country Status (1)

Country Link
JP (1) JPH0793262B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS571225A (en) * 1980-06-03 1982-01-06 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS60234312A (en) * 1984-05-08 1985-11-21 Nec Corp Formation of soi film

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS571225A (en) * 1980-06-03 1982-01-06 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS60234312A (en) * 1984-05-08 1985-11-21 Nec Corp Formation of soi film

Also Published As

Publication number Publication date
JPH0793262B2 (en) 1995-10-09

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