JPS60210830A - Electron beam annealing apparatus - Google Patents
Electron beam annealing apparatusInfo
- Publication number
- JPS60210830A JPS60210830A JP6582784A JP6582784A JPS60210830A JP S60210830 A JPS60210830 A JP S60210830A JP 6582784 A JP6582784 A JP 6582784A JP 6582784 A JP6582784 A JP 6582784A JP S60210830 A JPS60210830 A JP S60210830A
- Authority
- JP
- Japan
- Prior art keywords
- electron beam
- lens
- line
- coil
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02395—Arsenides
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野)
本発明は、電子ビームアニール装置に係わり、・特に一
対の平板電極とこれに印加する高周波電圧によりビーム
形状を線状化する機能を備えた電子ビームアニール装置
に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an electron beam annealing device, and in particular, an electron beam annealing device that has a function of linearizing the beam shape using a pair of flat electrodes and a high frequency voltage applied thereto. Regarding a beam annealing device.
近年、電子ビームやレーザビーム等のエネルギービーム
を利用し、S i 、Ge、GaASを初めとする半導
体試料、AI、MO,W等の金属試料或いは金属化合物
試料を熱処理(アニール)するビームアニール装置が開
発されている。そして、この装置を用い試料を短時間・
局所的にアニールすることにより、半導体デバイスの高
速化、高集積化、多機能化をはかり得、新機能及び新構
造のデバイス実現等の可能性が開けてきている。In recent years, beam annealing equipment has been developed that uses energy beams such as electron beams and laser beams to heat-treat (anneal) semiconductor samples such as Si, Ge, and GaAS, metal samples such as AI, MO, and W, and metal compound samples. is being developed. Using this device, samples can be sampled for a short period of time.
By locally annealing, semiconductor devices can be made faster, more highly integrated, and more multifunctional, opening up the possibility of realizing devices with new functions and new structures.
第1図は従来の電子ビームアニール装置を示す概略構成
図であり、図中11は試料室、12は光学鏡筒、13は
電子銃、14.15はレンズ、16は偏向コイル、17
は試料、18は試料ステージを示している。この装置で
は、電子銃13から放射された電子ビームをレンズ14
.15により集束すると共に、偏向コイル16により上
記ビームを試料17上で走査して試料17のアニール、
例えばエピタキシャル成長や溶融再結晶等を行っている
。FIG. 1 is a schematic configuration diagram showing a conventional electron beam annealing apparatus, in which 11 is a sample chamber, 12 is an optical barrel, 13 is an electron gun, 14.15 is a lens, 16 is a deflection coil, and 17
indicates a sample, and 18 indicates a sample stage. In this device, the electron beam emitted from the electron gun 13 is passed through the lens 14.
.. 15 and scans the beam on the sample 17 using the deflection coil 16 to anneal the sample 17.
For example, epitaxial growth, melt recrystallization, etc. are performed.
しかしながら、この種の装置にあっては次のような問題
があった。即ち、絶縁膜上シリコン躾のの固液界面がビ
ーム進行方向に対して凸型となるようにする必要がある
。しかし、ガウス分布を持つ電子ビームによるアニール
では上記進行方向に対して凸型の固液界面を形成するこ
とはできなかった。なお、図中Aはビーム走査方向、B
は溶融領域、Cは結晶粒界、Dは再結晶化領域をそれぞ
れ示している。一方、従来の電子ビームアニール装置で
は、スポットビーム(溶融ビーム径〜1゜0μm)を連
続的に走査させながら、適当に重ね合わせて全面の7ニ
ールを行うのであるが、この方式によるアニール時間は
長時間を要し、およそ実用的とは言いがたい。However, this type of device has the following problems. That is, it is necessary to make the solid-liquid interface of the silicon layer on the insulating film convex with respect to the beam traveling direction. However, annealing using an electron beam with a Gaussian distribution has not been able to form a solid-liquid interface that is convex in the direction of movement. In addition, in the figure, A indicates the beam scanning direction, and B
indicates a melting region, C indicates a grain boundary, and D indicates a recrystallized region. On the other hand, in conventional electron beam annealing equipment, the spot beam (melting beam diameter ~1°0 μm) is continuously scanned and overlaid appropriately to perform 7 anneals on the entire surface, but the annealing time using this method is It takes a long time and is hardly practical.
これらの問題点を解決する手段として本発明者等は、電
子ビームを該ビームの走査方向(×方向とする)と直交
する方向(Y方向)に高速に偏向してビームを線状化す
る方法を提案した。これは、パ1止−ルに比べてその時
間を著しく短縮することができる。また、線状化ビーム
を組合わせて、或いは高速偏向電極の形状を曲面状とす
ることにより、前記第3図に示す如きビーム進行方向に
対し凸型の固液界面を形成することが可能である。As a means to solve these problems, the present inventors developed a method of linearizing the electron beam by rapidly deflecting the electron beam in a direction (Y direction) perpendicular to the scanning direction (X direction) of the beam. proposed. This can significantly reduce the time compared to a single stop. Furthermore, by combining linear beams or by making the high-speed deflection electrode curved, it is possible to form a solid-liquid interface that is convex in the beam traveling direction as shown in FIG. be.
ところで、このような線状化ビームを用いたアニールに
ついて本発明者等が更に鋭意研究を重ねた結果、次のよ
うな事実が判明した。即ち、線状化するための高速偏向
電極の位置はビーb、の線状化において余り重要でない
と考えていたが、ビームの集束性及び走査性等において
極めて重大な影響を与えるものであることが判った。つ
まり、高速偏向電極の配置位置により、電子ビームの集
束性及び走査性が著しく低下することが判明した。By the way, as a result of further intensive research by the present inventors regarding annealing using such a linearized beam, the following facts were discovered. In other words, although we thought that the position of the high-speed deflection electrode for linearization was not very important in linearizing beam b, it had an extremely important effect on beam focusing, scanning performance, etc. It turns out. In other words, it has been found that the focusing and scanning properties of the electron beam are significantly reduced depending on the placement position of the high-speed deflection electrode.
(発明の目的)
本発明め目的は、ビーム7を線状化することができ、且
つ集束性及び走査性に極めて良好な特性を・、゛前記第
1図において、ビーム線状化のための高速偏向電極を設
ける場合、その取り付は位置としては、偏向コイル16
の下、偏向コイル16と対物レンズ15との間、対物レ
ンズ15より上方等種々考えられるが、本発明者等の実
鋏によれば対物レンズ15より上方ではレンズの収差が
大きくなり、偏向コイル16より上方ではビームの集束
性が悪くなることが判った。そして、偏向コイル16よ
り下方の位置では、レンズの収差が小さくビームの集束
性もよく、また偏向コイル16を使ってのビームの走査
性も極めてスムーズであり、走査ムラ等を効果的に解消
できるのが判った。(Object of the Invention) The object of the present invention is to linearize the beam 7 and to obtain extremely good focusing and scanning characteristics. If a high-speed deflection electrode is provided, its mounting position should be at the deflection coil 16.
There are various possibilities such as below, between the deflection coil 16 and the objective lens 15, above the objective lens 15, etc., but according to the actual scissors of the present inventors, the aberration of the lens becomes large above the objective lens 15, and the deflection coil It was found that the beam convergence deteriorates above 16. Further, at a position below the deflection coil 16, the aberration of the lens is small and the beam focusing property is good, and the scanning performance of the beam using the deflection coil 16 is also extremely smooth, and scanning unevenness etc. can be effectively eliminated. I found out.
本発明はこのような事情に着目してなされたもので、対
極して置かれた2枚の平板電極(高速偏向電極)IOに
高周波のsin波、3角波等によって変動する電圧を印
加することにより電子ビームを高速に偏向して線状ビー
ムとできる電子ビームアニール装置において、上記高速
偏向電極を最終最終段のレンズ若しくはコイルの下方に
設けた高速偏向電極によりビームを線状化することがで
き、且つビームの集束性及び走査性が極めて良好なもの
となる。従って、試料の最適アニールを行うことができ
る。このことは、絶縁膜上の半導体膜を電子ビームアニ
ールにより単結晶化する際に極めて有効であり、3次元
IC等の製造に適用して絶大なる効果を発揮する。The present invention has been made in view of these circumstances, and applies a voltage varying by high-frequency sine waves, triangular waves, etc. to two flat electrodes (high-speed deflection electrodes) IO placed opposite to each other. In an electron beam annealing device that can deflect an electron beam at high speed into a linear beam, it is possible to linearize the beam by using the high-speed deflection electrode provided below the final stage lens or coil. In addition, the beam focusing and scanning properties are extremely good. Therefore, optimal annealing of the sample can be performed. This is extremely effective when a semiconductor film on an insulating film is made into a single crystal by electron beam annealing, and is extremely effective when applied to the manufacture of three-dimensional ICs and the like.
第5図は本発明の一実施例に係わる電子ビームアニール
装置を示す概略構成図である。図中51は真空排気され
た試料室、52は電子光学a筒である。試料室51内に
は移動可能な試料ステージ53が配置され、このステー
ジ53上に試料54が載置されるものとなっている。光
学鏡筒52内には、電子銃55.ビーム集束用の第2レ
ンズ57及び第2レンズ(対物レンズ)57.走査用偏
向コイル58.ビーム線状化用高速偏向電極59がそれ
ぞれ配設されている。そして、電子銃55から放射され
た電子ビームは、レンズ56.57により集束されると
共に、高速偏向電極59により線状化され、また偏向コ
イル58により試料54上で走査され、これにより試料
54が7ニールされるものとなっている。FIG. 5 is a schematic configuration diagram showing an electron beam annealing apparatus according to an embodiment of the present invention. In the figure, 51 is an evacuated sample chamber, and 52 is an electron optical a cylinder. A movable sample stage 53 is arranged within the sample chamber 51, and a sample 54 is placed on this stage 53. Inside the optical lens barrel 52, an electron gun 55. A second lens 57 for beam focusing and a second lens (objective lens) 57. Scanning deflection coil 58. High-speed deflection electrodes 59 for beam linearization are provided respectively. The electron beam emitted from the electron gun 55 is focused by lenses 56 and 57, linearized by a high-speed deflection electrode 59, and scanned over the sample 54 by a deflection coil 58. It is supposed to be completed 7 times.
本実施例においては、ビーム線状化のための^速偏向電
極59は偏向コイル58の下、つまり最終段コイルの下
に置かれている。これにより、本発明の効果が最大に発
揮されている。高速偏向電極59の位置と電子ビームア
ニール特性との関係を調べた一連の実験結果によれば、
まず偏向コイル58と第2レンズ57との開に高速偏向
電極59が設置された場合、ビームの走査上に問題が生
じ、線状ビームの中心と両端とではビーム速度が異なり
、途中でビームが弓なりになることが判った。一方、高
速偏向電極59が第2レンズ57の上に設置された場合
、ビームの集束に問題が生じる。即ち、線状ビームの中
心と両端付近どの集束条件が若干具なり、両方共焦点を
合わせることは極めて困難であった。従って、電子ビー
ムアニールによる絶縁膜上シリコン膜の単結晶化では結
晶成長に不均一が生じ、ひいては素子特性に問題が生じ
た。In this embodiment, the fast deflection electrode 59 for beam linearization is placed below the deflection coil 58, that is, below the final stage coil. This maximizes the effects of the present invention. According to a series of experimental results that investigated the relationship between the position of the high-speed deflection electrode 59 and the electron beam annealing characteristics,
First, if the high-speed deflection electrode 59 is installed between the deflection coil 58 and the second lens 57, a problem will occur in beam scanning, and the beam speed will be different between the center and both ends of the linear beam, and the beam will be distorted in the middle. It turns out that it becomes arched. On the other hand, if the high-speed deflection electrode 59 is placed on the second lens 57, a problem arises in beam focusing. That is, the convergence conditions at the center and near both ends of the linear beam are slightly different, and it is extremely difficult to bring them both confocal. Therefore, when a silicon film on an insulating film is made into a single crystal by electron beam annealing, non-uniform crystal growth occurs, which in turn causes problems in device characteristics.
これに対して、本実施例装置では上記問題は全て解決さ
れるため、電子ビームアニールを最高条件で効率よく行
うことができ、且つアニールの均−性及び再現性の向上
をはかり得た。On the other hand, in the apparatus of this embodiment, all of the above problems were solved, so that electron beam annealing could be performed efficiently under the best conditions, and the uniformity and reproducibility of annealing could be improved.
以下、本装置をMOS−LSIの製造に用いた第6図(
a)に示す如く例えばP型(100)面方位の単結晶シ
リコン基板61上に約1[μTrL]膜厚の5102膜
62を形成し、その上に必要に応じてSiN躾63を形
成する。このSiN躾63は後の工程で多結晶若しくは
非晶質のシリコン層を単結晶化させ易くするためのもの
であり、必ずしも必要でない。次いで、第6図(b)に
示す如<SIN膜6膜上3上えば6000 [人コの多
結晶シリコン層64を被着し、その上に約2000[人
]の5102膜65を形成する。ここで、SiO2膜6
5は後の工程で多結晶シリコン層64を単結晶化させ易
くするためのもので、SiN膜であってもよい。The following is a diagram showing how this device is used in the manufacture of MOS-LSI (Fig. 6).
As shown in a), for example, a 5102 film 62 having a thickness of about 1 [μTrL] is formed on a single crystal silicon substrate 61 of P type (100) plane orientation, and a SiN layer 63 is formed thereon as required. This SiN layer 63 is intended to facilitate single crystallization of a polycrystalline or amorphous silicon layer in a later step, and is not necessarily necessary. Next, as shown in FIG. 6(b), a polycrystalline silicon layer 64 of approximately 6,000 layers is deposited on the SIN film 6, and a 5,102 layer 65 of approximately 2,000 layers is formed thereon. . Here, the SiO2 film 6
Reference numeral 5 is for facilitating single crystallization of the polycrystalline silicon layer 64 in a later step, and may be a SiN film.
次に、前記第5図に示した実施例装置を用い、第6図(
C)に示す如く試料上に電子ビームを照射しシリコン層
64を単結晶化させる。その際、電子ビームの加速電圧
は10 [KelV]ビーム電流は5 [mA]とした
。アニール時に溶融するシリコン層64の幅は約50[
μTrL]であった。ビーム走査を繰返すことにより徐
々に結晶粒が減少融及び再結晶化が極めてスムーズとな
り、熱処理ムラや未処理部分、或いはシリコンの蒸発と
いったトラブルが一切なく、シリコンの単結晶化を効果
的に行うことができた。Next, using the embodiment shown in FIG. 5, the apparatus shown in FIG.
As shown in C), the sample is irradiated with an electron beam to single-crystallize the silicon layer 64. At that time, the acceleration voltage of the electron beam was set to 10 [KelV], and the beam current was set to 5 [mA]. The width of the silicon layer 64 melted during annealing is approximately 50 [
μTrL]. By repeating beam scanning, the crystal grains gradually decrease, making melting and recrystallization extremely smooth, and effectively single-crystallizing silicon without any problems such as uneven heat treatment, untreated areas, or silicon evaporation. was completed.
次に、第6図(d)に示す如<SiO2膜65を除去し
たのち、ビームアニールにより単結晶化したシリコン層
64′をパターンニング【ノて2層目の素子形成領域と
し、周知の技術により素子分離用絶縁膜66を形成する
。続いて、シリコン層り4′上にゲート酸化膜67を介
して多結晶シリコンゲート電極68を形成し、さらにソ
ース・ドレイン領域69a、69bを形成してMOSト
ランジスタを完成する。次いで、第6図(e)に示す如
く全面を絶縁膜70で覆ったのち、A1配線層71a、
71b、71cを形成することにより、MOS−LSI
が完成される。Next, as shown in FIG. 6(d), after removing the SiO2 film 65, the silicon layer 64', which has been single-crystalized by beam annealing, is patterned to form a second layer element formation region using a well-known technique. An insulating film 66 for element isolation is formed. Subsequently, a polycrystalline silicon gate electrode 68 is formed on the silicon layer 4' via a gate oxide film 67, and source/drain regions 69a and 69b are further formed to complete a MOS transistor. Next, as shown in FIG. 6(e), after covering the entire surface with an insulating film 70, an A1 wiring layer 71a,
By forming 71b and 71c, MOS-LSI
is completed.
H筒の構成は第5図に何等限定されるものではな、・′
jり°、高速偏向電極を最終段レンズ若しくはコイルよ
り試料側に設置したものであれば、仕様に応じて適宜変
更可能である。例えば、高速偏向電極を曲面状に形成し
て曲面状ビームを形成し、ビーム進行方向に対し固液界
面が凸型となるようにしてもよい。さらに、2つの光学
鏡筒を用い、直線状ビームを組合わせてr<Jの字型ビ
ームを形成するようにしてもよい。また、高速偏向電極
に印加する電圧はsin波や3角波等に限定されるもの
ではなく、試料上でのビーム走査速度に対して十分高い
高周波であればよい。その他、本発明の要旨を逸脱しな
い範囲で、種々変形して実施することができる。The configuration of the H cylinder is not limited to that shown in Figure 5.
However, as long as the high-speed deflection electrode is placed closer to the sample than the final stage lens or coil, changes can be made as appropriate depending on the specifications. For example, the high-speed deflection electrode may be formed into a curved surface to form a curved beam so that the solid-liquid interface is convex with respect to the beam traveling direction. Furthermore, two optical barrels may be used to combine the linear beams to form a beam r<J. Furthermore, the voltage applied to the high-speed deflection electrode is not limited to a sine wave, a triangular wave, etc., and may be any high frequency voltage that is sufficiently high relative to the beam scanning speed on the sample. In addition, various modifications can be made without departing from the gist of the present invention.
第1図は従来の電子ビームアニール装置を示す概略構成
図、第2図は従来のスポットビームによる再結晶化にお
ける結晶粒界の現れ方を示す模式に係わる電子ビームア
ニール装置を示す概略構成:・る。
51・・・試料室、52・・・電子光学鏡筒、53・・
・試料ステージ、54・・・試料、55・・・電子銃、
56・・・第1の集束レンズ、57・・・第2の集束レ
ンズ(対物レンズ)、58・・・ビーム走査用偏向コイ
ル、59・・・高速偏向電極。
出願人 工業技術院長 用田裕部
第1図
第2図
第4図
(a)
(b )
第6図
第6図Fig. 1 is a schematic configuration diagram showing a conventional electron beam annealing device, and Fig. 2 is a schematic configuration diagram showing an electron beam annealing device related to a schematic diagram showing how grain boundaries appear in recrystallization using a conventional spot beam. Ru. 51... Sample chamber, 52... Electron optical column, 53...
・Sample stage, 54...sample, 55...electron gun,
56... First focusing lens, 57... Second focusing lens (objective lens), 58... Deflection coil for beam scanning, 59... High speed deflection electrode. Applicant: Director of the Agency of Industrial Science and Technology Hirobe Yoda Figure 1 Figure 2 Figure 4 (a) (b) Figure 6 Figure 6
Claims (1)
れた電子ビームを集束するレンズ系と、上記ビームを試
料上で走査する走査用偏向系と、上記ビームを高速偏向
して線状化する高速偏向電極とを具備し、前記高速偏向
電極は最終段のレンズ若しくはコイルより前記試料側に
起重されたものであることを特徴とする電子ビームアニ
ール装置。An electron gun that emits an electron beam, a lens system that focuses the electron beam emitted from the electron gun, a scanning deflection system that scans the beam on a sample, and a scanning deflection system that deflects the beam at high speed to linearize it. 1. An electron beam annealing apparatus comprising: a high-speed deflection electrode, the high-speed deflection electrode being raised closer to the sample than a final stage lens or coil.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6582784A JPS60210830A (en) | 1984-04-04 | 1984-04-04 | Electron beam annealing apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6582784A JPS60210830A (en) | 1984-04-04 | 1984-04-04 | Electron beam annealing apparatus |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60210830A true JPS60210830A (en) | 1985-10-23 |
Family
ID=13298245
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6582784A Pending JPS60210830A (en) | 1984-04-04 | 1984-04-04 | Electron beam annealing apparatus |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60210830A (en) |
-
1984
- 1984-04-04 JP JP6582784A patent/JPS60210830A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7176490B2 (en) | Semiconductor device | |
US7652286B2 (en) | Semiconductor device and semiconductor device producing system | |
JP3778456B2 (en) | Method for manufacturing insulated gate thin film semiconductor device | |
KR100388731B1 (en) | Method of manufacturing a semiconductor device | |
US7466735B2 (en) | Manufacturing method of semiconductor device | |
WO2013140764A1 (en) | Semiconductor device and method for manufacturing same | |
JPH1074697A (en) | Polycrystalline silicon film, manufacture thereof, manufacture of thin film transistor and liquid crystal display device, and laser annealing device | |
JPH09129573A (en) | Method and apparatus for laser annealing | |
JPS60210830A (en) | Electron beam annealing apparatus | |
JPH0697073A (en) | Formation of polycrystalline silicon layer and polycrystalline silicon thin film transistor using the same | |
JP3630593B2 (en) | Semiconductor device, method for manufacturing semiconductor device, and liquid crystal display device | |
JP2000111950A (en) | Manufacture of polycrystalline silicon | |
JP3857085B2 (en) | Thin film transistor and manufacturing method thereof | |
JP4627135B2 (en) | Semiconductor device production method | |
JP2003257865A (en) | Semiconductor device and production system thereof | |
JP3842083B2 (en) | Thin film transistor, manufacturing method thereof, and display device | |
JP3767727B2 (en) | Method for manufacturing semiconductor device | |
JPH0132628B2 (en) | ||
JPS60152017A (en) | Electron beam annealing device | |
JPS61187222A (en) | Manufacture of single-crystal layer of semiconductor | |
JP2003100652A (en) | Apparatus and method for irradiation with linear pulsed laser | |
JPS62190716A (en) | Manufacture of semiconductor thin film crystal layer | |
JPH0136970B2 (en) | ||
JPS5981851A (en) | Electron beam annealing device | |
JPH0287519A (en) | Manufacture of single crystal semiconductor thin film |