JPS60150112A - Insulated gate type field effect semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the constant voltage of high accuracy by deciding the threshold voltage of a MISFET with a gate electrode containing no impurity. CONSTITUTION:Equations I and II show the threshold voltage of a MISFET having a gate electrode which contains n and p type impurities. While an equation IIIshows the threshold voltage with the gate electrode including no impurity. An equation IV is satisfied among these threshold values. The MISFETs Q1 and Q2 contain a pinip and pipip type gate electrodes respectively and connected in series. The threshold values of the FETs Q1 and Q2 are shown by equations Vand VI from the equation IV. Then the difference is obtained between the threshold values of FETs Q1 and Q2 to obtain the voltage corresponding to a silicon energy gap, i.e., the difference of the work function among an n<+> gate electrode of the FETQ1, an (i) electrode of the FETQ2 and each substrate. This energy gap has an extremely small level of dependence on the production conditions and the ambient temperature conditions. Thus the constant voltage can be obtained with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect semiconductor device.

For example, an insulated gate field effect transistor (insulated gate field effect transistor) having a gate electrode of a different IK, 4;

An object of the present invention is to obtain a highly accurate constant voltage that is less susceptible to manufacturing variations and temperature conditions, and to
An object of the present invention is to provide an insulated gate field effect semiconductor device composed of FETs.

- This invention focuses on the fact that the energy gap in silicon has little dependence on manufacturing conditions and ambient temperature conditions, and uses this to obtain a constant voltage.

First, an MI with a pt n-type electrode devised by the present inventor
The 5FET will be explained.

FIG. 1 is a cross-sectional view of an element structure showing an embodiment for extracting the energy gap of silicon as a voltage signal. The device shown here is an enhancement type p-channel MISFET (1) formed on an n-type semiconductor body substrate (1).
Q+) and (Q,), each of which uses a conductor layer composed of a polysilicon layer containing semi-integral impurities of different conductivity types. That is, as shown in the figure, M is selectively deposited on the n-type semiconductor substrate (1).
P-type semiconductor regions (4, 5) constituting the source, drain, and gate of the ISFET are formed, and a gate insulating film (5) and this Polysilicon (
When forming a polycrystalline silicon (polycrystalline silicon) layer, one MIS
A semiconductor impurity (n
The polysilicon layer for forming the gate (6) of the other MISFET' (Qt) contains a semiconductor impurity (p type) of the conductivity type opposite to that of the substrate.
T (QI - Qt).

The respective threshold voltages (Vthq, .VthQt) of the MISFETs (Ql, Qt) having the above configuration can be calculated from the following equations (11 and (21).

Here, φMntφMp is each MISFET (
Ql , Qt ) is the work function between the gate and the substrate, COX is the gate capacitance per unit area, Qss is the surface charge, and QD is the charge in the substrate depletion layer.

If we calculate the difference in the threshold voltages of both MISFETs (QI, Qt), we get the difference in work function (φMp−φMJI), which is the first term on the right side of equations (11 and (2)), which is the energy gap of silicon. This voltage can be extracted as a voltage corresponding to the energy gap of silicon, so there is no manufacturing variation and there is extremely little temperature dependence.
The reason for the large variation in the threshold voltage of ET is given by the formula (I
), (This is because the second term (Qss/Cox) and the third term (QD/C0X) on the right side of 2+ vary depending on the manufacturing conditions. In this example, the above M I S F E
By manufacturing T (QI, Qt) under the same conditions, the second and third terms on the right side of equation (11, +21) are approximately the same as -
By calculating the difference, these are offset and the amount equivalent to the energy gap is used as the output voltage.

Next, FIG. 2, which is an embodiment of the present invention, shows an MI 5FET whose threshold voltage is determined by a gate electrode that does not contain impurities.
is used to extract a voltage corresponding to the silicon energy gap, which is the difference in work function between the n-type and i-type gate electrodes and their respective substrates. The threshold voltage of a MISFET having a gate electrode containing p-type and n-type impurities is given by equations (1) and (21).Similarly, for a MISFET whose gate electrode does not contain impurities,
ET17)L threshold voltage Vth(i))L, and φM
i is the work function between the gate and substrate of a MISFET whose gate electrode does not contain impurities. Here, between each threshold voltage, Vth(p) <Vth(i) <Vt
There is a relationship between b(.)...song...song...song (6). Furthermore, the MISFET (Ql.

If you have a good idea about the threshold voltage of Q,), MISFE
T(Q,) is a MISFET with p, i, n, i, p type gate electrodes, and MISFET T(Q,) is p
+I+1)+l+MISFE with p-type gate electrode
Let T be connected to a rectangular array. In this case M
The threshold voltages of the ISFET (QI) and MISFET (QI) are determined by the one with the widest threshold voltage among the MISFETs connected in series. From the relationship of equation (6), MISFET (Q, ) and MISFET (Q
The threshold voltage of I) is determined by the threshold voltage of a MISFET having an n-type gate electrode and a MISFET having an i-type gate electrode, respectively. Yacht Figure 2 K Oi”'CV thQ+ + Vth Q
t&”J-1.

Furthermore, MI S FET (Ql'-Q
! ) By taking the difference in threshold voltage of
), the second and third terms on the right side of (8) are canceled out, □,
What remains as the differential frost pressure is a voltage of approximately 0.55 V corresponding to the silicon energy gap, which is the difference in work function between the n+ gate electrode of MISFETQl, the i gate electrode of MISFETQz, and their respective substrates.

Next, the MISFET (Ql, Ql) of the above 41 components
The detection and pressure generation circuit using the following will be explained in detail.

FIG. 3 shows a firefly 1 pressure generation circuit to which the present invention is applied.

Since the conductive layer constituting the substrate and the gate are made of the same conductivity type semiconductor impurity, the drain, in, and gate of the MI S'FET (Ql) with the smaller work function are connected, and the load is It is supplied to the power supply voltage via a resistor (R1). On the other hand, since the substrate and the conductive layer constituting the gate are composed of semiconductor impurities of opposite conductivity type, the gate of the MISFET (Qy), which has a larger work function, is made common to the gate of the MISFET (Ql), and the MISFET ( Ql ) source and this MISFET
(Ql) is connected to the drain, and a load resistor (R7) is provided to the drain. The source is grounded to provide a reference voltage. In this circuit, the above MISFE
The gate of T(Ql) (gate of MISFETQ) has the threshold voltage (VthQt) of MISFET(Qy).
), the source of the MISFET (Qt) has the threshold voltage (V
thQ, ) minus the threshold voltage (VthQI) of MISFET (Qt)
hQI) is obtained. Note that in order to meet the above conditions, K and load resistance (Rt-R) are MISFETs (Qt, Ql
) should be sufficiently larger than the on-resistance of

In this embodiment circuit, since the drain current of MISFET (Q) is supplied from MfSFET (Ql), the load resistor (R1) may be omitted as shown in FIG.

□ Also, since the source potential of MI'SF E"T' (Ql) becomes the above output voltage E (Vout),
When the source and the substrate are at the same position of 111, lx (the so-called substrate effect occurs. Therefore, in order to eliminate the influence of this substrate effect on the output voltage, the above il<MI Sv'ET,
By configuring (Ql - Q, *) in a well region formed on a semiconductor substrate, the source and channel region of each MISFET (Ql, Qt) are made to have the same potential as shown in Fig. 4. It is preferable to do so.

M I S F E T (Ql , Ql
) may be applied to the circuit shown in FIG.

For example, when the semiconductor substrate is made of an n-type semiconductor, the well is to be a p-type semiconductor region, so the embodiment shown in FIG. 2 is formed in this region. N-channel type MI 5FET opposite to
(Ql, Ql) constitutes a circuit.

This embodiment is stepped when obtaining a constant voltage output with higher accuracy, and as mentioned above, the output constant voltage is approximately 0.55V.
The substrate effect in the degree M, I S F ET (Qt) is small, and therefore, the circuit of FIG. 3 can also provide a constant voltage neutral force with high accuracy, which is not a problem in practice.

FIG. 4 is a circuit diagram showing an example of a dynamic type constant-□positive output circuit. This circuit connects the gate and drain, and biases it through load resistors (R, , R1). MI 5
The above gate of FET (Ql - Qt).

A capacitor (C) is provided between the drain terminals, and the above MIS
The purpose is to obtain an output by accumulating the difference in the threshold voltage of the FET (Qs = Qt) in a capacitor. In other words, the MISFET (Qt
A MISFET (Q, ) driven by a clock pulse (φ) is provided between the gate and source of the MISFET
The respective load resistances (R,, R,) are made sufficiently large for the on-resistance of E T (,,Ql 9.Qt ), and the on-resistance of the MI5FET (Ql -Q,) is set to [, By making the on-resistance of MISFET (Ql) sufficiently small, as shown in the operating waveform diagram shown in Figure 6,
The clock pulse becomes low level and the MISFET (Q
When s) is turned on, both MI 5FETs (Qt,
Qt ) drain 711i2 voltage (threshold voltage vthQ
,,VthQ,) difference - (VthQ, 1VthQ,) is near 7te7? (C) (1') MI S at the other end
Obtained from the drain of FET (Qt). By sampling at this timing (φ), a constant voltage output similar to that of the circuit described above can be obtained.

Since the constant voltage generation circuit described above can be configured with MI 5FETs, it can be widely used as an electronic quick-clock device configured with MISFETs or as various constant voltage sources in monolithic annual circuits such as electronic watches. , for example, the seventh
As shown in the figure, a constant voltage generation circuit ((L, Qt, R
) is input as a reference voltage to one side of the voltage comparator circuit (7), and the power supply voltage (VDD) is connected to the dividing resistor (R, ., R
In the case of 2), a battery life detection circuit can be obtained by dividing the voltage in step II) and applying it to the other input.Since the battery voltage does not drop rapidly, the constant voltage generation circuit is The pressure circuit and the voltage comparison circuit may be driven by clock pulses, and if constant consumption and pressure output are not required, the constant voltage generation circuit may be clock-driven as described above.

The present invention is not limited to the above embodiments, but can be applied to an MI of the above configuration.
The circuit that calculates the difference in threshold voltage of the 5FET (Qt - Qt) can be modified in various ways, and any specific circuit may be used.

[Brief explanation of the drawing]

Figure 1 shows a MISFET with a pen-type gate electrode devised by the present inventor, Figure 2 is a structural cross-sectional view of a MISFET showing one embodiment of the present invention, and Figures 3 to 5 respectively. A circuit diagram of a constant voltage generation circuit to which this invention is applied, FIG. 6 is an operating waveform diagram of the circuit of FIG. 5, and FIG. 7 is a circuit diagram showing an example of a case where this invention is applied to a battery life detection circuit. It is. (1)...Semiconductor substrate, (2)...Gate insulating film,
(3)...Field insulating film, (4,5)...Source, drain, (6,6')...Gate electrode, (7)
...Voltage comparison circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] 1. A semiconductor substrate having one 21' conductive region of a conductivity type opposite to that of the semiconductor substrate on the surface of the semiconductor substrate, and a thin conductive region between the two conductor regions and on the surface of the semiconductor substrate. MISI pad 1 with gate electrode extending from polysilicon via edge 11'
In an insulated gate type frost, field effect semiconductor device having a field effect semiconductor device having an insulated gate frost of 1゛, the threshold voltage of 't' is determined by the gate frost pole which does not contain impurities or substances. Insulated gate lightning, field effect semiconductor device.