JPS60149175U - Package for multi-stage hybrid integrated circuits - Google Patents
Package for multi-stage hybrid integrated circuitsInfo
- Publication number
- JPS60149175U JPS60149175U JP3540384U JP3540384U JPS60149175U JP S60149175 U JPS60149175 U JP S60149175U JP 3540384 U JP3540384 U JP 3540384U JP 3540384 U JP3540384 U JP 3540384U JP S60149175 U JPS60149175 U JP S60149175U
- Authority
- JP
- Japan
- Prior art keywords
- component
- fixed
- side plate
- hybrid integrated
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Combinations Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図aは従来の混成集積回路用パッケージの概略斜視
図、bは同断面図、第2図は、従来の混成集積回路用パ
ッケージを積み重ねた際の概略斜[親図、第3図はこの
考案の一実施例を示すもの、 で、同図a、 bは第
1の部品、c、dは第3の部−品、e、fは第2の部品
のそれぞれ概略斜視図と断面図、第4図aは第9図を組
み合せる前の概略斜視図、bはその断面図、第5図aは
第4図を組み合せた概略斜視図、bは第1の部品と第2
の部。
° 品の間に多数の第3の部品を組み合せた概略斜視
図、Cは第1の部品と第2の部品を組み合せた概略斜視
図である。図中1及び1°a〜1dは混成集 ・積回
路基板、2は外部接続リード、3は従来の混成集積回路
用パッケージ、4は底板、5,6は側板、7(よこの考
案における第1の部品、8は第2の部品、9は第3の部
品である。なお、図中、同一あるいは相当部分には同一
符号を付しである。Fig. 1a is a schematic perspective view of a conventional hybrid integrated circuit package, b is a sectional view thereof, and Fig. 2 is a schematic perspective view of a conventional hybrid integrated circuit package when stacked. This figure shows an embodiment of this invention, in which figures a and b are first parts, c and d are third parts, and e and f are schematic perspective views and cross-sectional views of the second parts, respectively. , FIG. 4a is a schematic perspective view before combining FIG. 9, b is a sectional view thereof, FIG. 5a is a schematic perspective view combining FIG. 4, and b is a schematic perspective view of the first part and second part.
Department. C is a schematic perspective view of a combination of a number of third parts between the products; C is a schematic perspective view of a combination of the first part and the second part; In the figure, 1 and 1°a to 1d are hybrid integrated circuit boards, 2 is an external connection lead, 3 is a conventional package for hybrid integrated circuits, 4 is a bottom plate, 5 and 6 are side plates, and 7 (the first one in Yoko's invention) 1 is a part, 8 is a second part, and 9 is a third part. In the drawings, the same or corresponding parts are given the same reference numerals.
Claims (1)
外部接続リードを有する側板が固定された第1の部品と
、第1の部品の底板と同じ大きさの底板に、第1の部品
と異る2辺から上面方向に垂直に外部、リードを有する
第1の部品と同じ高さの側板が固定された第2の部品と
、第1の部品の底板の、第1の部品の側板が固定された
反対の面で、その側板が固定された辺と異る2辺に、第
2の部品の側板と同じ側板が固定された第3の部品とで
構成され、第1の部品と第2の部品との間に1個以上の
第3の部品を組み合せたことを特徴とする、多段式混成
集積回路パッケージ。 ゛A first component, in which a side plate having external connection leads is fixed to a rectangular bottom plate perpendicularly to the bottom surface from two adjacent sides thereof, and a bottom plate having the same size as the bottom plate of the first component; a second component to which a side plate of the same height as the first component having a lead is fixed to the outside perpendicularly to the upper surface direction from two sides different from that of the first component; and a side plate of the first component of the bottom plate of the first component. The side plate of the second part and the third part have the same side plate fixed on two sides different from the side to which the side plate is fixed, on the opposite side to which the side plate is fixed, and the second part and the third part are fixed. A multi-stage hybrid integrated circuit package, characterized in that one or more third components are combined with the second component.゛
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3540384U JPS60149175U (en) | 1984-03-13 | 1984-03-13 | Package for multi-stage hybrid integrated circuits |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3540384U JPS60149175U (en) | 1984-03-13 | 1984-03-13 | Package for multi-stage hybrid integrated circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60149175U true JPS60149175U (en) | 1985-10-03 |
Family
ID=30539647
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3540384U Pending JPS60149175U (en) | 1984-03-13 | 1984-03-13 | Package for multi-stage hybrid integrated circuits |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60149175U (en) |
-
1984
- 1984-03-13 JP JP3540384U patent/JPS60149175U/en active Pending
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