JPS60146525A - Multi-frequency clock generator - Google Patents

Abstract

PURPOSE:To use a device with a slow operating speed by providing a single oscillating source, a prime number frequency division circuit and a digital multiple circuit connected in cascade to the prime number frequency division circuit. CONSTITUTION:An output of a crystal oscillator 1' outputting a frequency of 1/2 of an original frequency F0 is amplified by a buffer 10, inverted by an inverter buffer 11, an output of the buffer 10 is frequency-divided by 1/3 at a 1/3 frequency division counter 3, frequency-divided by 1/5 at a 1/5 frequency division counter 4, the 1/3 frequency-division and 1/5 frequency division output is multiplied digitally by multiplication circuits 12, 13 comprising D flip-flops 14, 17, shift registers 15, 18 and an AND/OR circuits 16, 17. Thus, a 1/2 frequency division output 31, a 1/3 frequency division output 32 and a 1/5 frequency division output 33 to the original oscillating frequency F0 are obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a multi-frequency clock generator that generates a plurality of synchronized clocks having different frequencies.

(Prior Art) Generally, digital circuits often require a large number of mutually synchronized clocks. If all of these clocks need to be generated synchronously from a single oscillation source, and the frequencies of the desired generated clocks are prime numbers, a digital circuit can divide the frequencies to generate all the desired clocks. For generation, the frequency of a single oscillation source must be the least common multiple of the frequencies of all generated clocks. Therefore, as the types of generated frequencies increase and each frequency becomes higher, the least common multiple becomes dramatically higher, and the oscillation frequency F. is also getting higher. This oscillation frequency F. If the value becomes high, the selection range of devices that can be used for the oscillation source and the frequency divider circuit is limited, and it becomes impossible to implement it unless the circuit is extremely complex.

When this oscillation frequency Fo requires high precision and high reliability, a crystal resonator is used as the oscillation source, but the oscillation frequency F. It is not possible to use a crystal resonator whose oscillation frequency F exceeds the upper limit of the fundamental vibration frequency of the crystal resonator. A problem arises in that it becomes difficult to obtain devices that can directly divide the frequency.

FIG. 1 is a block diagram of a conventional clock generator. This circuit divides the output of a crystal oscillator 1 by a divide-by-2 counter 2, a divide-by-3 counter 3, and a divide-by-5 counter 4, and outputs a divide-by-2 output and a divide-by-3 output from output terminals 31, 32, and 33, respectively. It extracts the frequency output and the frequency divided by 5 output. In this case, the oscillation frequency F of the crystal oscillator 1 is 74.
13 MHz, the output frequency from each output terminal 31, 32.33 is 37.065 MHz.

24.71 MHz and 14.825 MHz clocks are available. Since it is difficult for this crystal oscillator 1 to operate at an oscillation frequency Fo of 100 MHz or more, it is difficult to operate the crystal oscillator 1 with an oscillation frequency Fo of 100 MHz or more.
, 7, it was difficult to obtain a clock with a frequency of 50 MHz, 33 MHz, or 25 MHz or higher.

Furthermore, in order to operate with such a high frequency circuit, it was necessary to use a high speed device such as an ECL.

(Object of the Invention) An object of the present invention is to provide a multi-frequency clock generator that solves these problems and can obtain a divided output with a high clock frequency or use a device with a slow operating speed. There is a particular thing.

(Structure of the Invention) The multi-frequency clock generator of the present invention includes: an oscillation circuit that generates a clock of a predetermined oscillation frequency; a plurality of prime number frequency dividing circuits that divide the clock of this oscillation circuit by a plurality of prime numbers, respectively; It is configured to include a digital multiplier circuit that adds the divided outputs of these prime frequency dividing circuits and the outputs obtained by delaying each of these divided outputs by a predetermined time, and outputs a signal that is substantially multiplied by the divided output. .

(Embodiment) FIG. 2 is a block diagram of an embodiment of the present invention, in which the original oscillation frequency is F. This is a circuit with half of the conventional one. In this embodiment, the original frequency is F. a crystal oscillator 1' of 1/2 of
Amplify the output of this crystal oscillator r.

A buffer 10 and an inverter buffer 11 that invert, a divide-by-3 counter 3 and a divide-by-5 counter 4 that divide the output of the buffer 10 by 3 and 5, respectively, and the outputs of the divide counters 3 and 4, respectively. It is composed of multiplier circuits 12 and 13 that perform digital multiplication. This multiplier circuit 12α has a D-flip-flop 14 (1η), a shift register 150 frame, and an AND/OR gate 16.
The AND/OR gate 16α is composed of αη and
It is composed of AND gates 20, 21 (23, 24) and OR gate 22 (25).

FIG. 3 is a waveform diagram of each part explaining the operation of FIG. 2. In this example, the original oscillation frequency F. i74.13000M
Hz, the oscillation frequency of crystal oscillator 1' is 374)
6500 MHz (duty cycle 50%) is sufficient, and this can be used as a frequency-divided clock. Therefore, the buffer 10 is connected to the divide-by-2 output terminal 31.
All you have to do is take out the output as is. Further, these circuit elements can be realized using Schottky TTL elements.

Next, the operation of this embodiment will be explained.

The output clock of the crystal oscillator 1' is supplied by a buffer 10 as an in-phase clock signal 101 to a D-flip-flop 14.17 and an AND/OR gate 16.17, and an inverted clock signal which is inverted by an inverter buffer 11. 102 to a shift register 1548 and an AND/OR gate 16.17.

The clock signal 101 is frequency-divided by 3 by the 3-frequency divider counter 3, resulting in a clock signal 110 having a pulse width Tw of about 26-98n(8). This clock signal 110 is.

The D-flip-flop 14 latches and outputs the clock signal 101 to become a delay signal 111.

Similarly, the clock signal 110 is output by 1 to the delay signal 111 by the clock signal 102 in the shift register 15.
．． It is shifted by 57w and output, and the delay signal 112
becomes. This delay signal 111 is applied to the AND gate 20
and the clock signal 102, and the pulse width is T w
/2 becomes the signal 113. Similarly, delay signal 1
12 is also connected to the clock signal 101 by the AND gate 21.
For ND', the signal 114 has a pulse width of Tw/2. These signals 113 and 114 are input to the OR gate 22, and a clock 115 which is doubled with respect to the signal 110 can be obtained at the output terminal 32. This doubled clock negative 5 is the apparent original frequency F. When viewed from above, it becomes a 3-frequency divided clock of this original oscillation Fo.

Further, the 5-divided clock 125 for the original oscillation F can be realized by the 5-divided counter 4 and the multiplier circuit 19 in the same manner as the 2.3-divided clock. In this case, the delay signal 122 is 2 with respect to the delay signal 121.
．． The circuit operates in the same way as the 3-frequency divided clock circuit, except that the output is lost at a timing shifted by 5 Tw.

As explained in this embodiment, by configuring the circuit in this manner, the operating speed of the constituent devices can be reduced to half.

In the present invention, the original swing F. The original oscillation F as the clock frequency of a single oscillator source if does not exceed 100 MHz.

By using a frequency divided by the multiplier of the multiplier circuit, it is possible to widen the selection range of devices that can be used as the oscillation source and the frequency divider circuit.

Specifically, a crystal oscillator can be used as an oscillation source, and a high-speed device such as an ECL can be used as a frequency dividing circuit device, but the 9-7 key TT can be used without using an ECL.
It is also possible with L etc. In short, the device element used can be replaced with a slower one whose operating speed is inversely proportional to the multiplier.

(Effects of the Invention) As explained above, the present invention uses a single oscillation source, a prime frequency divider circuit, and a digital multiplier circuit connected in cascade to the prime frequency divider circuit to create an apparent simple structure. The frequency twice the oscillation frequency of one oscillation source is the original mF.

It becomes possible to simultaneously generate desired frequency clocks.

In addition, from the perspective of the device elements that make up the circuit, the oscillation frequency of a single oscillation source is 0/2 of the apparent oscillation frequency, so replacing it with a device element that operates at half the operating speed and creating the desired clock generator. This has the effect of making it possible to achieve the following. Note that when the same high-speed device element is used, it is possible to output twice the high-speed clock frequency.

Note that in this embodiment, clock frequencies related to prime numbers 43 and 5 were generated, but it is clear that clock frequencies can be generated for other prime numbers as well.

Furthermore, in this embodiment, a multiplier circuit that doubles the frequency by applying a delay of 1/2 of the frequency divided period using a shift register has been described. A tripler circuit can also be obtained by adding 2/3 delayed circuits.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional multi-frequency ripple generator.
Fig. 2 is a block diagram of one embodiment of the present invention, and Fig. 3 is a block diagram of an embodiment of the present invention.
FIG. 3 is a timing chart diagram of each part in the figure. In the figure,
1. f...Crystal oscillator, 2...2 frequency division counter, 3...3 frequency division counter, 4...
...5 frequency division counter, 10...Buffer, 11
...Inverter buffer, 12.13...
・・Multiplier circuit, 14゜17・・・・・・D-flip・
Flo, Pu, 15.18・Old...shift register, 16.
19...AND fist OR gate, 20.21.2
3.24...AND gate, 22.25...
. . . OR gate, 31.32.33 . . . Output terminals. 1 piece of grass, 2 pieces of grass, -izo I47 770 pieces

Claims (2)

[Claims] (1) An oscillator circuit that generates a clock with a predetermined oscillation frequency, a plurality of prime number frequency divider circuits that divide the clock of this oscillation circuit into multiple prime numbers, and the divided outputs of these prime number frequency divider circuits and these A multi-frequency clock generator including a digital multiplier circuit that adds the frequency-divided outputs and outputs each delayed by a predetermined time and outputs a signal that is substantially multiplied by the frequency-divided outputs. (2) The multi-frequency clock generator according to claim 1, wherein the delayed predetermined time is 1/2 of the frequency division period, and the multiplier of the multiplier circuit is 2.