KR100265787B1 - Clock division circuit - Google Patents

Abstract

PURPOSE: A clock divide circuit is provided to decrease skew time by coinciding the timing of a leading edge and trailing edge of a first clock pulse and second clock pulse used for driving a peripheral device. CONSTITUTION: A clock divide circuit includes an oscillator(203), a first selector(205), a second selector(206), a divider(204) and a delay unit(207). The first selector(205) is formed of a first multiplexor having a selection control terminal which receives an output of the oscillator(203) and two input terminals which are connected with a power signal of a high level and a ground signal of a low level. The second selector(206) is formed of a second multiplexor having a selection control terminal which receives an output of the oscillator(203) and two input terminals which receive an output signal of the divider(204) and an output signal of the delay unit(207) and outputs a second clock signal in synchronization with the first clock signal. The divider(204) is formed of a first D-flipflop having a clock terminal which received an output of the oscillator(203) and an input terminal which received a negative output signal. The delay unit(207) is formed of a second D-flipflop having an input terminal which receives an output signal of the divider(204) and a clock terminal which receives an output of the oscillator(203). The oscillator(203) outputs an oscillation clock signal having a certain frequency.

Description

Clock divider

1 is a block diagram of a conventional clock division circuit.

2 is a block diagram of a clock division circuit according to the present invention.

3 is a waveform diagram of each part.

* Explanation of symbols for main parts of the drawings

203: Oscillator 204: Divider

207: delay 205: first selection means

206: second selection means

The present invention relates to a clock divider circuit, and more particularly, to a circuit for dividing and outputting an oscillating clock pulse output from an oscillator.

When configuring various control systems using a microprocessor, a predetermined number is synchronized with the first clock pulse to operate peripheral elements in addition to the first clock pulse used in the central processing unit (CPU). The second clock pulse divided by is obtained through an oscillator, and the clocks divided by the clock are obtained through a clock divider circuit composed of a predetermined number of delays.

FIG. 1 shows a conventional clock divider circuit, which is composed of an oscillator 103 and one delayer, and an oscillation clock pulse output from the oscillator 103 is used as the first clock pulse in the CPU or the like. The second clock pulse whose output is divided by two is used to drive the peripheral elements. In particular, the delay unit inputs the oscillation clock pulse output from the oscillator 103 to its own clock terminal as shown in the drawing, and its own input terminal feeds back its own negative output signal. The flip flop 104 is comprised.

However, the clock divider circuit configured as described above is warped because the oscillation clock pulses output from the oscillator 103 and the times where the leading edge and the trailing edge of the output signal of the D flip-flop do not coincide. (skew) There is a problem that the period of appearance is long. In other words, the period of time for stable operation is shortened.

Accordingly, the present invention is to solve the above problems, the rising edge (leading edge) and the falling edge (trailing edge) of the first clock pulse used as the system clock and the second clock pulse used to drive the peripheral device occurs. It is an object of the present invention to provide a clock divider circuit which can reduce the period in which skew occurs by matching the times.

In order to achieve the above object, the clock division circuit of the present invention includes: an oscillator for outputting an oscillating clock pulse having a predetermined frequency;

A divider for dividing an oscillating clock pulse output from the oscillator;

A delay unit for delaying and outputting the output signal of the frequency divider for half a period of a clock pulse in synchronization with the oscillation clock pulse output from the oscillator;

First selecting means for outputting a first clock pulse by alternately selecting a lower one of a "high" level signal and a "low" level signal according to an oscillation clock pulse output from the oscillator;

A second selection means for outputting a second clock pulse by alternately selecting one of the output signal of the divider and the output signal of the delayer according to the oscillation clock pulse output from the oscillator and having different frequencies. The edge skew of the first clock pulse and the second clock pulse may be minimized.

Next, the present invention will be described in more detail with reference to the accompanying drawings.

2 is a block diagram of a clock divider circuit according to the present invention, which includes an oscillator 203, a first selecting means 205, a second selecting means 206, a divider 204, and a delay unit 207. FIG. It is composed. In particular, the first selecting means 205 inputs the output of the oscillator 203 to its own selection control terminal, and the two input terminals have a power signal indicating a "high" level and a ground signal indicating a "low" level. And a second selection means 206 inputs the output of the oscillator 203 to its own selection control terminal, and the two input terminals of the output signal of the divider 204 and the two input terminals. And a second multiplexer for inputting the output signals of the delayers 207, respectively, in synchronization with the first clock pulses, and outputting the divided second clock pulses. The divider 204 is composed of a 1-D flip-flop which inputs the output of the oscillator 203 to a clock terminal and returns its own negative output signal to an input terminal. And a second 2-D flip-flop that inputs the output signal of the divider 204 to its own input terminal and inputs the output of the oscillator 203 to a clock terminal. The operation of the clock divider circuit configured as described above is as follows.

In FIG. 2, the oscillator 203 outputs an oscillating clockple having a predetermined frequency. The divider 204 performs a toggle operation in synchronization with the oscillation clock pulse 208 output as described above. That is, the output signal changes as 0,1,0,1, ... The delay unit 207 is configured to operate at a different clock edge from the divider 204 to perform a function of delaying and outputting the output of the divider 204 for half a period of the oscillation clock pulse 208. . The first selecting means 205 selects and outputs one of a "high" level signal and a "low" level signal according to the oscillation clock pulse 208, and the second selecting means 206 divides the division price 204. One of the output signal 209 and the output signal 210 of the delay unit 207 is selected according to the oscillation clock pulse 208 and output. Here, the first selecting means 205 and the second selecting means 206 similarly use the oscillation clock pulse 208 as a selection control signal so that the first clock pulse 201 and the second clock pulse which are the respective outputs. 202, leading and trailing edges appear at the same time.

3 is a waveform diagram showing the operation of each block described in FIG. 2 more concisely. The oscillation clock pulse 208 becomes the same waveform as the signal 101 of FIG. 1, and the signal 209 is the signal of FIG. It becomes the same waveform as 102. That is, the period in which the conventional skew phenomenon occurs may be represented by ST1, and the period in which the skew phenomenon occurs in the output signals of the clock division circuit according to the present invention may be represented by ST2. As can be seen in the drawings, the present invention is a skew phenomenon by matching the time at which the leading edge and the trailing edge occurs in the first clock pulse 201 and the second clock pulse 202. Since this period of time is reduced, the period of time that can be operated stably is longer than that of the conventional art.

As described above, the clock divider circuit of the present invention is a clock divider circuit having a shorter deflection, and thus, a period in which each device can be stably operated in a system employing the same increases the performance of the system.

Claims (5)

An oscillator for outputting an oscillating clock pulse having a predetermined frequency; A divider for dividing an oscillating clock pulse output from the oscillator; A delay unit for delaying and outputting the output signal of the frequency divider for half a period of a clock pulse in synchronization with the oscillation clock pulse output from the oscillator; First selecting means for outputting a first clock pulse by alternately selecting one of a "high" level signal and a "low" level signal according to an oscillation clock pulse output from the oscillator; A second selection means for outputting a second clock pulse by alternately selecting one of the output signal of the divider and the output signal of the delayer according to the oscillation clock pulse output from the oscillator and having different frequencies. A clock divider circuit for minimizing edge skew of a first clock pulse and a second clock pulse. The clock divider of claim 1, wherein the divider includes a first-D flip-flop for inputting an output of the oscillator to a clock terminal and returning its own negative output signal to an input terminal. Circuit. The clock divider circuit of claim 1, wherein the delay unit comprises a 2-D flip-flop for inputting an output signal of the frequency divider to its own input terminal and an output of the oscillator to a clock terminal. . 2. The first selector of claim 1, wherein the first selection means inputs the output of the oscillator to its own selection control terminal, and the two input terminals include a power signal representing a "high" level and a ground signal representing a "low" level. And a first multiplexer connected to each other. 2. The apparatus of claim 1, wherein the second selection means inputs the output of the oscillator as its own selection control terminal and inputs the output signal of the divider and the output signal of the delayer to two input terminals, respectively. And a second multiplexer for synchronizing with one clock pulse and outputting a divided second clock pulse.