JPS60145670A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60145670A JPS60145670A JP215584A JP215584A JPS60145670A JP S60145670 A JPS60145670 A JP S60145670A JP 215584 A JP215584 A JP 215584A JP 215584 A JP215584 A JP 215584A JP S60145670 A JPS60145670 A JP S60145670A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- metal
- etched
- gate metal
- resist pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 239000002184 metal Substances 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 11
- 238000005530 etching Methods 0.000 abstract description 6
- 238000010884 ion-beam technique Methods 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置、特に（ＪａＡＳなど化合物半導体
を用いたマイクロ波用ショットキー障壁ゲート型電界効
果トランジスタ（以下ＭＥ８Ｉ”Ｅ’ｒと称する）の製
法に関する。[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor device, and particularly to a method for manufacturing a microwave Schottky barrier gate field effect transistor (hereinafter referred to as ME8I"E'r) using a compound semiconductor such as JaAS. .
ＧａＡｓ ＭＢＳＦＥＴにおいて、特に低雑音用のもの
は、そのゲート長Ｌａが短いほど、またソース寄生抵抗
Ｒｓが小さいほど、発振限界周波数ｆｍａｘが高くなシ
、雑音指数ＮＦを低減できる。そのためＬａが０．５μ
ｍ以下、ソース・ゲート間距離も１０μｍ以下のものが
実用化されている。Among GaAs MBSFETs, especially those for low noise, the shorter the gate length La and the smaller the source parasitic resistance Rs, the higher the oscillation limit frequency fmax, and the lower the noise figure NF. Therefore, La is 0.5μ
A device with a source-to-gate distance of 10 μm or less has been put into practical use.
通常の光学露光によるマスクパターンの分野能は０．６
〜０．８μｍ程度の限界であることから、一般には第１
図（ａ）乃至（Ｃ） Ｋ示すように１．０μｍ程度の線
幅のホトレジストによるマスクパターン１１を形成し、
これ金マスクとしてＧａＡｓ活性層１０上に形成された
ショットキー接合メタル１２ｔサイドエツチングして庇
１４を形成することでサブミクロン長のゲートメタルを
つ＜シ、その後、オーミックメタル１５を蒸着しリフト
法でソース・ドレイン電極を形成している。あるいは、
第２図（ａ）乃至（Ｃ）に示すように、活性層２０上に
形成された２層から成るゲートメタルの上層２２を１．
０μｍ以上のマスクパターン２１で形成し、上層をマス
クとして下層のショットキー接合メタル２３をサイドエ
ツチングして庇２４をククシ、その後、第１図と同じよ
うにしてオーミックメタルを形成する方法が用いられて
いる。ソース・ゲート間Ｍの制御についは、それぞれサ
イドエツチングによって出来だ庇１４．２４を利用し、
オーミックメタル１５．２５に蒸着後、リフトオフ法に
より自己整合的に行うことが多い。The field ability of the mask pattern by normal optical exposure is 0.6
Since the limit is approximately 0.8 μm, generally the first
As shown in Figures (a) to (C) K, a mask pattern 11 of photoresist with a line width of about 1.0 μm is formed,
This is used as a gold mask to side-etch the Schottky junction metal 12t formed on the GaAs active layer 10 to form an eaves 14, thereby forming a submicron-long gate metal.After that, an ohmic metal 15 is vapor-deposited using a lift method. This forms the source and drain electrodes. or,
As shown in FIGS. 2(a) to 2(C), the upper layer 22 of the gate metal consisting of two layers formed on the active layer 20 is 1.
A method is used in which a mask pattern 21 of 0 μm or more is formed, the upper layer is used as a mask, the lower layer Schottky junction metal 23 is side-etched to form the eaves 24, and then an ohmic metal is formed in the same manner as shown in FIG. ing. Regarding the control of M between the source and the gate, use the eaves 14 and 24 made by side etching, respectively.
After vapor deposition on the ohmic metal 15.25, it is often performed in a self-aligned manner by a lift-off method.
これらの方法は、サブミクロンゲート長の形成方法とし
て比較的簡単な製造プロセスではあるが、１）ゲート長
細がサイドエツチングによるために再現性、制御性が不
充分であり、２）ソース・ゲート間を短くすると、ゲー
ト・ドレイン間も短くなるために、ゲート耐圧、ドレイ
ン耐圧が低下するなどの欠点がある。Although these methods are relatively simple manufacturing processes for forming submicron gate lengths, 1) the reproducibility and controllability are insufficient because the gate length is formed by side etching, and 2) the source gate length is If the gap is shortened, the gate-drain gap also becomes short, which has the disadvantage that the gate breakdown voltage and the drain breakdown voltage decrease.
本発明の目的はサブミクロンゲート長を耐圧を低下させ
ることなく再現性、制御性よく形成するショットキー障
壁ゲート型電界効果トランジスタの製造方法を提供する
ことにある。An object of the present invention is to provide a method for manufacturing a Schottky barrier gate type field effect transistor in which a submicron gate length can be formed with good reproducibility and controllability without reducing breakdown voltage.
本発明は、ゲートメタルを斜めからエツチングすること
を特徴とし、このことによ、９１．０μｍ以上のホトレ
ジストパターンから１．０μｍ以下のゲート長を得ると
同時九、ソース・ゲート間距離に比ベゲート・ドレイン
間圧１？ｆＡ ｆｆｉ長くする、いわゆるオフセットゲ
ート形成ができる。The present invention is characterized in that the gate metal is etched diagonally, thereby obtaining a gate length of 1.0 μm or less from a photoresist pattern of 91.0 μm or more.・Drain pressure 1? It is possible to form a so-called offset gate to lengthen fA ffi.
以下、本発明の実施例を図面によシ詳ＭＢＫ説明するＯ
第３図は本発明の一実施例による工程を説明するための
断面図である。まず、第３図（ａ）に示すよように、半
絶絶性ＧａＡｓ基板（図示しない）にエピタキシャル成
長法あるいはイオン注入法でｎ型ＧａＡｓ活性層３１を
形成し、この上に、ゲートメタル３２として例えばＡＡ
を０．８μｍ厚みに蒸着紫する。次に、通常の光学露光
法により線幅Ｗ＝１．０μｍのホトレジストパターン３
３を形成し、露出したＡｌ膜をＣＣ１，ガスにより反応
性イオンエツチングする。このエツチング処理にょシ、
ホトレジストパターン３３直下のＡＩＭはそのパターン
と同じ幅を有した垂直な断面形状が得られる。Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings. Fig. 3 is a sectional view for explaining the steps according to an embodiment of the present invention. First, as shown in FIG. 3(a), an n-type GaAs active layer 31 is formed on a semi-disruptive GaAs substrate (not shown) by epitaxial growth or ion implantation, and a gate metal 32 is formed on this. For example, A.A.
was vapor-deposited to a thickness of 0.8 μm. Next, a photoresist pattern 3 with a line width W=1.0 μm is formed using a normal optical exposure method.
3 is formed, and the exposed Al film is subjected to reactive ion etching using CC1 gas. This etching process
The AIM directly under the photoresist pattern 33 has a vertical cross-sectional shape having the same width as the pattern.
次に、第３図中）に示すように、予め算定した角度θ°
を用いて斜め上方よシ片側のゲートメタル３３を方向性
イオンビーム３４でエツチングする。Next, as shown in Figure 3), the angle θ° calculated in advance is
The gate metal 33 on one side is etched diagonally upward using a directional ion beam 34.
これによって、ホトレジストパターン３３幅Ｗより細い
ゲート長Ｌａ ＜得ることができる。As a result, a gate length La < which is smaller than the width W of the photoresist pattern 33 can be obtained.
このあと、第３図（Ｃ）に示すように、マスクとなった
ホトレジストパターン３３を有機溶剤等で除去し、第３
図（ｄ）に示すようにゲートメタルの斜めエッチした側
にドレイン電極３６、その反対側にソース電極３５を形
成する。After that, as shown in FIG. 3(C), the photoresist pattern 33 that served as a mask is removed using an organic solvent or the like, and the third
As shown in Figure (d), a drain electrode 36 is formed on the obliquely etched side of the gate metal, and a source electrode 35 is formed on the opposite side.
以上のように、所望のゲート長Ｌｃ（５得る場合、Ｌａ
はホトレジストの線幅Ｗ１ゲートメタル厚みｔｃおよび
方向性イオンビームの入射角度ｒから以下の関係式が成
り立つ。As described above, when obtaining the desired gate length Lc (5, La
The following relational expression holds true from the line width W1 of the photoresist, the gate metal thickness tc, and the incident angle r of the directional ion beam.
ｔＧ
Ｌａ＝Ｗ −−
ａｎＯ
例えばＬＧ＝０．３μｍを得るには、ｗ＝＝ １．０４
ｍ 。tG La=W -- anO For example, to obtain LG=0.3 μm, w== 1.04
m.
ｔｏ＝０，３８ｍの場合、θ冨４９°の斜めエツチング
すればよい。When to=0.38m, diagonal etching with a θ depth of 49° is sufficient.
ところで、単にゲート長Ｌｏのみを細くするとゲート寄
生抵抗ＲＧが大きくなシ、電力利得や雑音指数が悪化す
る。一般に、 Ｒａとゲートメタルの比抵抗ρＭ１ゲー
トメタルノリみｔｏ、ゲート１陽ｚの関係は次式で表わ
される。By the way, if only the gate length Lo is reduced, the gate parasitic resistance RG becomes large, and the power gain and noise figure deteriorate. Generally, the relationship between Ra, gate metal resistivity ρM1, gate metal thickness to, and gate 1 positive z is expressed by the following equation.
つまり、１（Ｇはゲートメタルの断面４Ｙ＜ （Ｌａと
ｔＧのｆｆ＜）に逆比例する。In other words, 1 (G is inversely proportional to the gate metal cross section 4Y<(ff< of La and tG).
通常、 Ｌｃ金短縮する場合、ＲＧが、その分、増加し
ないようにｔＧｒ厚くするが、第１図に示す従来の方法
ではサイドエツチングの加工性からｔＧ は０、６〜０
．８ μｍ程；寞である。ｆ反に、ｔ ｃ＝ ０．８
μｍトしてＬｏ２０．５μｍから０．３μｍに短縮する
と、それぞれのり１笛４責は０．４０μｍ月２から０．
２４μｍ２で４０チ小さくなる。Normally, when Lc gold is shortened, tGr is thickened so that RG does not increase accordingly, but in the conventional method shown in Figure 1, tG is 0.6 to 0 due to the workability of side etching.
．． Approximately 8 μm; On the contrary, t c = 0.8
If we shorten Lo2 from 0.5 μm to 0.3 μm, each glue 1 whistle 4 times will be 0.40 μm month 2 to 0.3 μm.
24 μm2 is 40 inches smaller.
で、従来の矩形断面を有するゲートメタルに比べ大幅に
Ｒｃを改善できる。Therefore, Rc can be significantly improved compared to conventional gate metals having a rectangular cross section.
以上、詳細に説明したように本発明によれば、通常の光
学露光法で形成した１、０μｍ以上のホトレジストパタ
ーンの線幅、ゲートメタルの厚みおよび余１めエッチ角
度を適当に選ぶことにより、０．３μｍ程度のゲート長
が形成され、またゲート・ドレイン間距離がゲート・ソ
ース間距離よす長いため、ソース寄生抵抗を低く抑えた
まま、高いドレイン耐圧を得ることができる。更には、
ゲート長を短縮してもゲート寄生抵抗を増大させること
のない逆台形状のゲートメタル形成ができるなど数々の
効果がある。As described above in detail, according to the present invention, by appropriately selecting the line width of the photoresist pattern of 1.0 μm or more formed by a normal optical exposure method, the thickness of the gate metal, and the extra etch angle, Since a gate length of about 0.3 μm is formed and the distance between the gate and drain is longer than the distance between the gate and source, a high drain breakdown voltage can be obtained while keeping the source parasitic resistance low. Furthermore,
This has many advantages, including the ability to form an inverted trapezoidal gate metal without increasing gate parasitic resistance even if the gate length is shortened.
尚、ＧａＡｓ以外の他の化合物半導体であっても全く同
様な製造方法が適用できることは当然のことである。It goes without saying that the same manufacturing method can be applied to other compound semiconductors other than GaAs.
第１図（ａ）乃至（Ｃ）および第２図（ａ）乃至（Ｃ）
はそれぞれ従来のＧａＡｓ ＭＨ８ＦＥＴの製造方法の
工程を説明するための断面図である。
第３図は本発明の一実施例による工程を説明するための
断面図である。
１０・・・・・・ｎ型ＧａＡｓ活性層、１１・・・・・
・ホトレジスト、１２・・・・・・ゲートメタル、１４
・・・・・・庇、１５・・・・・・オーミックメタル、
２０・・・・・・ｎ型ＧａＡｓ活性層、２１・・・・・
・ホトレジスト、２２・・・・・・上層のゲートメタル
、２３・・・・・・下層のゲートメタル、２４・・・・
・・庇、２５・・・・・・オーミックメタル、３１・・
・・・・ｎ型ＧａＡｓ活性層、３２・・・・・・ゲート
メタル、３３・・・・・・ホトレジスト、３４・・・・
・・方向性イオンビーム、３５・・・・・・ソース主、
断、３６・・・・・・ドレイン電極。
１
代理人 弁理士 内 原 晋７５．．４’、、’％。
第１図
（Ｃ）
第２閉Figures 1 (a) to (C) and Figures 2 (a) to (C)
These are cross-sectional views for explaining the steps of a conventional GaAs MH8FET manufacturing method. FIG. 3 is a sectional view for explaining a process according to an embodiment of the present invention. 10... n-type GaAs active layer, 11...
・Photoresist, 12...Gate metal, 14
... Eave, 15 ... Ohmic Metal,
20...n-type GaAs active layer, 21...
・Photoresist, 22... Upper layer gate metal, 23... Lower layer gate metal, 24...
... Eaves, 25 ... Ohmic Metal, 31 ...
...N-type GaAs active layer, 32...Gate metal, 33...Photoresist, 34...
...Directional ion beam, 35... Source main,
Disconnection, 36...Drain electrode. 1 Agent: Susumu Uchihara, patent attorney 75. ．． 4',,'%. Figure 1 (C) 2nd close
Claims (1)
レジスト全役け、該ホトレジストをマスクＫｇ出した金
属を選択的にエツチングし、さらに斜め上方よシ金属を
エツチングして該ホトレジストの幅よ仄紳い幅を有する
金属層全形成することを特徴とする半導体装置の製造方
法。A metal is deposited on a semiconductor substrate, a photoresist of a predetermined width is deposited on the metal, the metal is selectively etched with the photoresist exposed as a mask, and the metal is further etched diagonally upward to increase the width of the photoresist. A method for manufacturing a semiconductor device, characterized in that a metal layer having a narrow width is entirely formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP215584A JPS60145670A (en) | 1984-01-10 | 1984-01-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP215584A JPS60145670A (en) | 1984-01-10 | 1984-01-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60145670A true JPS60145670A (en) | 1985-08-01 |
Family
ID=11521457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP215584A Pending JPS60145670A (en) | 1984-01-10 | 1984-01-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60145670A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016167600A (en) * | 2009-08-28 | 2016-09-15 | トランスフォーム インコーポレーテッド | Semiconductor device having field plate |
-
1984
- 1984-01-10 JP JP215584A patent/JPS60145670A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016167600A (en) * | 2009-08-28 | 2016-09-15 | トランスフォーム インコーポレーテッド | Semiconductor device having field plate |
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