JPS60144971A - Semiconductor device - Google Patents

Abstract

PURPOSE:To share a power supply for CCD shift registers for transfer and a drain by mutually making concentration in the surface or in the vicinity of the surfaces of CCDs for transfer and the drain mutually adjoining through a gate differ to each other. CONSTITUTION:A substrate 10 takes a P type, and a CCD shift register 3 for transfer is constituted by a gate 11, a gate oxide film 16 and an N well 13. A CCD shift register 7 for a drain is constituted by a gate 12, the film 16 and an N well 14, and the concentration of the well 14 is made higher than that of the well 13. Consequently, a power supply 21 for drivers 17 and 18 for driving connected to each gate 11 and 12 in the register 3 and the register 7 can be shared. Driver 17 and 18 themselves can also be made common. Accordingly, the potential of the register 7 can be made deeper than that of the register 3 when the gates 11 and 12 are supplied with voltage at the same high level, and charges in the register 3 are transferred to the register 7 when a drain gate 6 is brought to a high level under the state.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device having a charge transfer function.

2. Description of the Related Art Structures of Conventional Examples and Their Problems Recently, the development of COD (charge-coupled devices) having a charge transfer function has progressed, and as an application thereof, the development of COD image sensors is actively progressing.

FIG. 1 shows a schematic diagram of a conventional one-dimensional COD solid-state imaging device. The incident light is converted into charges according to the strength of the light in the photoelectric conversion unit 1, and after being accumulated for a certain period of time, the charges accumulated in the odd-numbered pixels in the photoelectric conversion unit 1 are converted into charges according to the intensity of the light. The charge accumulated in the even numbered pixel is transferred to the even numbered CCD shift register 3b through the shift gate 2b, and the charge in each of the even and odd shift registers is transferred by COD transfer. , are transferred to the output section 5 through the output gate 4.

In the conventional structure described above, the charges of all pixels must be constantly transferred within the CCD shift register, and the scanning time (accumulation time) of a line is equal to the transfer time of one stage multiplied by the number of pixels. Therefore, even with a structure in which the CCD shift register is divided into odd and even numbers, the scanning time is only half of the above scanning time.

Recently, there has been a growing demand for high-speed recognition of a portion of information9, and the above-mentioned conventionally structured devices cannot meet the above-mentioned demands. Therefore, one structure has been proposed to solve the above problems. FIG. 2 shows an improved conventional structure, which is a CCD shift register 3a for even and odd transfers of the structure shown in FIG.

Drain CCD shift registers 7a and 7b are provided next to the transfer COD shift registers 3a and 3b via drain gates 6a and 6b, and unnecessary signals in the transfer COD shift registers 3a and 3b are transferred to the drain C'CD shift registers 7a and 7b.
The structure is such that the charges are transferred to drains 8a and 8b provided at the ends and discarded. Therefore, in the structure shown in Fig. 2, the required number of pixels can be selected by appropriately selecting the timing of the pulses applied to the drain gates 6a and 6b, and the scanning time for one line can be arbitrarily selected accordingly. can do.

However, in the conventional structure shown in FIG. 2, the transfer COD shift registers 3a and 3b and the drain CCD shift registers 7a and 7b must have different potentials.
Transfer between CDs is completely impossible.

FIG. 3a shows the cross-sectional structure of the conventional structure in FIG. It consists of an N-well 13 for a buried channel. The drain CCD shift register 7b is composed of a gate 12, a gate oxide film 16, and an N well 14, and each of the transfer and drain COD shift registers 3b.

7b are adjacent to each other with the drain gate 6b interposed therebetween. 17 is a driver that drives the transfer COD shift register 3b, and 19 is a power source for the driver. On the other hand, 18 is a driver that drives the drain CCD shift register 7b, and 20 is a power source for the driver. In the structure shown in FIG. 3a, the transfer COD shift register s
In order to transfer the charge in b to the drain CCD shift register 7b, in the transfer state as shown in the figure, the drain gate 6 is shifted from the low potential A to the high potential B.
, the potential C of the transfer COD shift register 3b also changes to the potential C of the drain CCD shift register 7.
The potential D of b must be deeper. However, in the conventional structure shown in FIG. 3a, the N well 13 of the transfer COD shift register 3b and the N well 14 of the drain COD
have the same concentration, and the potentials of each CCD gate 11 and 12 in the low level state are exactly the same as shown in FIG. Therefore, the power source 20 of the driver 18 that drives the drain CCD shift register 7b requires a higher voltage than the power source 19 of the driver 17 that drives the transfer COD shift register 3b. Therefore, the power source for the drivers cannot be shared, and the circuit becomes complicated accordingly.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional problems and provides a semiconductor device that can share the power source of the transfer and drain CCD shift registers.

Structure of the Invention The present invention is configured such that the concentrations at or near the surfaces of CODs for transfer and drain adjacent to each other via gates are different from each other, and the power supply for the CCD shift register for transfer and drain is shared. be.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

In this embodiment, the cross section taken along the line AA' in FIG. 2 has a configuration as shown in FIG. 4.

FIG. 4a shows the cross-sectional structure of the main part in one embodiment of the present invention.
The OD shift register 3b has a gate 11 and a gate oxide film 1.
6 and an N-well 13 for a buried channel. The drain CCD shift register 7b is composed of a gate 12, a gate oxide film 16, and an N well 14, and the concentration of the N well 14 is higher than that of the N well 13 of the transfer COD shift small register 3b. Therefore, the transfer COD shift register 3b and the drain C
The power source 21 of the driving drivers 17 and 18 connected to the respective gates 11 and 12 of the CD shift register 7b can be shared. Furthermore, it is possible to use a common driver for each of the transfer and drain COD shift registers. Figure 4 shows the potential during transfer in cross-sectional view a, and shows the potential when the same high-level voltage is supplied to each gate 11 and 12 of CCD shift registers 3 and 7 for transfer and drain. As shown in the same figure, drain CCD shift register 7
The potential D of b is the transfer COD shift register 3b.
This shows that the potential A is deeper than the potential C of drain game 1-6.
When the potential is set to high level, the transfer CO
The charges in the D shift register 3 are transferred to the drain CCD shift register 7b. Note that C in the figure shows the potential of the transfer and drain CCD shift registers 3b and 7b at a low level.

Effects of the Invention The semiconductor device of the present invention can transfer the charge of one charge transfer device to another charge transfer device using a common dryer, 6-power supply or a common driver, and its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a conventional one-dimensional COD solid-state imaging device, and FIG. 2 is a plan view of an improved one-dimensional COD solid-state imaging device.
Fig. 3 C5 Fig. 4 a is a sectional view taken along the line A-A' in Fig. 2 in the conventional 5 invention, Fig. 3 and Fig. 4 are potential diagrams during each operation, and Fig. 3 C5 FIG. 4C is an impurity concentration distribution map of ゛, respectively. 1o...Substrate, 11.12...Gate 1, 13゜14 River/N well, 15...Channel stopper, 16...Gate oxide film , 17
．． 18・Kawa・Driver, 21... Power supply for the driver. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 8 Construction Figure 3/''10 Figure 4

Claims (1)

[Claims] Adjacent transfer and drain CODs across gates
A semiconductor device characterized in that the concentrations at or near the surface of the semiconductor devices are different from each other.