JPS60143676A - Photovoltaic device - Google Patents

Photovoltaic device

Info

Publication number
JPS60143676A
JPS60143676A JP58251962A JP25196283A JPS60143676A JP S60143676 A JPS60143676 A JP S60143676A JP 58251962 A JP58251962 A JP 58251962A JP 25196283 A JP25196283 A JP 25196283A JP S60143676 A JPS60143676 A JP S60143676A
Authority
JP
Japan
Prior art keywords
layer
solar cell
amorphous silicon
cell element
amorphous semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58251962A
Other languages
Japanese (ja)
Inventor
Osamu Nakamura
修 中村
Mitsuo Matsumura
松村 光雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tonen General Sekiyu KK
Original Assignee
Toa Nenryo Kogyyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toa Nenryo Kogyyo KK filed Critical Toa Nenryo Kogyyo KK
Priority to JP58251962A priority Critical patent/JPS60143676A/en
Publication of JPS60143676A publication Critical patent/JPS60143676A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042PV modules or arrays of single PV cells
    • H01L31/0445PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042PV modules or arrays of single PV cells
    • H01L31/05Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
    • H01L31/0504Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

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  • Engineering & Computer Science (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Sustainable Energy (AREA)
  • Photovoltaic Devices (AREA)

Abstract

PURPOSE:To obtain a device which can obtain high output voltage by connecting in series plural amorphous semiconductor solar cell elements. CONSTITUTION:An amorphous semiconductor solar cell element 2 which constitutes a photovoltaic device 1 is the laminating of an amorphous semiconductor layer 6 on such a conductive substrate 4 as a stainless steel thin plate or a thin iron plate. The semiconductor layer 6 can be made a p-n construction, a n-p construction or a tandem construction piled in two layers of these two constructions. A long size conductive substrate wherein amorphous silicon layers are piled is cut, a transparent conductive film 8 is formed on the semiconductor layer 6 and the solar cell element 2 of W wide and L long is formed. The element 2 is so placed on an insulating substrate 30 that the ends (d) of the adjacent elements 2a and 2b are piled. Then, at the right ends of the elements 2a, 2b, 2c,..., a passivation film 24 is formed and a leak between the substrates of each element is prevented.

Description

【発明の詳細な説明】 本発明は、一般には光起電力装置に関するものであり、
特にアモルファス半導体太@電池を複数個電気的に接続
して構成される光起電力装置に関するものである。本明
細書において、アモルファス半導体とは、微結晶化半導
体をも含むものとして使用する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates generally to photovoltaic devices;
In particular, the present invention relates to a photovoltaic device constructed by electrically connecting a plurality of amorphous semiconductor batteries. In this specification, amorphous semiconductor is used to include microcrystallized semiconductor.

近年、アモ/I/7アス半導体、例えばアモルファスシ
リコン太陽電池は、(1)薄膜であること、つまり結晶
化シリコンに比べ可視光域での吸収係数が大きく、結晶
シリコンと同程度の変換効率を得るには約1けた薄い膜
厚でよいこと、12)γモル7アスシリコン太陽電池の
製造に要した電力は結晶シリコン太陽電池よりも極めて
少なく、エネルギ回収率が少ないこと、(3)基板加熱
が少なく且つアモルファスシリコンが基板と反応するこ
とがなく、ステンレス板、ガラス板等のように種々の基
板を使用し得ること、(4)シラン(SiH4)からグ
ルー放電分解にて直接基板上に膜を形成し得るため連続
生産が容易であること、等々の理由によって光起電力装
置の構成要素として注目を浴びている。
In recent years, AMO/I/7A semiconductors, such as amorphous silicon solar cells, have (1) been thin films, that is, have a larger absorption coefficient in the visible light range than crystallized silicon, and have a conversion efficiency comparable to that of crystalline silicon. 12) The power required to manufacture γmol 7As silicon solar cells is much lower than that of crystalline silicon solar cells, resulting in a lower energy recovery rate; (3) Substrate heating (4) Amorphous silicon does not react with the substrate, and various substrates such as stainless steel plates and glass plates can be used. It is attracting attention as a component of photovoltaic devices because it can be easily produced in a continuous manner.

しかしながら、アモルファスシリコン太陽電池の単位面
積当りの出力は極めて小さく、従って実用に供し得る大
電力を発生するには、太陽電池の表面積を大とすること
が不可欠である。
However, the output per unit area of an amorphous silicon solar cell is extremely small, and therefore, in order to generate a large amount of power that can be put to practical use, it is essential to increase the surface area of the solar cell.

斯る欠点を解決するべく、一つの太陽電池素子の表面積
を大とすると、素子の表面積を構成する透明導電層のシ
ート抵抗により効率が低下することが分っている。更に
又、このような大きな太陽電池を製造するのは技術的に
はより困難となり、歩留まりが低下するという不利益が
あった。
It has been found that when the surface area of a single solar cell element is increased in order to solve this drawback, the efficiency decreases due to the sheet resistance of the transparent conductive layer that constitutes the surface area of the element. Furthermore, it is technically more difficult to manufacture such a large solar cell, resulting in a disadvantage of lower yield.

上記の如き不利益の中、特に透明導′成層のシート抵抗
による効率低下を解消するべく、絶縁基板上に複数の太
陽電池素子を形成し、各太陽電池素子を直列に接続する
ようにした集積型が考えられているが、製造工程が複雑
で、製造価格が大であるというばかりでなく、素子占有
面積に比べ有効発電面積が狭い、つまり、実用効率が低
いという欠点があった。又、例集積型であっても、例え
ば201角のセルを作るには201角の基板上にアモル
ファスシリコン等を堆積せねばならず、大面積化による
歩留まりの低下が余儀なくされる。
Among the above-mentioned disadvantages, in order to overcome the reduction in efficiency due to the sheet resistance of transparent conductive layers, integrated solar cells are formed in which multiple solar cell elements are formed on an insulating substrate and each solar cell element is connected in series. However, the manufacturing process is complicated and the manufacturing cost is high, and the effective power generation area is small compared to the area occupied by the element, which means that the practical efficiency is low. Furthermore, even in the integrated type, for example, to make a 201 square cell, amorphous silicon or the like must be deposited on a 201 square substrate, which inevitably lowers the yield due to the larger area.

従って、本発明の主たる目的は、大面積を有し、効率の
良いしかも低価格の光起電力装置を提供することである
Therefore, the main object of the present invention is to provide a photovoltaic device having a large area, high efficiency, and low cost.

本発明の他の目的は、複数のアモルファス半導体太陽電
池素子を直列に接続して構成され、高出力電圧を得るこ
とのできる光起電力装置を提供することである。
Another object of the present invention is to provide a photovoltaic device configured by connecting a plurality of amorphous semiconductor solar cell elements in series and capable of obtaining a high output voltage.

次に、本発明に係る光起電力装置を図面に則して説明す
る。
Next, a photovoltaic device according to the present invention will be explained with reference to the drawings.

第1図は、本発明の光起電力装置1を構成するアモルフ
ァス半導体太陽電池素子2を示す。アモルファス半導体
太陽電池素子2は、例えばステンレス薄板の導電性基板
4上にアモルファス半導体層6が積層される。ここで導
電性基板4は鉄薄板など他の金属製基板を使用すること
ができる。
FIG. 1 shows an amorphous semiconductor solar cell element 2 constituting a photovoltaic device 1 of the present invention. In the amorphous semiconductor solar cell element 2, an amorphous semiconductor layer 6 is laminated on a conductive substrate 4 made of, for example, a thin stainless steel plate. Here, as the conductive substrate 4, another metal substrate such as a thin iron plate can be used.

本実施態様において、アモルファス半導体層6は、pi
n構造、nlp構造、又はこれら構造体を二層に積んだ
タンデム構造とすることができる。又、p層、1層及び
n層はアモルファスシリコン層とすることができるが、
p層、n層には微結晶化シリコン層、tmにはアモルフ
ァスシリコン・ゲルマニウム層を用いることもできる。
In this embodiment, the amorphous semiconductor layer 6 is made of pi
It can be an n structure, an nlp structure, or a tandem structure in which these structures are stacked in two layers. Also, the p layer, 1 layer and n layer can be amorphous silicon layers,
A microcrystalline silicon layer may be used for the p layer and the n layer, and an amorphous silicon germanium layer may be used for the tm.

第1図に示されるアモルファス半導体層6は、基板4側
より順次にアモルファスシリコンp型層6m、アモルフ
ァスシリコンl型層6b及びアモルファスシリコンn型
層6cを積層したpin構造であり、アモルファス半導
体N6の上層には透明導電膜8が形成される。
The amorphous semiconductor layer 6 shown in FIG. 1 has a pin structure in which an amorphous silicon p-type layer 6m, an amorphous silicon l-type layer 6b, and an amorphous silicon n-type layer 6c are sequentially laminated from the substrate 4 side. A transparent conductive film 8 is formed on the upper layer.

アモルファス太陽電池素子2は、上述のように、第1図
に示される素子構造に限定されるものではなく、例えば
具体的に一例を掲げれば、基板/n−1−p(アモルフ
ァスシリコン/透明導電膜、M板/p(アモルファスシ
リコン−魚(アモルファスシリコン・ゲルマニウム)−
n−p−1−n(アモルファスシリコン)/透明導電膜
(タンデム構造)が考えられる。
As mentioned above, the amorphous solar cell element 2 is not limited to the element structure shown in FIG. Conductive film, M plate/p (amorphous silicon - fish (amorphous silicon germanium) -
n-p-1-n (amorphous silicon)/transparent conductive film (tandem structure) can be considered.

次に、゛第1図に示すp−1−n(アモルファスシリコ
ン)構造の太陽電池素子2の一製造方法について、第2
図を参照して説明する。
Next, we will discuss a second method for manufacturing a solar cell element 2 having a p-1-n (amorphous silicon) structure shown in FIG.
This will be explained with reference to the figures.

第2図にはアモルファスシリコン堆積装置10の構成が
概略図示されている。該装置10は内部に、p型層形成
チャンバ12.1側層形成チャンバ14及びn型層形成
チャンバ16を有する。各チャンバ12.14及び16
は、対をなす電極18a、b、20a、b及び22aX
bを備えたグロー放電装置18.20及び22を有する
FIG. 2 schematically shows the structure of the amorphous silicon deposition apparatus 10. As shown in FIG. The apparatus 10 has a p-type layer forming chamber 12, a side layer forming chamber 14, and an n-type layer forming chamber 16 inside. Each chamber 12.14 and 16
are paired electrodes 18a, b, 20a, b and 22aX
a glow discharge device 18, 20 and 22 with b.

又、前記各チャンバ12.14及び16を貫通して、即
ち、各チャンバの対の電極間を通って長尺の導電性基板
4が、供給p層ル4aから巻取p−ル4bへと供給され
る。
Further, the elongated conductive substrate 4 passes through each of the chambers 12, 14 and 16, that is, between the pair of electrodes in each chamber, from the supply p-layer 4a to the take-up p-rule 4b. Supplied.

更に、各チャンバ12.14及び16には、所定のドー
パントガスが供給される。即ち、チャンバ12にはSi
H4とB2H,の混合ガス、チャンバ14にはSiH4
ガス及びチャンバ16にはPH3,81H4及びH2の
混合ガスが供給される。
Furthermore, each chamber 12.14 and 16 is supplied with a predetermined dopant gas. That is, the chamber 12 contains Si.
Mixed gas of H4 and B2H, SiH4 in chamber 14
A mixed gas of PH3, 81H4 and H2 is supplied to the gas and chamber 16.

導電性基板4は、例えば(11m厚、20cH1幅のス
テンレス薄板とされ、供給ロール4&側から、各チャン
バの電極間を通って巻取田−ル4b側へと搬送される。
The conductive substrate 4 is, for example, a thin stainless steel plate with a thickness of 11 m and a width of 20 cH1, and is conveyed from the supply roll 4& side to the winding roll 4b side through between the electrodes of each chamber.

基板4上には、チャンバ12にてp 型層6 mが、次
でチャンバ14にては前記p型層6a上にl型層6bが
堆積され、最後にチャンバ16にては前記1型層6b上
に更にn型層6Cが堆積される。このようにして、導電
性基板4には連続的にアモルファスシリコン層6が堆積
される。
On the substrate 4, a p-type layer 6m is deposited in the chamber 12, then an l-type layer 6b is deposited on the p-type layer 6a in the chamber 14, and finally, the 1-type layer 6m is deposited in the chamber 16. An n-type layer 6C is further deposited on 6b. In this way, the amorphous silicon layer 6 is continuously deposited on the conductive substrate 4.

アモルファスシリコン層が堆積された長尺導電性基板は
、長手方向に5〜50關間隔幅、好ましくは10〜30
1111幅にて順次に切断される。
The elongated conductive substrate on which the amorphous silicon layer is deposited has a width of 5 to 50 degrees in the longitudinal direction, preferably 10 to 30 degrees.
It is sequentially cut at 1111 widths.

切断された各アモルファスシリコン層相基板は蒸着装置
に導入され、透明導電層8が、通常態様にてアモルファ
スシリコン層6上に形成される。
Each cut amorphous silicon layer phase substrate is introduced into a vapor deposition apparatus and a transparent conductive layer 8 is formed on the amorphous silicon layer 6 in the usual manner.

これによって、第1図に図示されるように、巾(W)2
01?FF+、長す(L) 5〜50關のアモルファス
シリコン太陽電池素子2が製造される。太陽電池2の長
さくL)は、前述のように5〜50關とされるが、切断
幅即ち長さくL)を5龍以下とすることは生産速度の低
下、生産コストの上昇をもたらし好ましくなく、又長さ
くL)を501111以上とすると、透明導電層8のシ
ート抵抗によって太VwJ電池の効率が低下し、更に歩
留まりが悪くなり好ましくない。
As a result, the width (W) 2
01? FF+, an amorphous silicon solar cell element 2 having a length (L) of 5 to 50 mm is manufactured. The length L) of the solar cell 2 is set to be 5 to 50 mm as described above, but it is preferable to set the cutting width, that is, the length L) to less than 5 mm, as this will decrease the production speed and increase the production cost. In addition, if the length L) is set to 501111 or more, the efficiency of the thick VwJ battery will decrease due to the sheet resistance of the transparent conductive layer 8, and the yield will further deteriorate, which is undesirable.

又、所望に応じ、第3図に図示されるように、太陽電池
要素2の一端にパッシベーション膜24を施すことがで
きる。パッシベーション膜24は、透明導電層8を堆積
する前のアモルファスシリコン層6の上表面に幅(D)
α2〜2關にわたり、且つ上表面から端面に沿って基板
4に達するように設けられる。このパッシベーション膜
24は、5in4及びO!の混合ガス又は5IH4及び
NH3の混合ガスを使用したプラズマCVD法によって
形成された5102又はSiN4膜とすることもできる
し、又は適当な有機材料を塗布して形成された絶縁性有
機膜とすることができる。このようなパッシベーション
膜24を施すことにより、後述するように、直列に接続
された各太陽電池素子の基板間のリークによる歩留りの
低下を防ぐことができる。又、パッシベーション膜24
を施すことによって太陽電池の変換効率が低下すること
はない。
Furthermore, if desired, a passivation film 24 can be applied to one end of the solar cell element 2, as shown in FIG. The passivation film 24 has a width (D) on the upper surface of the amorphous silicon layer 6 before the transparent conductive layer 8 is deposited.
It is provided so as to extend over α2~2 and reach the substrate 4 from the upper surface along the end surface. This passivation film 24 is 5in4 and O! It can be a 5102 or SiN4 film formed by a plasma CVD method using a mixed gas of 5IH4 and NH3, or an insulating organic film formed by coating an appropriate organic material. I can do it. By applying such a passivation film 24, as will be described later, it is possible to prevent a decrease in yield due to leakage between the substrates of each solar cell element connected in series. Moreover, the passivation film 24
The conversion efficiency of the solar cell does not decrease by applying this.

以上の如くにして製造されたアモルファスシリコン太陽
電池素子2は、第4図に図示されるように、絶縁性基板
50、例えばプラスチック基板上に、隣接する二つの太
陽電池素子2a及び2bの隣り合った端部が互いに重な
り合うように整列して配置される。更に詳しく言えば、
#81の太陽電池素子21の右端には、第1の太陽電池
素子2a直ぐ隣りに位置した第2の太陽電池素子2bの
左端が幅(d)だけ重ね合せられる。又第2の太陽電池
素子2bの右端には、該第2の太陽電池素子2bの直ぐ
隣りに位置した第3の太陽電池素子2Cの左端が幅(d
)だけ重ね合せられる。このとき、前述のように太陽電
池素子21% 2b、2cm1・・・・・・の右端にパ
ッシベーション膜24を施せば、各太陽電池素子の基板
間のリークを未然に防止することができる。以後、所望
数の太li!電池素が上述のようにして直列接続態様で
配置され、光起電力装置1が構成される。
As shown in FIG. 4, the amorphous silicon solar cell element 2 manufactured as described above is placed on an insulating substrate 50, for example, a plastic substrate, on which two adjacent solar cell elements 2a and 2b are placed. The ends are arranged in alignment so that they overlap each other. To be more specific,
The left end of the second solar cell element 2b located immediately adjacent to the first solar cell element 2a is overlapped with the right end of the #81 solar cell element 21 by a width (d). Further, the left end of the third solar cell element 2C located immediately adjacent to the second solar cell element 2b has a width (d) at the right end of the second solar cell element 2b.
) can be superimposed. At this time, if the passivation film 24 is applied to the right end of the solar cell elements 21% 2b, 2 cm1, . . . as described above, leakage between the substrates of each solar cell element can be prevented. After that, the desired number of fat li! The battery elements are arranged in a series connection manner as described above, and the photovoltaic device 1 is constructed.

各太陽電池素子2 (21LN 2 bs 2 es 
”’)は、適当な接着剤でもってその導電性基板4側が
絶縁性基板60に固定され、互いに重なり合った部分、
つまり、一方の太陽電池素子の透明導電膜8と他方の太
陽電池素子の導電性基板との接合部分(d)は、銀ペー
スト等のような導電性接着剤を利用することによって電
気的接続が保証される。重なり合い部分の長さくd)は
、太陽電池の効率の点で言えば任意の大きさとすること
ができるが、生産の容易さ、原料コスト等を考えると、
α5〜5−が好適である。又、パッシベーション膜幅(
D)は、接合部分(d)より小とされるであろう。
Each solar cell element 2 (21LN 2 bs 2 es
"') is a portion where the conductive substrate 4 side is fixed to the insulating substrate 60 with a suitable adhesive and overlaps each other,
In other words, electrical connection is established between the transparent conductive film 8 of one solar cell element and the conductive substrate of the other solar cell element by using a conductive adhesive such as silver paste. Guaranteed. The length d) of the overlapping portion can be set to any size from the viewpoint of solar cell efficiency, but considering ease of production, raw material cost, etc.
α5-5- is preferred. Also, the passivation film width (
D) will be smaller than the joining part (d).

以上の方法により、例えば幅(W)20cM1、長さく
I、)12mの太li1!電池素子2を、互いに重なり
部分(d)が2闘となるようにして絶縁性基板30上に
配列し、集積することによって、20crR角の光起電
力装置1を容易に製造することができる。
By the above method, for example, a thick li1 with a width (W) of 20 cm and a length of I,) of 12 m! By arranging and integrating the battery elements 2 on the insulating substrate 30 so that two overlapping portions (d) overlap with each other, the photovoltaic device 1 having a square size of 20 crR can be easily manufactured.

以上の如くに構成される本発明に従った光起電力装置は
、(1)各太陽電池素子を、例えば20cIR×t2c
1nといった比較的小面積とし、変換効率及び歩留まり
共高く保つことができる、(2)各太陽電池素子は20
段といった直列配置構成とすることができ、例えば16
■といった実用的な高い出力電圧を得ることができる、
(3)例えば20瓜角といった光起電力装置のほぼ全面
積で発電が行なわれ面積効率が著しく大である、(4)
4電性基板としてステンレス薄板等の低価格の材料を使
用することができ、低価格の太vj電池、従って低価格
の光起電力装置を提供し得る、といった楓々の利益を有
するO
The photovoltaic device according to the present invention configured as described above has the following features: (1) Each solar cell element has an arrangement of, for example, 20cIR×t2c
(2) Each solar cell element has a relatively small area of 1n, and can maintain high conversion efficiency and yield.
It may be arranged in series such as stages, e.g. 16
■It is possible to obtain a practical high output voltage such as
(3) Electricity is generated over almost the entire area of the photovoltaic device, for example, 20°, and the area efficiency is extremely high. (4)
Kaede has the advantage of being able to use low-cost materials such as thin stainless steel plates as the four-conductor substrate, and providing a low-cost thick VJ battery and, therefore, a low-cost photovoltaic device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、アモルファス半導体太陽電池素子の斜視図で
ある。 第2図は、アモルファスシリコン太1i[池素子の製造
装置の概略断面図である。 第3図は、アモルファス半導体太陽電池素子の正面図で
ある。 第4図は、本発明に係る光起電力装置の部分正面図であ
る。 1:光起電力装置 2:アモルファス半導体太陽電池素子 4:導電性基板 6:アモルファス半導体層 8:透明導電層 24:パンシベーション膜 区 (〕 区 〜 手続補正書(方式) 昭和59年 4 Jl 26 目 特許庁長官 若 杉 和 夫 殿 事件の表示 昭和58年 特願第251962 壮発明
の名称 光起電力装置 補正をする者 事件との関係 特許出願人 名称 東亜姑料工梁株式会社 代理人 〒103 補正命令通知の目付 昭和59年3月27日−幇hト軒
旨トカ→曽力+1+リシ嘴ジ男マ列牧下補正の対象 委任4層e戸ト〜や辷 +−1通 図面 1通 明細書 補正の内容 別紙の通り
FIG. 1 is a perspective view of an amorphous semiconductor solar cell element. FIG. 2 is a schematic cross-sectional view of an apparatus for manufacturing an amorphous silicon device. FIG. 3 is a front view of the amorphous semiconductor solar cell element. FIG. 4 is a partial front view of a photovoltaic device according to the present invention. 1: Photovoltaic device 2: Amorphous semiconductor solar cell element 4: Conductive substrate 6: Amorphous semiconductor layer 8: Transparent conductive layer 24: Pansivation film Ward ~ Procedural amendment (method) 1980 4 Jl 26 Indication of the case of Kazuo Wakasugi, Commissioner of the Patent Office, 1982, Patent Application No. 251962, Title of the grand invention Relationship with the case of person who corrects photovoltaic devices Name of patent applicant: Agent of Toagu Ryoko Liang Co., Ltd. Address: 103 Weight of notice of amendment order March 27, 1980 - 幇hto 纹目トカ → Sori + 1 + rishi beak ji manma row makishita subject of amendment 4th layer e to ~ and 辷 + - 1 drawing 1 copy Contents of amendment to the description As shown in the attached sheet

Claims (1)

【特許請求の範囲】 1)導電性基板、アモルファス半導体層及び透明導電膜
層を積層して構成される太@電池素子を複数個直列態様
で配置し、隣接する太陽電池素子は、一方の太陽電池素
子の透明導電膜層上に他方の太陽電池素子の導電性基板
が一部重なり合うようにして電気的に直列接続されて成
る光起電力装置。 2)アモルファス半導体層は、pin構造、nlp構造
、又はpln或はnlp構造を二層に積んだタンデム構
造とされて成る特許請求の範囲第1項記載の装置。 3)p層、1層及びn層はいずれもアモルファスシリコ
ン層である特許請求の範囲第2項記載の装置。 4) p層及び/又はn層は微結晶化シリコン層である
特許請求の範囲第2項記載の装置。 5)1層はアモルファスシリコン・ゲルマニウム層であ
る特許請求の範囲第2項記載の装置。 6)導電性基板はステンレス薄板又は鉄薄板である特許
請求の範囲第1項又は第2項記載の装置。 7)太@電池素子の端面にはパッシベーション膜が施さ
れて成る特許請求の範囲第1項〜第6項のいずれかの項
に記載の装置。
[Claims] 1) A plurality of thick battery elements each formed by laminating a conductive substrate, an amorphous semiconductor layer, and a transparent conductive film layer are arranged in series, and adjacent solar battery elements are connected to one solar cell. A photovoltaic device comprising a transparent conductive film layer of a battery element and a conductive substrate of another solar cell element electrically connected in series so as to partially overlap with each other. 2) The device according to claim 1, wherein the amorphous semiconductor layer has a pin structure, an nlp structure, or a tandem structure in which two layers of pln or nlp structures are stacked. 3) The device according to claim 2, wherein the p-layer, 1-layer and n-layer are all amorphous silicon layers. 4) The device according to claim 2, wherein the p-layer and/or the n-layer are microcrystalline silicon layers. 5) The device according to claim 2, wherein one layer is an amorphous silicon germanium layer. 6) The device according to claim 1 or 2, wherein the conductive substrate is a thin stainless steel plate or a thin iron plate. 7) The device according to any one of claims 1 to 6, wherein a passivation film is provided on the end face of the thick battery element.
JP58251962A 1983-12-29 1983-12-29 Photovoltaic device Pending JPS60143676A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58251962A JPS60143676A (en) 1983-12-29 1983-12-29 Photovoltaic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58251962A JPS60143676A (en) 1983-12-29 1983-12-29 Photovoltaic device

Publications (1)

Publication Number Publication Date
JPS60143676A true JPS60143676A (en) 1985-07-29

Family

ID=17230572

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58251962A Pending JPS60143676A (en) 1983-12-29 1983-12-29 Photovoltaic device

Country Status (1)

Country Link
JP (1) JPS60143676A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL1005926C2 (en) * 1997-04-29 1998-11-02 Stichting Energie Solar panel with photovoltaic units connected in series.
WO2012127932A1 (en) * 2011-03-18 2012-09-27 東レエンジニアリング株式会社 Device and method for manufacturing solar battery module

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55108779A (en) * 1979-02-14 1980-08-21 Sharp Corp Thin film solar cell
JPS5679476A (en) * 1979-12-04 1981-06-30 Fuji Electric Co Ltd Solar battery

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55108779A (en) * 1979-02-14 1980-08-21 Sharp Corp Thin film solar cell
JPS5679476A (en) * 1979-12-04 1981-06-30 Fuji Electric Co Ltd Solar battery

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL1005926C2 (en) * 1997-04-29 1998-11-02 Stichting Energie Solar panel with photovoltaic units connected in series.
WO1998049735A1 (en) * 1997-04-29 1998-11-05 Stichting Energieonderzoek Centrum Nederland Solar panel having photovoltaic units connected in series
WO2012127932A1 (en) * 2011-03-18 2012-09-27 東レエンジニアリング株式会社 Device and method for manufacturing solar battery module
JP2012199278A (en) * 2011-03-18 2012-10-18 Toray Eng Co Ltd Manufacturing apparatus and method for solar cell module
CN103415927A (en) * 2011-03-18 2013-11-27 东丽工程株式会社 Device and method for manufacturing solar battery module
US9023736B2 (en) 2011-03-18 2015-05-05 Toray Engineering Co., Ltd. Solar cell module manufacturing apparatus and solar cell module manufacturing method
TWI505494B (en) * 2011-03-18 2015-10-21 Toray Eng Co Ltd Manufacture of solar cell module and manufacturing method thereof

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