JPS60143666A - Matrix type semiconductor device - Google Patents
Matrix type semiconductor deviceInfo
- Publication number
- JPS60143666A JPS60143666A JP24816283A JP24816283A JPS60143666A JP S60143666 A JPS60143666 A JP S60143666A JP 24816283 A JP24816283 A JP 24816283A JP 24816283 A JP24816283 A JP 24816283A JP S60143666 A JPS60143666 A JP S60143666A
- Authority
- JP
- Japan
- Prior art keywords
- liquid crystal
- matrix type
- channel length
- soi
- grain boundary
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000011159 matrix material Substances 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000009792 diffusion process Methods 0.000 abstract description 12
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 11
- 238000002425 crystallisation Methods 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 8
- 230000002159 abnormal effect Effects 0.000 abstract description 7
- 230000008025 crystallization Effects 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract 1
- 230000005669 field effect Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000002547 anomalous effect Effects 0.000 description 4
- 239000000969 carrier Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 210000002858 crystal cell Anatomy 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000005499 laser crystallization Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229940072033 potash Drugs 0.000 description 1
- 235000015320 potassium carbonate Nutrition 0.000 description 1
- BWHMMNNQKKPAPP-UHFFFAOYSA-L potassium carbonate Substances [K+].[K+].[O-]C([O-])=O BWHMMNNQKKPAPP-UHFFFAOYSA-L 0.000 description 1
- UAJUXJSXCLUTNU-UHFFFAOYSA-N pranlukast Chemical compound C=1C=C(OCCCCC=2C=CC=CC=2)C=CC=1C(=O)NC(C=1)=CC=C(C(C=2)=O)C=1OC=2C=1N=NNN=1 UAJUXJSXCLUTNU-UHFFFAOYSA-N 0.000 description 1
- 229960004583 pranlukast Drugs 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はマ） １１ツクス型半導体装置に係り、特に・
絶縁基板に形成したマ） ＋１ツクス型半導体装置に係
る。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a
This invention relates to a +1x type semiconductor device formed on an insulating substrate.
絶縁基板上に半導体素子を形成する技術は・Ｓ ＯＳ（
５ｉｌｉｃｏｎ ｏｎ ５ａｐｐｈｉｖｅ ）技術とし
て古くから研究されており、高速性、耐放射線性の優れ
た素子が製造されるに到っている。しかし基板となるサ
ファイアが高価であるため、その使用範囲７５！限られ
ている。The technology for forming semiconductor elements on an insulating substrate is SOS (
It has been studied for a long time as a 5ilicon on 5apphive) technology, and elements with excellent high speed and radiation resistance have been manufactured. However, because the sapphire substrate is expensive, its usage range is 75! limited.
最近ＳＯＳに代り得る技術としてＳ ＯＩ（Ｓｉｌｉｃ
ｏｎｏｎ ：［ｎ５ｕｌａｔｏｒ）技術が検討されてい
る。これはシリコンなどの半導体層を石英板、ガラス板
。Recently, SOI (Silicon) is a technology that can replace SOS.
onon: [n5lator) technology is being considered. This is a semiconductor layer such as silicon on a quartz plate or a glass plate.
５ｉ０２膜等の絶縁基体の上に形成する技術である。例
えば・石英基板上に多結晶シリコン膜を形成した後に・
レーザー光、抵抗加熱による線状ヒーター・高周波加熱
による線状ヒーター等を走査あるいは移動させることに
より、多結晶シリコン膜を溶融し・再結晶化させる。再
結晶化させることによりシリコン層の粒子径は非常に犬
きくなり、半導体素子を形成した場合、多結晶シリコン
膜に形成した場合より・著しく特性の向上した素子が得
られるようになる。This is a technique for forming on an insulating substrate such as a 5i02 film. For example, after forming a polycrystalline silicon film on a quartz substrate,
By scanning or moving a laser beam, a linear heater using resistance heating, a linear heater using high frequency heating, etc., the polycrystalline silicon film is melted and recrystallized. By recrystallizing, the grain size of the silicon layer becomes extremely large, and when a semiconductor element is formed, it becomes possible to obtain an element with significantly improved characteristics than when formed on a polycrystalline silicon film.
このように、絶縁基板上に形成したＳＯＩ型半導体装置
の応用目的としては、ＳＯ８と同じ高速性や耐放射線性
のほか、三次元素子、基板の透明性を利用した光学表示
素子の実現等が考えられている。In this way, the application purposes of SOI type semiconductor devices formed on insulating substrates include the realization of optical display elements that utilize tertiary elements and the transparency of the substrate, in addition to the same high speed and radiation resistance as SO8. It is considered.
ところで、これらの応用に供するためには、ＳＯＩに形
成した素子の特性を十分に認識する必要がある。例えば
ＳＯＩで形成したＭＯ８素子のスイッチング特性は・単
結晶シリコンに形成した素子とほぼ同等になってきてい
る。しかしながら・８０Ｉで形成した半導体層の中には
・特有の粒界が存在しており・この粒界が・素子を形成
する場合の異常拡散や・伝導におけるキャリアの散乱を
引き起し、素子の特性を大きく左右する。したがって、
ＳＯＩで形成した場合は、このような粒界の性質を十分
解明し、有効に利用することが必要となる。By the way, in order to use the device for these applications, it is necessary to fully understand the characteristics of the device formed on SOI. For example, the switching characteristics of an MO8 element formed of SOI are becoming almost equal to those of an element formed of single crystal silicon. However, there are unique grain boundaries in the semiconductor layer formed with 80I, and these grain boundaries cause abnormal diffusion when forming devices and scattering of carriers during conduction. It greatly influences the characteristics. therefore,
When forming SOI, it is necessary to fully elucidate the properties of such grain boundaries and use them effectively.
本発明の目的は、ＳＯＩの特徴を生かした新規なマトリ
ックス型半導体装置を提供する点にある。An object of the present invention is to provide a novel matrix type semiconductor device that takes advantage of the characteristics of SOI.
具体的には、アクティブマトリックスを構成する素子群
とシフトレジスタを構成するＭＯ８型素子群とを同一基
板に一体化した新規なマトリックス型半導体装置を提供
する点にある。Specifically, the present invention provides a novel matrix type semiconductor device in which a group of elements constituting an active matrix and a group of MO8 type elements constituting a shift register are integrated on the same substrate.
本発明はマトリックス型半導体装置の特徴とするところ
は、ＳＯＩ基板の半導体層の所定の領域にアクティブマ
トリックスを構成する素子群を形成し、他の領域にシフ
トレジスタを構成するＭＯ８型素子群を形成し、かつＭ
Ｏ８型素子群はそのチャンネル方向が実質的に半導体層
の粒界の方向となっている点にある。The feature of the matrix type semiconductor device of the present invention is that a group of elements constituting an active matrix is formed in a predetermined region of a semiconductor layer of an SOI substrate, and a group of MO8 type elements constituting a shift register is formed in another region. And M
The O8 type device group is characterized in that its channel direction is substantially in the direction of the grain boundaries of the semiconductor layer.
本発明は、発明者らの以下の検討に基づいてなされたも
のである。The present invention was made based on the following studies by the inventors.
第１図はＭＯＳＦＥＴ のチャンネル長とリーク電流と
の関係を示したものである。Ａは・結晶化の際のレーザ
ーのスキャン方向と平向な方向にキャリアが流れるよう
にチャネルを形成した場合で、Ｂは、レーザーのスキャ
ン方向と直角にチャンネルを形成した場合である。Ｂで
はチャンネル長が小さくなってもわずかにリーク雪１流
が増加する程度であるが・Ａの場合、チャンネル長が５
μｍ以下とがると、リーク電流が急増する。FIG. 1 shows the relationship between MOSFET channel length and leakage current. A is a case in which a channel is formed so that carriers flow in a direction parallel to the laser scanning direction during crystallization, and B is a case in which a channel is formed perpendicular to the laser scanning direction. In case B, even if the channel length becomes smaller, the amount of leaked snow increases slightly, but in case A, the channel length is 5.
When the peak is less than μm, the leakage current increases rapidly.
第２図はチャンネル長と電界効果移動度との関係を示す
。Ａ、Ｂの定義は第１図と同じであり、チャンネル長が
小さくなる程電界効果移動度は大きくなり、ＢよりＡの
方か大きい点が特徴となっている。FIG. 2 shows the relationship between channel length and field effect mobility. The definitions of A and B are the same as in FIG. 1, and the smaller the channel length, the greater the field effect mobility, and the characteristic is that A is larger than B.
以上の結果は次のように説明できる。ここでＭＯ８ＦＥ
Ｔ’を例にとって説明する。第３図は、第１図のＡに示
した、レーザーの結晶化方向とチャンネルの方向を平行
にした例である。石英板上に形成したシリコン層１を結
晶化させるため、図中の矢印方向にレーザー光をスキャ
ンする。この時１粒界はスキャン方向に平行に発生する
性質がある。こうして結晶化した後、セルフアライメン
ト法を使い、ソース２．ドレイン３．ゲー）４を形成す
る。ｎチャンネル型の場合にはリンをイオン注入または
熱拡散で拡散する。このとき、レーザー光のスキャニン
グ方向に走る粒界６に沿って、リンが異常拡散を起し正
常なソース・ドレイン接合５より中側に、異常拡散層７
が形成される。この異常拡散層７が大きい場合は・ソー
ス・ドレイン接合５が短絡しやすくなる。この限界は、
レーザー結晶化の側ではチャンネル長が約５μｍであり
・これエリチャンネル長が小さくなると、第１図Ａに示
すようにリーク電流が急増することになるＯ
第４図は、第１図Ｂに示した、レーザーの結晶化方向と
チャンネルの方向を直角にし食倒である０この場合、チ
ャンネルの方向と直角方向に粒界が走ることに々る。ソ
ース・ドレイン接合５が形成される時、やはり第３図と
同様に粒界６に沿って異常拡散層７が形成される。しか
しこの場合、異常拡散層はチャンネルと直角の方向に延
びるだけであり、実効的なチャンネル長が小さくなるこ
とはほとんどない。したがって、第１図Ｂに示すように
、チャンネル長が短かくなってもリーク電流が著しく増
すようなことはない。The above results can be explained as follows. Here MO8FE
This will be explained using T' as an example. FIG. 3 is an example in which the crystallization direction of the laser and the direction of the channel are parallel to each other, as shown in A of FIG. In order to crystallize the silicon layer 1 formed on the quartz plate, a laser beam is scanned in the direction of the arrow in the figure. At this time, one grain boundary has the property of occurring parallel to the scanning direction. After crystallizing in this way, using the self-alignment method, source 2. Drain 3. Game) form 4. In the case of an n-channel type, phosphorus is diffused by ion implantation or thermal diffusion. At this time, phosphorus undergoes abnormal diffusion along the grain boundaries 6 running in the scanning direction of the laser beam, and an abnormal diffusion layer 7 is formed inside the normal source-drain junction 5.
is formed. If the abnormal diffusion layer 7 is large, the source/drain junction 5 is likely to be short-circuited. This limit is
On the laser crystallization side, the channel length is approximately 5 μm, and as the channel length becomes smaller, the leakage current increases rapidly as shown in Figure 1A. Figure 4 is as shown in Figure 1B. In addition, the crystallization direction of the laser and the direction of the channel are perpendicular to each other. In this case, grain boundaries often run in a direction perpendicular to the direction of the channel. When the source/drain junction 5 is formed, an anomalous diffusion layer 7 is also formed along the grain boundaries 6 similarly to FIG. However, in this case, the anomalous diffusion layer only extends in a direction perpendicular to the channel, and the effective channel length is hardly reduced. Therefore, as shown in FIG. 1B, even if the channel length is shortened, the leakage current does not increase significantly.
一方、第２図の結果は次のように説明できる。On the other hand, the results shown in FIG. 2 can be explained as follows.
粒界は結晶欠陥の集合体であり・キャリアの散乱原因と
なる。ところで、第１図Ａ（第３図）のように粒界を位
置させると、ソースから出たキャリアは、粒界のない部
分を走ってドレインに到達することができる。したがっ
て、粒界により走行がさ１ｆｃげられることはない。逆
に第１図Ｂ（第４図）のように粒界を形成した場合、キ
ャリアは必ず粒界を通らざるを得なくカリ・散乱されて
電界効果移動度がＡより低下することになる。Grain boundaries are aggregates of crystal defects and cause carrier scattering. By the way, if the grain boundaries are located as shown in FIG. 1A (FIG. 3), carriers emitted from the source can reach the drain by running along the part where there is no grain boundary. Therefore, the running speed is not reduced by 1 fc due to grain boundaries. Conversely, when grain boundaries are formed as shown in FIG. 1B (FIG. 4), carriers are forced to pass through the grain boundaries and are scattered by potash, resulting in a field effect mobility lower than that in A.
以上の結果から、正常な特性は、粒界との関係で決定さ
れることになる。すなわち、レーザーアニールによる結
晶化法の場合では、Ａの方法で得られる最小のチャンネ
ル長は約５μｍとなる。したがってＶＬＳＩ等には無理
があり、さらに微細化するにはＢの方法を採用すること
が必要となる。From the above results, normal properties are determined by the relationship with grain boundaries. That is, in the case of the crystallization method using laser annealing, the minimum channel length obtained by method A is about 5 μm. Therefore, it is unreasonable for VLSI etc., and it is necessary to adopt method B for further miniaturization.
しかしながらこの場合は電界効果移動度が小さくなるの
で、Ａの場合より素子のスピードは低下することになる
。However, in this case, the field effect mobility becomes smaller, so the speed of the element will be lower than in case A.
以上ではレーザー光による結晶化法と素子の特性との関
係を説明した。しかし結晶化法により、半導体層の結晶
性が種々に異なってくる。またソース・ドレインの形成
法など素子製作条件によって異常拡散の程度が異なる。The relationship between the crystallization method using laser light and the characteristics of the device has been explained above. However, the crystallinity of the semiconductor layer varies depending on the crystallization method. Furthermore, the degree of abnormal diffusion differs depending on device manufacturing conditions such as the method of forming the source and drain.
したがって・特性が得られる限界の素子寸法も異なって
くる。異方る例として、線状のヒーターで結晶化させる
場合はレーザー光による結晶化より格段に大きなサイズ
の結晶粒の結晶層を得ることが可能で・粒界の数も少な
くなる。またソース・ドレインを形成する場合、イオン
注入法で形成し短時間に低温でアニールする方法によれ
ば、異常拡散をさらに小さくすることが可能であり・両
者の結晶化法と製作法を合せれば、Ａの方法で可能な素
子のチャンネル長の限界は３〜５μｍとなる。またＡの
電界効果移動度はＢの約２倍となる。Therefore, the critical element dimensions at which the characteristics can be obtained also differ. As an anisotropic example, when crystallizing with a linear heater, it is possible to obtain a crystal layer with significantly larger crystal grains than with crystallization using laser light, and the number of grain boundaries is also reduced. In addition, when forming sources and drains, anomalous diffusion can be further reduced by forming them using ion implantation and annealing them at low temperatures in a short period of time. For example, the limit of the channel length of the device that can be achieved using method A is 3 to 5 μm. Further, the field effect mobility of A is approximately twice that of B.
以上述べた事実関係に基づきＳＯＩでマトリックス型半
導体装置を形成する場合、上述したように、高速動作が
要求されるシフトレジスタの各ＭＯ８型素子をＡタイプ
とすることにより、実用的なシフトレジスタを得ること
ができる。When forming a matrix type semiconductor device using SOI based on the above-mentioned facts, as mentioned above, by making each MO8 type element of the shift register that requires high-speed operation to be A type, a practical shift register can be created. Obtainable.
平面表示素子として、液晶を使ったアクティブマトリッ
クス型半導体装置を実施例として述べる。An active matrix type semiconductor device using liquid crystal as a flat display element will be described as an example.
アクティブマトリックス型液晶表示装置は第５図に示し
た部分図のように・各画素に設けられたＭＯ８ＦＥＴＩ
Ｏと、そのソース側に接続される液晶セル１１から成り
・ドレイン１２・ゲート１３は共通と力って結線されて
いる。ドレイン１２に、駆動低圧を印加し、ゲート１３
の信号でＭＯ８ＦＥＴ１０’ｉオンさせると液晶セル１
１が駆動されて、情報が表示される。高精細の表示とす
るには、数千の画素をマトリックス状に配置することに
力る。このような表示装置は裏面から光を透過させて液
晶により表示させるため、透明基板を使っており、ＭＯ
Ｓ ＦＥＴ１０を形成するにはＳＯＩ技術が使われる。As shown in the partial diagram in Figure 5, an active matrix type liquid crystal display device has MO8FETI provided in each pixel.
The liquid crystal cell 11 is connected to the source side of the liquid crystal cell 11, and the drain 12 and gate 13 are commonly connected. A driving low voltage is applied to the drain 12, and the gate 13
When MO8FET10'i is turned on with the signal, liquid crystal cell 1
1 is activated to display information. High-definition display requires arranging thousands of pixels in a matrix. Such display devices use transparent substrates to transmit light from the back side and display on liquid crystals, and MO
SOI technology is used to form S FET 10.
このＭＯ８ＦＥＴＩＯは液晶に電圧を印加し、その電圧
を保持するためにスイッチ機能が必要であり、オン抵抗
が小さく。This MO8FETIO applies a voltage to the liquid crystal and requires a switch function to maintain that voltage, and has a small on-resistance.
オフ抵抗の大きいことが要求される。ところでＳＯＩ技
術で形成されるＭＯＳＦＥＴの特性は、はぼこの条件を
満すことができる。A large off-resistance is required. By the way, the characteristics of a MOSFET formed using SOI technology can satisfy the conditions of lava.
ところでこのＭＯＳＦＥＴのマトリックスを駆動するに
は、ドレインの信号と、ゲートの信号を順次走査するた
めのシフトレジスター（駆動回路）が必要である。第６
図は、シフトレジスターを設けたマトリックス型半導体
装置を示す。マトリックス２０からドレイン２１、ゲー
ト２２は、Ｘ方向シフトレジスタ２３．Ｙ方向シフトレ
ジスタ２４、さらに信号発生器２５．２６に接続されて
いる。ところでシフトレジスタは信号をマトリックス２
０の画素に伝え々がら走査する機能を有するものである
。Ｙ方向に走査しなからＸ方向に走査する場合、Ｘ方向
に走査する周波数は、Ｘ方向の画素数倍だけＹ方向の周
波数より大きいことが必要となる。し本がって、このよ
うなシフトレジスタを構成するＭＯＳＦＥＴには高速性
が要求される。画素数が犬きく々るほど高速性が重要と
なる。例えば画素数が２００Ｘ２００の場合、少なくと
も約ＩＭＨｚ以上で動作するシフトレジスターが必要で
あり・シフトレジスターを構成するＭＯ８’ＦＥＴにも
この速度が必要となる。このような高速性を実現するに
は・できるだけ電界効果移動度の大きいＭＯ８ＦＥＴ素
子を使用することが不可欠である。８０Ｉ技術でＭＯ８
ＦＥＴ＝を形成する場合、前述したように粒界が存在す
ることから、その方向性で特性が異なるが、高速性の観
点からは、粒界の方向と平行にチャンネルを形成した構
造が有利となる。ところがこの場合、異常拡散による実
効チャンネル長の減少の観点から、素子のチャンネル長
に制限がある。すなわち前述したように、チャンネル長
を３〜５μｍ以上にしなければならない。ところが、液
晶表示素子に使うシフトレジスタやスイッチング素子は
比較的大きいため、チャンネル長を３〜５μｍ以上にす
ることが可能である。すなわち、粒界の方向とチャンネ
ルの方向を平行とすることにより、実用的なマ） ＋）
ックス型半導体装置が可能とがる。By the way, in order to drive this matrix of MOSFETs, a shift register (drive circuit) is required to sequentially scan the drain signal and the gate signal. 6th
The figure shows a matrix type semiconductor device provided with a shift register. The drain 21 and gate 22 from the matrix 20 are connected to an X direction shift register 23 . It is connected to the Y-direction shift register 24 and further to signal generators 25 and 26. By the way, the shift register transfers the signal to matrix 2.
It has a function of scanning while transmitting information to the 0 pixel. When scanning in the X direction without scanning in the Y direction, the frequency for scanning in the X direction needs to be higher than the frequency in the Y direction by the number of pixels in the X direction. Therefore, the MOSFETs forming such a shift register are required to have high speed. The higher the number of pixels, the more important high speed becomes. For example, when the number of pixels is 200x200, a shift register that operates at least at approximately IMHz or higher is required, and the MO8'FET that constitutes the shift register also requires this speed. In order to achieve such high speed, it is essential to use a MO8FET element with as high field effect mobility as possible. MO8 with 80I technology
When forming a FET=, since there are grain boundaries as mentioned above, the characteristics differ depending on the direction of the grain boundaries, but from the viewpoint of high speed, a structure in which channels are formed parallel to the direction of the grain boundaries is advantageous. Become. However, in this case, there is a limit to the channel length of the device from the viewpoint of a reduction in the effective channel length due to anomalous diffusion. That is, as mentioned above, the channel length must be 3 to 5 μm or more. However, since shift registers and switching elements used in liquid crystal display elements are relatively large, it is possible to increase the channel length to 3 to 5 μm or more. In other words, by making the grain boundary direction parallel to the channel direction, practical ma) +)
A box-type semiconductor device becomes possible.
本発明により、８０Ｉ基板を用いてシフトレジスタ等が
十分な高速性を有するマトリックス型半導体装置が実現
できる。According to the present invention, it is possible to realize a matrix type semiconductor device in which a shift register and the like have sufficient high speed performance using an 80I substrate.
第１図は本発明の詳細な説明するためのチャンネル長と
リーク電流との相関図、第２図は同じく本発明の詳細な
説明するためのチャンネル長と電界効果移動度との相関
図、第３図及び第４図は本発明の詳細な説明するための
ＭＯ８ＦＥＴ部分平面図、第５図は本発明の詳細な説明
するためのアクティブマトリックス部分図、第６図は本
発明の詳細な説明するためのマトリックス型半導体装置
のブロック図である。
１・・・シリコン層、２・・・ソース％３・・・ドレイ
ン、４・・・ゲー）、５・・・ソース・ドレイン接合、
６・・・粒界。
７・・・異常拡散層、２０・・・マトリックス、２３・
・・Ｘ方向シフトレジスタ、２４・・・Ｙ方向シフトレ
ジス１１図
÷ヤ＞ネＩＬ、長 らμｍ−ン
茅２図
１ ５ １０ ２０
÷ヤ〉ネ１し長 （矛ｔ−ｙｎ）
￥３因
Ｖｔｕ
′″Ｉ！Ｊ５図
ＩＯ１０
Ｙ６図
３
２２ ２０FIG. 1 is a correlation diagram between channel length and leakage current for explaining the present invention in detail, FIG. 2 is a correlation diagram between channel length and field effect mobility for explaining the present invention in detail, and FIG. 3 and 4 are partial plan views of MO8FET for detailed explanation of the present invention, FIG. 5 is a partial plan view of an active matrix for detailed explanation of the present invention, and FIG. 6 is a detailed explanation of the present invention. FIG. 2 is a block diagram of a matrix type semiconductor device for use in the present invention. DESCRIPTION OF SYMBOLS 1...Silicon layer, 2...Source%3...Drain, 4...Ga), 5...Source-drain junction,
6...Grain boundary. 7... Abnormal diffusion layer, 20... Matrix, 23.
... Vtu '''I! J5 Figure IO10 Y6 Figure 3 22 20
Claims (1)
した半導体薄層ヲ有する半導体基板の半導体薄層の所定
の領域にマ） ＋１ツクス状に配置した第１の素子群と
・この第１の素子群を制御するために半導体薄層の他の
領域に配列されたＭＯ８型素子からなる第１の素子群と
を有し、半導体薄層の他の領域の粒界の方向とキャリア
の移動方向が実質的に同一となる方向に形成したことを
特徴とするマトリックス型半導体装置。1. A first element group arranged in a +1x shape in a predetermined region of a semiconductor thin layer of a semiconductor substrate having a semiconductor thin layer provided on an insulating plate and crystallized by applying energy; a first element group consisting of MO8 type elements arranged in another region of the semiconductor thin layer in order to control the element group of A matrix type semiconductor device characterized in that the semiconductor devices are formed in substantially the same direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24816283A JPS60143666A (en) | 1983-12-29 | 1983-12-29 | Matrix type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24816283A JPS60143666A (en) | 1983-12-29 | 1983-12-29 | Matrix type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60143666A true JPS60143666A (en) | 1985-07-29 |
Family
ID=17174136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24816283A Pending JPS60143666A (en) | 1983-12-29 | 1983-12-29 | Matrix type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60143666A (en) |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1991017471A1 (en) * | 1990-04-27 | 1991-11-14 | Japan As Represented By Director General Of Agency Of Industrial Science And Technology | Optical valve device |
| US5233211A (en) * | 1990-10-16 | 1993-08-03 | Agency Of Industrial Science And Technology | Semiconductor device for driving a light valve |
| US5347154A (en) * | 1990-11-15 | 1994-09-13 | Seiko Instruments Inc. | Light valve device using semiconductive composite substrate |
| US5434433A (en) * | 1992-08-19 | 1995-07-18 | Seiko Instruments Inc. | Semiconductor device for a light wave |
| US5574292A (en) * | 1992-05-13 | 1996-11-12 | Seiko Instruments Inc. | Semiconductor device with monosilicon layer |
| US5578865A (en) * | 1992-01-22 | 1996-11-26 | Kopin Corporation | Reduction of parasitic effects in floating body mosfets |
| US5633176A (en) * | 1992-08-19 | 1997-05-27 | Seiko Instruments Inc. | Method of producing a semiconductor device for a light valve |
| US5637187A (en) * | 1990-09-05 | 1997-06-10 | Seiko Instruments Inc. | Light valve device making |
| JPH11121753A (en) * | 1997-10-14 | 1999-04-30 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| US6191476B1 (en) | 1992-10-21 | 2001-02-20 | Seiko Instruments Inc. | Semiconductor device |
| JP2003059831A (en) * | 2001-08-17 | 2003-02-28 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor device |
| JP2003086507A (en) * | 2001-09-10 | 2003-03-20 | Semiconductor Energy Lab Co Ltd | Method of manufacturing semiconductor device |
| US6608325B1 (en) | 1993-05-26 | 2003-08-19 | Semiconductor Energy Laboratory Co., Ltd. | Transistor and semiconductor device having columnar crystals |
| JP2004006644A (en) * | 2002-01-28 | 2004-01-08 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its fabricating method |
| US7422987B2 (en) | 2001-08-30 | 2008-09-09 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| JP2014239246A (en) * | 2002-01-28 | 2014-12-18 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| JP2021101464A (en) * | 2002-01-28 | 2021-07-08 | 株式会社半導体エネルギー研究所 | Semiconductor device |
-
1983
- 1983-12-29 JP JP24816283A patent/JPS60143666A/en active Pending
Cited By (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5982461A (en) * | 1990-04-27 | 1999-11-09 | Hayashi; Yutaka | Light valve device |
| WO1991017471A1 (en) * | 1990-04-27 | 1991-11-14 | Japan As Represented By Director General Of Agency Of Industrial Science And Technology | Optical valve device |
| US5637187A (en) * | 1990-09-05 | 1997-06-10 | Seiko Instruments Inc. | Light valve device making |
| US6067062A (en) * | 1990-09-05 | 2000-05-23 | Seiko Instruments Inc. | Light valve device |
| US5233211A (en) * | 1990-10-16 | 1993-08-03 | Agency Of Industrial Science And Technology | Semiconductor device for driving a light valve |
| USRE36836E (en) * | 1990-10-16 | 2000-08-29 | Agency Of Industrial Science And Technology | Semiconductor device for driving a light valve |
| US5926699A (en) * | 1990-10-16 | 1999-07-20 | Agency Of Industrial Science And Technology | Method of fabricating semiconductor device having stacked layer substrate |
| US5759878A (en) * | 1990-10-16 | 1998-06-02 | Agency Of Industrial Science And Technology | Method of fabricating semiconductor device having epitaxially grown semiconductor single crystal film |
| US5486708A (en) * | 1990-11-15 | 1996-01-23 | Seiko Instruments Inc. | Light valve device using semiconductive composite substrate |
| US5728591A (en) * | 1990-11-15 | 1998-03-17 | Seiko Instruments Inc. | Process for manufacturing light valve device using semiconductive composite substrate |
| US5572045A (en) * | 1990-11-15 | 1996-11-05 | Seiko Instruments Inc. | Light valve device using semiconductive composite substrate |
| US5347154A (en) * | 1990-11-15 | 1994-09-13 | Seiko Instruments Inc. | Light valve device using semiconductive composite substrate |
| US5578865A (en) * | 1992-01-22 | 1996-11-26 | Kopin Corporation | Reduction of parasitic effects in floating body mosfets |
| US5574292A (en) * | 1992-05-13 | 1996-11-12 | Seiko Instruments Inc. | Semiconductor device with monosilicon layer |
| US5633176A (en) * | 1992-08-19 | 1997-05-27 | Seiko Instruments Inc. | Method of producing a semiconductor device for a light valve |
| US6187605B1 (en) | 1992-08-19 | 2001-02-13 | Seiko Instruments Inc. | Method of forming a semiconductor device for a light valve |
| US5434433A (en) * | 1992-08-19 | 1995-07-18 | Seiko Instruments Inc. | Semiconductor device for a light wave |
| US6191476B1 (en) | 1992-10-21 | 2001-02-20 | Seiko Instruments Inc. | Semiconductor device |
| US6608325B1 (en) | 1993-05-26 | 2003-08-19 | Semiconductor Energy Laboratory Co., Ltd. | Transistor and semiconductor device having columnar crystals |
| JPH11121753A (en) * | 1997-10-14 | 1999-04-30 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JP2003059831A (en) * | 2001-08-17 | 2003-02-28 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor device |
| US7393729B2 (en) | 2001-08-17 | 2008-07-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for fabricating semiconductor device |
| US7422987B2 (en) | 2001-08-30 | 2008-09-09 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| JP2003086507A (en) * | 2001-09-10 | 2003-03-20 | Semiconductor Energy Lab Co Ltd | Method of manufacturing semiconductor device |
| JP2004006644A (en) * | 2002-01-28 | 2004-01-08 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its fabricating method |
| JP2014239246A (en) * | 2002-01-28 | 2014-12-18 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| JP2021101464A (en) * | 2002-01-28 | 2021-07-08 | 株式会社半導体エネルギー研究所 | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS60143666A (en) | Matrix type semiconductor device | |
| JP3402400B2 (en) | Manufacturing method of semiconductor integrated circuit | |
| KR100374737B1 (en) | METHOD FOR FORMING TRANSISTOR, CIRCUIT CONTAINING THE TRANSISTOR, METHOD FOR PRODUCING ACTIVE MATRIX SUBSTRATE, METHOD FOR MANUFACTURING DISPLAY DEVICE, | |
| JP2999271B2 (en) | Display device | |
| KR100408324B1 (en) | Ultra-high resolution liquid crystal display on silicon-on-sapphire | |
| KR100546905B1 (en) | LlQUID DISPLAY APPARATUS | |
| JP3109968B2 (en) | Method for manufacturing active matrix circuit board and method for manufacturing liquid crystal display device using the circuit board | |
| JP4366732B2 (en) | Method for manufacturing electro-optical device and method for manufacturing drive substrate for electro-optical device | |
| KR20010071526A (en) | Thin film transistor and liquid crystal display | |
| JP2000243970A (en) | Thin film transistor, manufacture thereof, liquid crystal display device using the same and manufacture thereof | |
| JP2001127302A (en) | Semiconductor thin-film substrate, semiconductor device as well as manufacturing method therefor, and electronic device | |
| JPH01194351A (en) | Thin film semiconductor device | |
| KR100527576B1 (en) | N-channel insulated gate thin-film transister and liquid crystal display apparatus using the same | |
| JP3386682B2 (en) | Thin film transistor, logic gate device, and thin film transistor array | |
| US6940483B2 (en) | Method for driving display device having digital memory for each pixel | |
| JP2000243968A (en) | Thin film transistor, manufacture thereof, liquid crystal display device using the same and manufacture thereof | |
| JPH0142146B2 (en) | ||
| JP2635542B2 (en) | Thin film transistor | |
| JP2000243969A (en) | Thin film transistor, manufacture thereof, liquid crystal display device using the same and manufacture thereof | |
| JP4257482B2 (en) | THIN FILM TRANSISTOR, ITS MANUFACTURING METHOD, CIRCUIT USING THE SAME, AND LIQUID CRYSTAL DISPLAY DEVICE | |
| JP3276900B2 (en) | Semiconductor device and display device | |
| KR950009797B1 (en) | Fid poly silicon tft with bottom gate | |
| JP4366731B2 (en) | Method for manufacturing electro-optical device and method for manufacturing drive substrate for electro-optical device | |
| JP2000231122A (en) | Electrooptical device, driving board for electrooptical device, and their production | |
| KR100194676B1 (en) | Transfer gate device |