JPS60143498A - Semiconductor input circuit - Google Patents

Abstract

PURPOSE:To allow interruption of the supply current which flows at the time of waiting by providing a transistor between a VCC terminal and an MOS transistor on the VCC terminal side, which constitutes an inverter circuit, and by giving a constant voltage which is lower than the VCC voltage. CONSTITUTION:Since the current from a load MOS transistor 17 is small, the voltage of a connecting point 24 is decided by overlapping of threshold voltages of MOS transistors 18-23. When the voltage is impressed on the gate electrode of an MOS transistor 15, the MOS transistor 15 executes the operation of the source follower, and a voltage V16 which is lower than the voltage of the gate electrode of the MOS transistor 15 by the threshold voltage, appears at a connecting point 16. Under this condition, the voltage difference between the source electrode of an MOS transistor 3 and the gate electrode becomes smaller than the threshold voltage from the aspect of the absolute vale even if ''1'' level of a CS signal lowers, the MOS transistor 3 turns off, and the supply current does not flow.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an input circuit for a semiconductor integrated circuit using MOS transistors, and particularly to a low power consumption input circuit that is effective for use in a semiconductor memory circuit.

[Prior art]

Generally, a semiconductor memory system is composed of a large number of semiconductor elements. In such a memory system,
Therefore, reading or writing of necessary data is performed only in the memory element designated by the address, and the other elements are placed in a standby state. This operation is called chip select, and the memory element is provided with a terminal (plane terminal or σπ terminal) to which a signal (102 or a) for controlling this operation is applied. When the level of the n signal applied to the ε1 terminal is “L”, the storage element is in the read or write operation state.
”, it goes into standby mode.

Normally, in the operating state, the internal circuit of the element operates, so the power supply current becomes large, and in the standby state, the internal circuit does not operate, so the current decreases. This situation is shown in FIG. In the same figure, +al indicates the n signal, and in the same figure, C) indicates the power supply current Ice, and the current value 1 ccA during operation is several tens of mA.

In a memory system that is backed up by a battery in the event of a power outage, the standby current T cc in Figure 1 is
It is required that s be as small as possible, and currently it is several tens of microns.
Grade A products are generally manufactured.

FIG. 2 shows an input circuit used in this type of memory element. In the figure, 1 is a power supply terminal, 2 is an input terminal to which the σ signal is applied, and 3 and 4 are MOS transistors with opposite conductivity connected in series between the power supply terminal 1 and the ground. The electrodes are connected to a common input terminal 2, forming a complementary MOS inverter circuit 30 which receives the above surface signal as input. In the inverter circuit 30, a P-channel MOS transistor 3 is connected to the power supply terminal 1 side, and an N-channel MOS transistor 4 is connected to the ground side. 5 is an output terminal of the inverter circuit 30. Further, 40 is a complementary MOS inverter circuit configured similarly to the above inverter circuit 30, and the output terminal 5 of the above inverter circuit 30 is directly connected to the input terminal of this complementary MOS inverter circuit.

8 is an output terminal of the inverter circuit 40, and an output signal C8° is obtained at this output terminal 8.

Reference numeral 9 denotes an input terminal to which address signal A, which is one of the input signals of the storage element, is applied. Reference numerals 10 and 11 designate MOS transistors having opposite conductivity and connected in series, each having its gate electrode connected to a common input terminal 9.

12 is an MO with the same conductivity as the above MO3) transistor lO
S) A transistor connected in series with the M6S transistor 10. 13 is the above MOS transistor 11
is a MoS transistor having the same conductivity as , and is connected in parallel with the MOS transistor 11 . And both MO3
The gate electrodes of each of the I-transistors 12, 13 are connected to the output terminal 8 of the inverter circuit 40, so that the U signal from the inverter circuit 40 is applied thereto.

In FIG. 2, A is used as the address signal of the memory element.
o is shown, but other input signals (A1゜A2...
, DIN, R/W') is also the same as the above MO.
3) It is omitted because it has the same configuration as the transistors 10 to 13.

Next, the operation of the circuit shown in FIG. 2 will be explained using the waveform diagram shown in FIG. The waveforms in FIG. 3 indicate that the memory element at the address where address signal AO="0" performs a memory operation.

First, at time t1, the Ao multiplication signal is “0” for address specification.
Changes to However, since the ζ/NO signal is "1", the 1' signal is "1", the MOS transistor 13 is turned on, and the address signal Ao remains at "O".

Next, at time t2, when the surface signal changes to "0", the MOS signal changes to "0", and the MOS) transistor 12 turns on, MOS
)-77 resistor 13 is turned off, (MOS) transistor 10 is already turned on and transistor 11 is turned off], so the 6' signal becomes "1". The level of this heart signal is transmitted to a decoder circuit (not shown) of this element, a designated memory cell is selected, and data is then read or written.

When the above memory operation is completed, the 600 signal becomes "1" again at time t3.
”. In this case, the same as time t1.

The signal becomes 1", MOS) transistor 12 becomes 0, FF
, MOS) transistor 13 is turned on, and the voltage signal becomes A.
The o times signal becomes "0" regardless.

Therefore, even if the Ao multiplied signal changes to "1" at time t4, the Aθ signal input circuit does not operate.

Figure 3 (fl shows the power supply current waveform of the personal power circuit. As shown in the figure, at times t2 and t3, the input circuit provided for the σ100 signal, A, and A transient current flows when the inverter circuit operates.This current flows through the P-channel M
The current flows when the O3I transistor and the N-channel MO3 transistor are turned on simultaneously at a predetermined time.

What should be considered here is the current that flows during the period when the σ3 signal is l", that is, during standby. This current depends on the input level of the plane signal. Specifically, the level of the τ100 signal is the same as the power supply voltage ( = Vcc), then the MOS) transistor 3 is completely OFF and no power supply current flows (only the leakage current from the P-N junction as shown by the solid line in Figure 3 + fl).However, the level of the C8 signal is TTL. level, i.e. 2
．． In the case of 4■, if Vcc = 5V, the threshold voltage of MOS transistor 3 is set to about -0.5V, so the voltage difference between the input and Vce (2.4V -5V = -
2,6■) exceeds the threshold voltage of MOS) transistor 3 -〇,5V, MO3I-transistor 3 is turned on.
However, a current of several mA as shown by the broken line fl in FIG. 3 (fl) will flow. This current value is unacceptable when bank-up with batteries.

For this reason, conventionally, for such applications, a pull-up resistor was provided between the output of the TTL circuit that drives the C8 circuit and the power supply terminal to raise the TTL output level to the power supply voltage Vcc and reduce the current during standby. I'm trying to reduce it.

However, providing a pull amplifier resistor has the drawback of increasing mounting space.

[Summary of the invention]

The present invention has been made in order to eliminate the drawbacks of the conventional ones as described above, and an L transistor is provided between the Vcc terminal and the MO3) transistor on the Vcc terminal side constituting the inverter circuit, and the gate electrode of this transistor is It is an object of the present invention to provide a semiconductor input circuit that can cut off the power supply current flowing during standby by applying a constant voltage lower than the Vcc voltage to the input circuit.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a circuit diagram showing one embodiment of the present invention.

In the figure, the same reference numerals as in FIG. 2 indicate the same parts. 4 is an N-channel MOS transistor (first
(MOS) transistor), 3 has one main electrode as the above MO
3) A P-channel MO transistor (second MO5L run transistor) connected to the other main electrode of the transistor 4 and whose gate electrode is connected to the input terminal 2; In addition, one main electrode of 15 is the MO3) transistor 3.
The other main electrode of the N-channel MOS transistor (third MO3I-
). 16 is a connection point between MOS transistors 15 and 3;

17 to 23 are N-channel MOS) transistors connected in series between the power supply terminal 1 and the ground (first power supply terminal); 17 is a high resistance load Mos transistor; 18 to 23
is a MOS transistor whose drain and gate electrodes are connected. 24 is MOS) transistors 17 and 18~2
This is the connection point with 3. And 50fJ (MOS) in the figure
This is a voltage ordering circuit that applies a constant voltage lower than the power supply voltage to the gate electrode of the transistor 15.

Next, the operation of the circuit shown in FIG. 4 will be explained.

In a circuit where the power supply voltage Vcc is 5V as shown in Fig. 4,
The threshold voltage of the N-channel MOS transistor is usually set to about 0.5V for 3M. Further, the high resistance MO3) transistor 17 only supplies voltage to the connection point 24, and is set to have a very high resistance of, for example, IMΩ.

Since the current flowing through the load transistor 17 is reduced in this way, the voltage at the connection point 24 is determined by the accumulation of the threshold voltages of the transistors 18 to 23 (MOS). In the case of Fig. 4, six MO3) transistors are connected, so the voltage V24 at the connection point 24 is 0.5V x 6 = 3V.
becomes. Next, when this voltage is applied to the gate electrode of the MOS transistor 15, the MOS transistor 15 performs a so-called source follower operation, and the connection point 16 has an M
The voltage of the gate electrode of the OS transistor 15 is higher than that of the MOS transistor 15.
Voltage V16 lower by the threshold voltage (=0.5V) of transistor 15 = 3V -0.5V = 2.5V
appears.

In this state, the "1" level of the surface signal is 2.4■
Even if the voltage difference V1 between the source electrode [connection point 16] and the gate electrode [input terminal 2] of the MOS transistor 3
B-V2 is 2.5V-2,4V=0. IV, which is smaller in absolute value than the threshold voltage of the MOS transistor 3, so the Mo3 transistor 3 is turned off and no power supply current flows.

However, when the ■signal is "0", the level of the "1" output voltage at the connection point 5 is 2.5■.
Power supply current flows through 7. However, the current in this case is a current during operation, and is only a few percent of the total current during operation, so it does not pose a problem.

As described above, in this embodiment, the Mo3I-transistor 15 is provided between the input circuit for the σ100 signal and the power supply terminal, and the
3) Since a constant voltage from a voltage generation circuit provided between the power supply terminal and the ground is applied to the gate electrode of the transistor 15, the power supply current of the σI input circuit is reduced even if the e1 input signal is at TTL level. It can be shut off, eliminating the need for a pull-up resistor provided in conventional circuits, which has the effect of saving mounting space.

Further, the increase in power supply current due to the provision of the voltage generating circuit 50 is approximately (5V-3V)/IMΩ-2 μA, which is sufficiently smaller than the allowable current of the Vanteri Puff Assop.

In this embodiment, a case has been described in which a positive polarity power source is used, but it is also possible to perform the process using a negative polarity power source by reversing the polarity of each signal and the polarity of the MOS transistor.

Furthermore, although this embodiment describes the case of a memory element, the present invention can be applied to any semiconductor integrated circuit that has an active state and a standby state, and the same effects as in the above embodiment can be obtained. It will be done.

〔Effect of the invention〕

As described above, according to the present invention, a MoS transistor is provided between a τ circuit and a power supply terminal for controlling the operating state and standby state in a semiconductor integrated circuit, and the MoS transistor is
Since the voltage of the constant voltage generation circuit installed between the power supply terminal and the ground is applied to the gate electrode of the transistor, the power supply current flowing during standby is reliably cut off even when the input signal of the C8 circuit is at TTL level. This has the effect of reducing power consumption and saving mounting space.

[Brief explanation of drawings]

Fig. 1 is a CS signal and power supply current waveform diagram of a semiconductor integrated circuit with 5 manpower, Fig. 2 is a circuit diagram of a conventional σ-input circuit,
FIG. 3 is a waveform diagram of various parts of the circuit of FIG. 2, and FIG. 4 is a circuit diagram showing an embodiment of the present invention. 4... first Mo3) transistor, 3... second M
o3) Ranjisku, 15... Third Mo3I-ransistor, 1... Second power supply terminal, 50... Voltage generating circuit, 17-23... N-channel Mo3) transistor. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3 t1t2t3t4 Figure 4

Claims (1)

[Claims] (1) A circuit for inputting signals to a semiconductor integrated circuit, wherein one main electrode is connected to a first power supply terminal, the other main electrode is connected to an output terminal, and a gate electrode is connected to an input terminal.
O3I-transistor, and the first MO having one main electrode connected to the output terminal and a gate electrode connected to the input terminal.
S) a second MOS transistor of opposite conductivity type to the transistor; one main electrode of the transistor is connected to the other main electrode of the second MOS transistor; a third MOS) transistor of the same conductivity type as the first MO'SI transistor, and a voltage generation circuit that applies a constant voltage smaller than the voltage of the second power supply terminal to the gate electrode of the third MOS transistor. A semiconductor input circuit characterized by comprising: