JP2000068815A - Integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an integrated circuit device that effectively interrupts supply of power in the power-down mode. SOLUTION: The integrated circuit device is provided with a NAND circuit ND1 that receives an output signal from a NAND circuit ND2 connecting to power supplies 18, 19, a PMOS transistor(TR) 26 whose source connects to the power supply 18, whose back-gate connects to the power supply 19, and whose gate connects to the NAND circuit ND1, and an NMOS TR 27 whose back-gate connects to a ground power supply 20, whose gate connects to a NOR circuit NR1 and whose source connects to the drain of the PMOS TR 26.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device, and more particularly to an integrated circuit device having a circuit that can be powered down by stopping power supply.

[0002]

2. Description of the Related Art With the spread of devices for supplying power to an integrated circuit by a battery, such as a cellular phone, the importance of reducing the power consumption of an integrated circuit device is increasing. In order to suppress the current consumption of the integrated circuit, it is conceivable to stop power supply to unused semiconductor elements according to the operation state of the device.

FIG. 6 shows a CM built in a conventional integrated circuit.
This is an OS type tristate driver circuit. FIG.
Is an example of an output circuit using the CMOS tristate driver circuit of FIG. In FIG. 7, in this operation, the output signal Q outputs "H", "L", "Z" (high impedance, hereinafter referred to as "Z") according to the values of the drive control signal EN and the output data signal D. . The power supply of all the logic gates is VDD. FIG. 8 is a truth table corresponding to the output circuit of FIG.

FIG. 9 shows a CMOS type level conversion circuit used for converting the voltage amplitude of a signal in a conventional integrated circuit. This is used to convert the voltage amplitude of an input / output signal between the integrated circuit and the outside when the voltage amplitude is larger than the voltage amplitude of an internal signal of the integrated circuit.
Decreasing the voltage amplitude of the internal signal of the integrated circuit is effective for suppressing the power consumption in the integrated circuit, and as a prior example, “HOT Chips 8-1996 Symp
“Strong ARM” processor described in “Osium Record Page 121”.

In FIG. 9, a signal DH and a signal DL are complementary inputs, and a signal QH and a signal QL are complementary outputs. The “H” voltage input to the signal DH and the signal DL is applied to the P-channel transistors P1 and P1 of the level conversion circuit.
It is lower than the voltage supplied to P2. The circuit constant of the P-channel transistor P1 and the N-channel transistor N1 is N
When the channel transistor N1 is turned on, the potential of the signal QL is lowered to a level sufficient to make the P-channel transistor P2 conductive.

Similarly, P-channel transistors P2 and N
The circuit constant of channel transistor N2 is such that when N-channel transistor N2 is turned on, the potential of signal QH drops to a level sufficient to turn on P-channel transistor P1.

When "H" is input to signal DH and "L" is input to signal DL, N-channel transistor N1 is turned on and N-channel transistor N2 is turned off. Therefore, the potential of signal QL decreases, P-channel transistor P2 is turned on, the potential of signal QH is raised, and P-channel transistor P1 is turned off. Therefore, the signal QH becomes “H” and the signal QL becomes “L”. The potential difference between the signal QH and the signal QL is equal to the potential difference between the source terminal of the P-channel transistor and the source terminal of the N-channel transistor of the level conversion circuit. Thus, the signals QH and QL having a potential difference different from the potential difference between the signals DH and DL are obtained.

FIG. 10 shows an example of a conventional output circuit in which the CMOS type tri-state driver circuit shown in FIG. 6 and the CMOS type level conversion circuit shown in FIG. 9 are combined. This circuit operates similarly to the output circuit of FIG. 7, except that the voltage amplitude of the drive control signal EN and the output data signal D and the voltage amplitude of the output signal Q are different. The power supplies of all the logic gates are internal power supplies lower than VDD.

FIG. 11 shows an input / output circuit using the output circuit of FIG. The operation is such that the drive control signal EN is set to “L” and the output signal Q of the input / output circuit is set to “Z” regardless of the level of the output data signal D. Q is “H” or “L”
To transmit the level change of the output signal Q to the input data signal N. Also, the power supply of all logic gates is VDD
It is.

FIG. 12 shows an input / output circuit using the output circuit of FIG. Drive control signal EN and output data signal D
7 operates in the same manner as the output circuit of FIG. 7 except that the voltage amplitude of the output signal Q is different from the voltage amplitude of the output signal Q. The power supplies of all the logic gates are internal power supplies lower than VDD.

FIG. 13 shows an example of a computer system constituted by using an integrated circuit having the input / output circuit of FIG. In FIG. 13, the CPU shares the memory, the system control LSI, and the bus A, and the system control LSI
When data transfer between the CPU and the memory is permitted by the control signal B from the CPU, the output circuit of the system control LSI outputs “Z” to the bus A, and the CPU uses the bus A to transmit data to and from the memory. Perform a transfer. On the other hand, when data transfer between the CPU and the memory is prohibited by the control signal B from the system control LSI, the output circuit of the CPU outputs “Z” to the bus A, and the system control LSI uses the bus A. To transfer data to and from the memory.

[0012]

When the computer system shown in FIG. 13 does not need to operate the CPU and only has to operate the system control LSI and the memory, the power consumption to the CPU can be stopped if it can be stopped. Power can be significantly reduced. However, since a conventional CMOS tristate driver circuit is used for the CPU, the power supply is stopped (referred to as power down) and the P-type CMOS tristate driver circuit is turned off.
When the potential of the source terminal, the back gate terminal, and the drain terminal of the channel transistor drops, the system control L
When the SI tries to output the "H" signal to the bus A to the memory, the PN junction between the drain terminal of the P-channel transistor and the back gate terminal of the P-channel transistor becomes forward as shown in FIG. Electric charges are supplied from the output terminal of the system control LSI to the power supply terminal of the CPU, and power consumption cannot be reduced.

FIG. 15 shows, for example, Japanese Patent Application Laid-Open No. 8-3072.
38 discloses a CMOS type tri-state driver circuit in which a circuit for applying a back gate potential to a P-channel transistor even when power is turned off is added to prevent a leak current from flowing. According to FIG. 15, the PN junction between the drain terminal and the back gate terminal of the P-channel transistor is not in the forward direction, but no charge is supplied to the gate terminal of the P-channel transistor in the power down mode, so that a channel is formed in the P-channel transistor. Therefore, leakage to the power supply terminal via the channel cannot be prevented. Further, there is a problem that the number of elements per output driver circuit increases.

Further, in the computer system shown in FIG. 13, when there is no need to operate the CPU and only the system control LSI and the memory need to operate,
The power consumption can also be significantly reduced by stopping only the power supply to the circuit inside the CPU. In this case, in order to transfer data between the system control LSI and the memory,
A voltage of "H" is applied to the gate terminal of the P-channel transistor and a voltage of "L" is applied to the gate terminal of the N-channel transistor of the CMOS tri-state driver circuit of FIG. 10, and the output of the CMOS tri-state driver is set to "Z". Although it is necessary, since the power supply to the CPU internal circuit to supply the complementary signal to the input pair terminal of the CMOS type level conversion circuit is stopped, the voltage of "H" cannot be supplied to the gate terminal of the P-channel transistor. However, leakage to the power supply terminal via the channel cannot be prevented.

FIG. 16 is a CMOS type tri-state driver circuit disclosed in Japanese Patent Application Laid-Open No. 9-64718, and FIG. 17 is a CMOS type tri-state driver circuit disclosed in US Pat. No. 4,963,766.
A circuit for applying a high voltage to the back gate voltage of a P-channel transistor to prevent leakage when a high voltage is applied to an output terminal, and increasing the gate voltage of the P-channel transistor in response to the application of the high voltage to the output terminal Is added. In a circuit in which a P-channel transistor is added between the output terminal and the gate terminal of the P-channel transistor of the main buffer, even when the power is down, the P-channel transistor of the main buffer is
Charge is supplied to the gate terminal of the channel transistor. However, a delay time occurs because the charge is supplied from the output terminal to the gate terminal of the P-channel transistor of the main buffer via the added P-channel transistor. When the voltage rises steeply, there is a problem that a leak current flows transiently.

[0016]

According to the integrated circuit device of the present invention, one source / drain terminal of a second conductivity type MOS transistor is connected to one source / drain terminal of a first conductivity type MOS transistor, and the other is connected to the other source / drain terminal. An integrated circuit device provided with a tri-state driver circuit including the first conductivity type MOS transistor in which a source / drain terminal and a back gate terminal are electrically separated from each other.
A first power supply terminal for applying a first constant potential;
A second power supply terminal for applying a constant potential, a third power supply terminal for applying a third constant potential, and a first conductivity type M.
The other source / drain terminal of the OS transistor is the second
And a back gate terminal of the first conductivity type MOS transistor is connected to a third power supply terminal,
A tri-state driver circuit having the other source / drain terminal of the conductive type MOS transistor connected to the first power supply terminal; and a potential difference detecting means connected to the second power supply terminal and the third power supply terminal for detecting a potential difference therebetween. And a first conductivity type MOS connected to the potential difference detecting means,
Gate potential control means for controlling the potential of the gate terminal of the transistor.

Also, one source / drain terminal of the second conductivity type MOS transistor is connected to one source / drain terminal of the first conductivity type MOS transistor, and the other source / drain terminal and the back gate terminal are electrically connected. In an integrated circuit device provided with a tri-state driver circuit including a separated first conductivity type MOS transistor, the other source / source of the first conductivity type MOS transistor is provided.
The drain terminal is connected to the second power supply terminal, the back gate terminal of the first conductivity type MOS transistor is connected to the third power supply terminal, and the other source / drain terminal and the back gate terminal of the second conductivity type MOS transistor are connected to each other. A tri-state driver circuit connected to the first power supply terminal;

A triode comprising a first conductivity type MOS transistor and a second conductivity type MOS transistor, one of which has a source / drain terminal connected to each other and the other of which has a source / drain terminal and a back gate terminal electrically connected to each other. In an integrated circuit device provided with a state driver circuit, a first power supply terminal for applying a first constant potential, a second power supply terminal for applying a second constant potential,
A third power supply terminal for applying a third constant potential;
And a potential difference detecting means for detecting the potential difference between the power supply terminal and the third power supply terminal. If the potential difference is detected between the second power supply terminal and the third power supply terminal by the potential difference detection means, The same potential as the potential of the third power supply terminal is applied to the gate terminal of the first conductivity type MOS transistor of the tristate driver circuit, and the first potential is applied to the gate terminal of the second conductivity type MOS transistor of the tristate driver circuit. And a CMOS level conversion circuit for applying the same potential as the potential of the power supply terminal.

Also, a triode comprising a first conductivity type MOS transistor and a second conductivity type MOS transistor having one source / drain terminal connected to each other and the other source / drain terminal and back gate terminal electrically connected to each other. In an integrated circuit device provided with a state driver circuit, a first power supply terminal for applying a first constant potential, a second power supply terminal for applying a second constant potential,
Switch means for electrically connecting or disconnecting between the second power supply terminal and one of the source / drain terminals of the first conductivity type MOS transistor; and a gate for controlling the potential of the gate terminal of the first conductivity type MOS transistor A power supply control means for controlling the switch means and the gate potential control means, the power supply control means being divided into a first block including a tristate driver circuit and a second block including a power supply control means; When the back gate terminal of the one conductivity type MOS transistor is connected to the second power supply terminal and the first block is powered down by the power supply control means,
The switch means electrically cuts off between the second power supply terminal and one of the source / drain terminals of the first conductivity type MOS transistor, and the gate potential control means changes the potential of the gate terminal of the second conductivity type MOS transistor to the second. And a potential difference equal to that of the power supply terminal.

In an integrated circuit device provided with a CMOS type level conversion circuit, the CMOS type level conversion circuit includes:
A first power supply terminal for applying a first constant potential;
A first power supply type MOS transistor and a second first power supply type MOS transistor, one of which has a source / drain terminal and a back gate terminal connected to the second power supply terminal. A conductive type MOS transistor, a third first conductive type MOS transistor, a second second conductive type MOS transistor having one source / drain terminal and a back gate terminal connected to a first power supply terminal, and a third second type MOS transistor; Two-conductivity-type MOS transistor and fourth second-conductivity-type MO
The S transistor and one source / drain terminal are connected to the first
Are connected to the other source / drain terminals of the first conductivity type MOS transistor and the second first conductivity type MOS transistor, and the other source / drain terminal is the other source / drain of the second second conductivity type MOS transistor. A first second-conductivity-type MOS transistor connected to the first power-supply terminal and a back-gate terminal connected to the first power-supply terminal;
Conductive MOS transistor and fourth second conductive MOS
The third first conductivity type MOS transistor is connected to the other source / drain terminal of the transistor, and the gate terminal of the third first conductivity type MOS transistor is connected to the first first conductivity type MOS transistor and the second first conductivity type MOS transistor.
The other source / drain terminal of the third conductivity type MOS transistor is connected to the other source / drain terminal of the third conductivity type MOS transistor.
Connected to the other source / drain terminal of the transistor and the fourth second conductivity type MOS transistor,
A first data input terminal to which the gate terminal of the conductive type MOS transistor is connected, and a second data input to which the gate terminals of the first first conductive type MOS transistor and the first second conductive type MOS transistor are connected Terminal, a first mode control input terminal to which a gate terminal of the second second conductivity type MOS transistor is connected, and a fourth second conductivity type MOS transistor.
A second mode control input terminal to which a gate terminal of the transistor is connected.

Further, in the integrated circuit device provided with the CMOS type level conversion circuit, the other source / drain terminal of the first first conductivity type MOS transistor and the second first conductivity type MOS transistor and the first second conductivity type MOS transistor. An output terminal connected to one of the source / drain terminals of the type MOS transistor is provided.

Further, in the integrated circuit device having the CMOS type level conversion circuit, the other source / drain terminal of the third first conductivity type MOS transistor, the third second conductivity type MOS transistor, and the fourth second conductivity type MOS transistor are provided. An output terminal connected to the other source / drain terminal of the type MOS transistor is provided.

Also, a triode comprising a first conductivity type MOS transistor and a second conductivity type MOS transistor, one of which has a source / drain terminal connected to each other and the other of which has a source / drain terminal and a back gate terminal electrically connected to each other. In an integrated circuit device provided with a state driver circuit, a first conductivity type MOS of a tristate driver circuit is provided.
The CMOS level conversion circuit according to claim 5 is electrically connected to each gate terminal of the transistor and the second conductivity type MOS transistor.

Further, a first conductivity type MOS in which one source / drain terminal is connected to each other and the other source / drain terminal and the back gate terminal are electrically connected.
In an integrated circuit device provided with a tristate driver circuit including a transistor and a second conductivity type MOS transistor, the first conductivity type MO of the tristate driver circuit is provided.
7. The CMOS according to claim 6, wherein a gate terminal of the S transistor is provided.
An output terminal of the type level conversion circuit is connected, and an output terminal of the CMOS type level conversion circuit is connected to a gate terminal of the second conductivity type MOS transistor of the tristate driver circuit.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an integrated circuit device according to the first embodiment. In FIG.
On the chip 1, a CPU 2, a bus control circuit 3, a memory 4, a power switch circuit 5, and a pad 6 are arranged. The CPU 2, the bus control circuit 3, and the memory 4 are connected to an internal data bus 7 for mutually transferring data. The address signal 8, the read / write signal 9, and the access request signal 10 output from the CPU 2 are connected to the bus control circuit 3, and the bus control circuit 3
Has an access completion signal 11, a bus permission signal 12 and C
The PU reset signal 13 has been output. An address signal 14, a read strobe signal 15, and a write strobe signal 16 are output from the bus control circuit 3 to the memory 4.

A power control cutoff signal 17 is output from the bus control circuit 3 to the power switch circuit 5. A power supply 18 that is cut off at the time of power down is output from the power switch circuit 5 to the CPU 2.

The pad 6, the CPU 2, the bus control circuit 3, the memory 4 and the power switch circuit 5 have a power supply 1
9 and a ground power supply 20 are supplied from outside the chip 1. The power supplies 18 and 19 are supplied with a positive voltage to the ground power supply 20 and have the same voltage during normal operation.

The bus control circuit 3 outputs an external address bus 21, an external read strobe signal 22 and an external write strobe signal 23 to the pad 6. A power down request signal 24 and an external data signal 25 are output from the pad 6 to the bus control circuit 3. Hereinafter, the operation of each block in the normal operation mode and the return operation from the power down mode will be described.

FIG. 2 shows a CMOS type input / output terminal circuit used for connection with the internal data bus 7 of the CPU 2. CPU2
Are also supplied with power 18 and power 19. Referring to FIG. 2, NAND circuit N to which power supplies 18 and 19 are connected
D2 and its output are input via an inverter circuit IV2, and an output enable signal 40 and an output data signal 41
Circuits ND1 and ND1 to each other.
1 is connected to the gate, one of the source / drain terminals is connected to the power supply 18, the back gate terminal is connected to the P-channel transistor 26 connected to the power supply 19, and the output of the NAND circuit ND2 is input. NOR circuit NR1 to which NOR circuit N1 is input via inverter circuit IV1 and output data signal 41;
R1 is connected to the gate, one source / drain terminal is connected to the other source / drain terminal of the P-channel transistor 26, and the back gate terminal and the other source / drain terminal are connected to the ground power supply 20. Output data of the CMOS type tri-state driver circuit including the channel transistor 27 and the P-channel transistor 26 and the N-channel transistor 27 is output to the internal data bus 7 or becomes input data via the inverter circuit IV3. ND1, ND2, NR1, IV
Power supply 19 is supplied to 1 and IV2, and 18 is supplied to other circuits inside CPU 2. Also, CP
A ground power supply 20 is supplied to all circuits of U2.

First, the normal operation mode will be described.
The operation is performed by the CPU 2 of FIG.
Starts data processing. At this time, the bus control circuit 3
Outputs "occupation permission" (for example, a voltage of "H") to the bus permission signal 12. When the occupancy is permitted, the CPU 2 has the occupation right of the internal data bus 7, and when the occupation is prohibited, the bus control circuit 3 has the occupation right of the internal data bus 7. . CPU 2 has address 8
At the same time, a "read" (for example, "H" voltage) is output to the read / write signal 9, and a "request" (for example, "H" voltage) is output to the access request signal 10. .

When "request" is output to the access request signal 10, the bus control circuit 3 detects that an access request from the CPU 2 has occurred. The bus control circuit 3 decodes the address 8 and determines whether the address to be accessed indicates the memory 4 inside the chip. If the address 8 indicates the memory 4 as a result of the decoding, the bus control circuit 3 outputs the address 8 to the address 14 and outputs a “read request” (for example, a voltage of “H”) to the read strobe signal 15. Here, for the sake of simplicity, only the operation when the address 8 indicates the memory 4 will be described.
May indicate a memory connected to the outside or a register in the bus control circuit 3.

The memory 4 detects that a “read request” has been output to the read strobe signal 15 and outputs data corresponding to the address 14 to the internal data bus 7.
The bus control circuit 3 outputs “complete” (for example, “H” voltage) to the access completion signal 11 at the time when the data from the memory 4 is output to the internal data bus 7, and outputs “read non-request” to the read strobe signal 15. (Eg, "L" voltage)
Is output. The CPU 2 detects that the “read request” has been output to the access completion signal 11, takes in the program from the internal data bus 7, and starts processing. CPU
2 sequentially fetches and executes programs as described above. When reading the data from the memory 4 is specified by the program, the data is fetched from the internal data bus 7 in the same manner as the program.

When write is designated, the CPU 2 outputs a data address to the address 8 and outputs data to be written to the internal data bus 7 using the CMOS type input / output terminal circuit of FIG. A “write” (eg, “L” voltage) is output as the signal 9, and a “request” (eg, “H” voltage) is output as the access request signal 10.

When "request" is output to the access request signal 10, the bus control circuit 3 detects that an access request from the CPU 2 has occurred. The bus control circuit 3 decodes the address 8 and determines whether the address to be accessed indicates the memory 4 inside the chip. When the address 8 indicates the memory 4 as a result of the decoding, the bus control circuit 3 outputs the address 8 to the address 14 and outputs a “write request” (for example, a voltage of “H”) to the write strobe signal 16. The memory 4 detects that the “write request” is output to the write strobe signal 16 and writes the data input from the internal data bus 7 to the memory element corresponding to the address 14.
The bus control circuit 3 sets the access completion signal 11 to “completed” at the time when the data writing to the memory element of the memory 4 is completed.
(For example, a voltage of “H”), and outputs “write non-request” (for example, a voltage of “L”) to the write strobe signal 16. The CPU 2 detects that the next data transfer using the internal data bus 7 has been enabled by outputting “completion” to the access completion signal 11.

Next, the operation when the bus control circuit 3 has the right to occupy the bus will be described. While the bus control circuit 3 outputs “occupancy permission” to the bus permission signal 12, the CPU 2
Has the right to occupy the internal data bus 7, and the bus control circuit 3 does not voluntarily use the internal data bus 7 to transfer data.

The bus control circuit 3 controls the internal data bus 7
In order to obtain the occupation right, "occupation prohibited" (for example, a voltage of "L") is output to the bus permission signal 12. When "occupation prohibition" is output to the bus permission signal 12, the CPU 2 sets the output to "Z" by setting the output enable signal 40 to "L" to release the internal data bus 7, and the CPU 2
2, the internal data bus 7 can be driven and the access request signal 1
0 is not allowed to be occupied. These operations enable the bus control circuit 3 to perform data transfer using the internal data bus 7.

The bus control circuit 3 controls the internal data bus 7
When the read is performed from the memory 4 by using the data, the bus control circuit 3 outputs the address 14 to the memory 4 and sets the read strobe signal 15 to “read request” (for example, “H”).
Output). The memory 4 detects that the “read request” has been output to the read strobe signal 15 and outputs data stored in the memory element corresponding to the address 14 to the internal data bus 7. The bus control circuit 3 takes in data from the internal data bus 7, writes the data in a register in the bus control circuit 3, and outputs “read non-request” (for example, “L” voltage) to the read strobe signal 15.

When writing to the memory 4, the bus control circuit 3 outputs the address 14 to the memory 4 and outputs the data of the register in the bus control circuit 3, and at the same time, writes “write request” (for example, (“H” voltage). The memory 4 has a write strobe signal 16
, The data input from the internal data bus 7 is written to the memory element corresponding to the address 14. The bus control circuit 3 permits the access completion signal 11 to be interrupted at the time when the data writing to the memory element of the memory 4 is completed, and sets the write strobe signal 16 to “write non-request” (eg, “L” voltage)
Is output.

Next, the power down mode will be described. The transition to the power down mode is started by outputting a “power down request” (for example, a voltage of “H”) as a power down request signal 24 from the pad 6 to the bus control circuit 3. The bus control circuit 3 outputs the power down request signal 2
4 detects that a “power down request” has been output,
It outputs “interruption” (for example, a voltage of “H”) as the power interruption control signal 17 to the power switch circuit 5. The power switch circuit 5 cuts off the power supply 18 by outputting “cut” to the power cutoff control signal 17. When the power supply 18 is cut off, the input / output terminal circuit of the CPU 2 operates as follows.

When the power supply 18 is cut off, the NAND circuit N
D2 outputs “H” (the voltage of the power supply 19) to the power down control line 30. The inverter circuit IV2 that generates an inverted signal of this signal outputs the inverted signal of the power down control line 30 to the power down control line 31. The power down control lines 30 and 31 are connected to the NAND circuit ND1 and the NOR circuit NR1.
When the power down control lines 30 and 31 change as described above, the NAND circuit ND1 turns the output 32 of the NAND circuit ND1 to "H" regardless of the voltage of the output enable signal 40 and the output data signal 41. , N
The output 33 of the OR circuit NR1 becomes "L".

The P-channel transistor 26 is turned off when the gate terminal and the back gate terminal are kept at "H" (voltage of the power supply 19). Similarly N
The channel transistor 27 is turned off when the source terminal, the back gate terminal, and the gate terminal are kept at “L” (ground voltage). That is, the output of the input / output terminal circuit is maintained at “Z” in the power down mode, and the internal data bus 7 is set to “H” by the memory 4 or the bus control circuit 3
Regardless of which of the voltage levels "L" is driven, the current can be prevented from being supplied to the power supply 18 through the P-channel transistor 26.

The CPU 2 operates according to the operation of the input / output terminal circuit.
"Z" is applied to the internal data bus 7 regardless of the internal state of the CPU 2.
Is output. The power supply 18 to the circuits other than the input / output terminal circuit inside the CPU 2 is shut off, and the power consumption inside the CPU is suppressed to only a small leak current in the input / output terminal circuit. The bus control circuit 3 controls the memory 4 as in the normal operation mode.
Performs a read / write operation.

Next, the return operation from the power down mode will be described. The return from the power down mode is performed by the power down request signal 2 from the pad 6 to the bus control circuit 3.
In FIG. 4, “power-down not required” (for example, “L” voltage) is started by output. The bus control circuit 3 detects that “power-down not required” is output as the power-down request signal 24, and outputs “non-interrupt” (for example, “L” voltage) to the power-off control signal 17 to the power switch circuit 5. Is output.
The power switch circuit 5 supplies the power 18 by outputting “non-block” to the power cut control signal 17. Since the state in the CPU 2 is not held in the power down mode, the bus control circuit 3 outputs the CPU reset signal 13 to the CPU 2 and outputs “occupation permission” to the bus permission signal 12. The CPU 2 returns from the power down mode to the normal operation mode by the supply of the CPU reset signal 13 and the power supply 18, and starts data processing.
Further, a NOR circuit NR1, inverter circuits IV1, IV
The power supply of 3 is 18 and the power supply of NAND circuit ND2 and inverter circuit IV2 is 19.

As described above, by providing the CMOS type tristate driver circuit according to the present invention in the integrated circuit device to be powered down, the output of the CMOS type tristate driver circuit to the bus in the power down mode is set to "Z". I do. That is, it can be electrically opened. For this reason, a circuit element that is not powered down can perform data transfer using the bus without extra power consumption, and low power consumption can be achieved.

Embodiment 2 FIG. 3 is a block diagram of an integrated circuit device according to the second embodiment. The basic operation of this integrated circuit device is the same as that of FIG. 1, except that the operating voltage of the internal circuit of the CPU 2a is lower than other voltages. Referring to FIG. 3, reference numeral 1a denotes a chip. CP on chip 1a
U2a, a bus control circuit 3a, a memory 4a, a power switch circuit 5a, and a pad 6a are arranged. CP
The U2a, the bus control circuit 3a, and the memory 4a are connected to an internal data bus 7a for mutually transferring data. Address signal 8a output from CPU 2a
Read / write signal 9a and access request signal 10a
Is connected to the bus control circuit 3a.
The access completion signal 11a, the bus permission signal 12a, and the CPU reset signal 13a are output to the CPU 2a from a. An address signal 14a, a read strobe signal 15a, and a write strobe signal 16a are output from the bus control circuit 3a to the memory 4a.

The power control cutoff signal 17a is output from the bus control circuit 3a to the power switch circuit 5a. A power supply 18a which is cut off at the time of power down is output from the power switch circuit 5a to the CPU 2a.

The CPU 6a from the pad 6a, the bus control circuit 3a, the memory 4a and the power switch circuit 5a
Power supply 50a, 19a and ground power supply 20a
a. The power supplies 50a and 19a are supplied with a positive voltage with respect to the ground power supply 20a.
The voltage between the power supply 19a and the ground power supply 20a is lower than the voltage between the power supply 19a and the ground power supply 20a.

Further, the bus control circuit 3a outputs an external address bus 21a, an external read strobe signal 22a and an external write strobe signal 23a to the pad 6a. A power down request signal 24a and an external data signal 25a are output from the pad 6a to the bus control circuit 3a.

FIG. 4 shows a potential difference detecting circuit for detecting the cutoff of the power supply. Referring to FIG. 4, by setting the resistance 52 to an appropriate value, the power-down control line 30 is set to “L” during the normal operation mode (the power supply 18a is supplied).
"H" is output to the power-down mode (power supply 18).
When “a” is shut off), “H” can be output to the power-down control line 30 and “L” can be output to the power-down control line 31, so that the shut-down of the power supply 18a can be detected.

FIG. 5 shows an input / output terminal circuit including a CMOS type level conversion circuit of the CPU 2a. Referring to FIG. 5, CMOS type level conversion circuit 70 includes an N-channel transistor 83 in which power down control line 30 is connected to a gate terminal and a back gate terminal is connected to ground power supply line 85.
An N-channel transistor 81 and a P-channel transistor 71 having a back gate terminal connected to the ground power supply line 85 and a power down control line 31 connected to the gate terminal; a NAND circuit 65 to which an enable signal and a data signal are input; The output is input to the gate terminal, the back gate terminal is connected to the ground power supply line 85, and one source / drain terminal is connected to one source / drain terminal of the N-channel transistor 83.
4 and the NAND inverted by the inverter circuit 66
The output of the circuit 65 is input to the gate terminal, and one of the source / drain terminal and the back gate terminal is connected to the ground power line 85.
, An N-channel transistor 82 having the other source / drain terminal connected to the other source / drain terminal of the N-channel transistor 81, a back gate terminal, and one source / drain terminal connected to the power supply line 86. , A P-channel transistor 72 having the other source / drain terminal connected to P-channel transistor 71
And a P-channel transistor 73 having one source / drain terminal and back gate terminal connected to the power supply line 86 and the other source / drain terminal connected to the N-channel transistor 84.

The CMOS type level conversion circuit 80 is also
It has a transistor configuration similar to that of 0. However, a NOR circuit 68 to which a data signal and an enable signal inverted via an inverter circuit 67 are input, an N-channel transistor 82 whose output is input to a gate terminal,
NOR circuit 68 inverted via inverter circuit 69
And an N-channel transistor 84 whose output is input to the gate terminal. Further, a CMOS type comprising a P-channel transistor 61 to which the output QH of the CMOS type level conversion circuit 70 is input to the gate terminal and an N-channel transistor 62 to which the output QL of the CMOS type level conversion circuit 80 is input to the gate terminal. A tristate driver circuit 60 is provided. Note that the NAND circuit 65, N
The power supplied to the OR circuit 68 and the inverter circuits 66, 67, 69 is cut off at the time of power down.

Next, the normal operation mode will be described.
When “L” is applied to the power down control line 30 and “H” is applied to the power down control line 31 and the enable signal is “H” and the data signal is “L”, the CMOS level conversion circuit 7
The 0-channel N-channel transistors 81 and 84 are ON, and the P-channel transistor 71 and N-channel transistor 82 are OFF. Since the N-channel transistor 84 is turned on, the P-channel transistor 72 is also turned on, and the power supply potential of the power supply line 86 is applied to the gate terminal of the P-channel transistor 61. At that time, the P-channel transistor 61 is turned off.

The N of the CMOS level conversion circuit 80
The channel transistors 81 and 82 are turned on, and the P-channel transistor 71 and the N-channel transistors 83 and 84 are turned off. N-channel transistors 81 and 82 are O
Since N is applied, the P-channel transistor 73 is also turned on, and the power supply potential of the power supply line
2 is applied to the gate terminal. At that time, the N-channel transistor 62 is turned on, and the CMOS tristate driver circuit 60 outputs the potential of the ground power supply line 85.

Next, when the enable signal is "L" and the data signal is "H" while the levels of the power down control lines 30 and 31 remain unchanged, the N-channel transistors 81 and 84 of the CMOS type level conversion circuit 70 are turned on. The P-channel transistor 71 and the N-channel transistor 82 are turned off. Since the N-channel transistor 84 is turned on,
The channel transistor 72 is also turned on, and the power line 86
Is applied to the gate terminal of the P-channel transistor 61. At that time, the P-channel transistor 61 is turned off.

The N of the CMOS type level conversion circuit 80
The channel transistors 81 and 84 are turned on, and the P-channel transistor 71 and the N-channel transistors 82 and 83 are turned off. Since the N-channel transistor 84 is turned on, the P-channel transistor 72 is also turned on, the power supply potential of the power supply line 86 is applied to the gate terminal of the P-channel transistor 73, and the P-channel transistor 73
When the N-channel transistor 84 is turned on, an “L” signal is applied to the gate terminal of the N-channel transistor 62. At that time, the N-channel transistor 62
Is turned off, and the CMOS tristate driver circuit 60 becomes "Z".

Next, when the enable signal is "H" and the data signal is "H" while the levels of the power-down control lines 30 and 31 remain unchanged, the N-channel transistors 81 and 82 of the CMOS type level conversion circuit 70 are turned on. P channel transistor 71 and N channel transistors 83 and 84 are O
It becomes FF. N-channel transistors 81 and 82 are ON
Therefore, “L” is applied to the gate terminal of the P-channel transistor 61. At that time, the P-channel transistor 61 turns ON.

The N of the CMOS type level conversion circuit 80
The channel transistors 81 and 84 are turned on, and the P-channel transistor 71 and the N-channel transistors 82 and 83 are turned off. Since the N-channel transistor 84 is turned on, the P-channel transistor 72 is also turned on, the power supply potential of the power supply line 86 is applied to the gate terminal of the P-channel transistor 73, and the P-channel transistor 73
When the N-channel transistor 84 is turned on, an “L” signal is applied to the gate terminal of the N-channel transistor 62. At that time, the N-channel transistor 62
Is turned off, and the CMOS tristate driver circuit 60 outputs the power supply potential of the power supply line 86.

Further, when the enable signal is at "L" and the data signal is at "L" while the level of the power down control lines 30 and 31 remains unchanged, N of the CMOS type level conversion circuit 70 is
Channel transistors 81 and 84 are ON, P-channel transistor 71 and N-channel transistor 82 are OFF
Becomes Since the N-channel transistor 84 is turned on, the P-channel transistor 72 is also turned on and the power line 8
6 is applied to the gate terminal of the P-channel transistor 61. At that time, the P-channel transistor 61
Becomes OFF.

The N of the CMOS type level conversion circuit 80
The channel transistors 81 and 84 are turned on, and the P-channel transistor 71 and the N-channel transistors 82 and 83 are turned off. Since the N-channel transistor 4 is turned on, the P-channel transistor 72 is also turned on, but the P-channel transistor 73 is turned off, so that an “L” signal is applied to the gate terminal of the N-channel transistor 62. At that time, the N-channel transistor 62 is turned off, and the CMOS type tri-state driver circuit 60 becomes "Z".

Next, the power down mode will be described. At the time of power down, “H” is applied to the power down control line 30 and “L” is applied to the power down control line 31. In addition, power supply to the NAND circuit 65, the NOR circuit 68, and the inverter circuits 66, 67, and 69 is cut off,
The output potential is undefined. In the CMOS type level conversion circuit 70, the P-channel transistor 71 and the N-channel transistor 83 are ON, and the N-channel transistor 81 is O
To perform FF, the N-channel transistors 82 and 84
The power supply potential of the power supply line 86 is applied to the gate terminal of the P-channel transistor 61 regardless of N / OFF. At that time, the P-channel transistor 61 is turned off. Also,
As for the CMOS type level conversion circuit 80, the P-channel transistors 71 and N of the CMOS type level conversion circuit 70
Since the channel transistor 83 is turned on and the N-channel transistor 81 is turned off, the N-channel transistor 8
Regardless of the ON / OFF state of the transistors 2 and 84, the gate terminal of the N-channel transistor 62 is supplied with ground power,
The channel transistor 62 is turned off. Since both the P-channel transistor 61 and the N-channel transistor 62 are turned off, the output of the CMOS tristate driver circuit 60 becomes “Z”.

As described above, by providing a CMOS type level conversion circuit in an integrated circuit device to be powered down,
In the power down mode, the output of the CMOS type tristate driver circuit to the bus is set to “Z” to be electrically open. For this reason, the circuit elements that are not powered down can perform data transfer using the bus without extra power consumption, and low power consumption can be achieved.

[0062]

According to the integrated circuit device of the present invention, one source / drain terminal of the second conductive type MOS transistor is connected to one source / drain terminal of the first conductive type MOS transistor, and the other source / drain terminal is connected to the other source / drain terminal. A first power supply terminal for applying a first constant potential in an integrated circuit device provided with a tri-state driver circuit including the first conductivity type MOS transistor in which a terminal and a back gate terminal are electrically separated; A second power supply terminal for applying a second constant potential, a third power supply terminal for applying a third constant potential, and the other source / drain terminal of the first conductivity type MOS transistor are connected to the second power supply terminal. And the back gate terminal of the first conductivity type MOS transistor is connected to the third power source terminal, and the other of the second conductivity type MOS transistor A tristate driver circuit source / drain terminal connected to a first power supply terminal, a second
Potential difference detecting means connected to the power supply terminal and the third power supply terminal for detecting the potential difference, and gate potential control connected to the potential difference detection means and controlling the potential of the gate terminal of the first conductivity type MOS transistor by the output thereof With this configuration, it is possible to obtain an integrated circuit device that can effectively cut off power supply in the power down mode.

Further, one source / drain terminal of the second conductivity type MOS transistor is connected to one source / drain terminal of the first conductivity type MOS transistor, and the other source / drain terminal and the back gate terminal are electrically connected. In an integrated circuit device provided with a tri-state driver circuit including a separated first conductivity type MOS transistor, the other source / source of the first conductivity type MOS transistor is provided.
The drain terminal is connected to the second power supply terminal, the back gate terminal of the first conductivity type MOS transistor is connected to the third power supply terminal, and the other source / drain terminal and the back gate terminal of the second conductivity type MOS transistor are connected to each other. With the provision of the tri-state driver circuit connected to the first power supply terminal, it is possible to further obtain an integrated circuit device capable of effectively shutting off power supply in the power down mode.

Further, a triode composed of a first conductivity type MOS transistor and a second conductivity type MOS transistor having one source / drain terminal connected to each other and the other source / drain terminal and back gate terminal electrically connected to each other. In an integrated circuit device provided with a state driver circuit, a first power supply terminal for applying a first constant potential, a second power supply terminal for applying a second constant potential,
A third power supply terminal for applying a third constant potential;
And a potential difference detecting means for detecting the potential difference between the power supply terminal and the third power supply terminal. If the potential difference is detected between the second power supply terminal and the third power supply terminal by the potential difference detection means, The same potential as the potential of the third power supply terminal is applied to the gate terminal of the first conductivity type MOS transistor of the tristate driver circuit, and the first potential is applied to the gate terminal of the second conductivity type MOS transistor of the tristate driver circuit. An integrated circuit device that includes a CMOS type level conversion circuit that applies the same potential as the potential of a power supply terminal, can effectively cut off power supply in a power down mode, and can reduce power consumption in an internal circuit during normal operation. It is possible to obtain.

Further, a triode composed of a first conductivity type MOS transistor and a second conductivity type MOS transistor having one source / drain terminal connected to each other and the other source / drain terminal and back gate terminal electrically connected to each other. In an integrated circuit device provided with a state driver circuit, a first power supply terminal for applying a first constant potential, a second power supply terminal for applying a second constant potential,
Switch means for electrically connecting or disconnecting between the second power supply terminal and one of the source / drain terminals of the first conductivity type MOS transistor; and a gate for controlling the potential of the gate terminal of the first conductivity type MOS transistor A power supply control means for controlling the switch means and the gate potential control means, the power supply control means being divided into a first block including a tristate driver circuit and a second block including a power supply control means; When the back gate terminal of the one conductivity type MOS transistor is connected to the second power supply terminal and the first block is powered down by the power supply control means,
The switch means electrically cuts off between the second power supply terminal and one of the source / drain terminals of the first conductivity type MOS transistor, and the gate potential control means changes the potential of the gate terminal of the second conductivity type MOS transistor to the second. By setting the potential difference equal to that of the power supply terminal, it is possible to obtain an integrated circuit device capable of effectively shutting off power supply in the power down mode and reducing power consumption in an internal circuit during normal operation.

In an integrated circuit device provided with a CMOS type level conversion circuit, the CMOS type level conversion circuit
A first power supply terminal for applying a first constant potential;
A first power supply type MOS transistor and a second first power supply type MOS transistor, one of which has a source / drain terminal and a back gate terminal connected to the second power supply terminal. A conductive type MOS transistor, a third first conductive type MOS transistor, a second second conductive type MOS transistor having one source / drain terminal and a back gate terminal connected to a first power supply terminal, and a third second type MOS transistor; Two-conductivity-type MOS transistor and fourth second-conductivity-type MO
The S transistor and one source / drain terminal are connected to the first
Are connected to the other source / drain terminals of the first conductivity type MOS transistor and the second first conductivity type MOS transistor, and the other source / drain terminal is the other source / drain of the second second conductivity type MOS transistor. A first second-conductivity-type MOS transistor connected to the first power-supply terminal and a back-gate terminal connected to the first power-supply terminal;
Conductive MOS transistor and fourth second conductive MOS
The third first conductivity type MOS transistor is connected to the other source / drain terminal of the transistor, and the gate terminal of the third first conductivity type MOS transistor is connected to the first first conductivity type MOS transistor and the second first conductivity type MOS transistor.
The other source / drain terminal of the third conductivity type MOS transistor is connected to the other source / drain terminal of the third conductivity type MOS transistor.
Connected to the other source / drain terminal of the transistor and the fourth second conductivity type MOS transistor,
A first data input terminal to which the gate terminal of the conductive type MOS transistor is connected, and a second data input to which the gate terminals of the first first conductive type MOS transistor and the first second conductive type MOS transistor are connected Terminal, a first mode control input terminal to which a gate terminal of the second second conductivity type MOS transistor is connected, and a fourth second conductivity type MOS transistor.
A second mode control input terminal to which a gate terminal of the transistor is connected; furthermore, power supply can be effectively cut off in a power down mode, and power consumption in an internal circuit can be reduced during normal operation. A circuit device can be obtained.

Further, in an integrated circuit device having a CMOS type level conversion circuit, the other source / drain terminal of the first first conductivity type MOS transistor and the second first conductivity type MOS transistor and the first second conductivity type MOS transistor. The CMOS type level conversion circuit according to claim 5, further comprising an output terminal connected to one of the source / drain terminals of the MOS transistor. It is possible to obtain an integrated circuit device that can reduce power consumption in an internal circuit during operation.

In the integrated circuit device having the CMOS type level conversion circuit, the other source / drain terminal of the third first conductivity type MOS transistor, the third second conductivity type MOS transistor, and the fourth second conductivity type MOS transistor are provided. The CMOS type level conversion circuit according to claim 5, further comprising an output terminal connected to the other source / drain terminal of the type MOS transistor. It is possible to obtain an integrated circuit device that can reduce power consumption in an internal circuit during operation.

Further, a triode composed of a first conductivity type MOS transistor and a second conductivity type MOS transistor having one source / drain terminal connected to each other and the other source / drain terminal and back gate terminal electrically connected to each other. In an integrated circuit device provided with a state driver circuit, a first conductivity type MOS of a tristate driver circuit is provided.
Since the CMOS type level conversion circuit according to claim 5 is electrically connected to each gate terminal of the transistor and the second conductivity type MOS transistor, the power supply can be effectively cut off in the power down mode, and An integrated circuit device that can reduce power consumption in an internal circuit during normal operation can be obtained.

Further, a first conductivity type MOS in which one source / drain terminal is connected to each other and the other source / drain terminal and back gate terminal are electrically connected.
In an integrated circuit device provided with a tristate driver circuit including a transistor and a second conductivity type MOS transistor, the first conductivity type MO of the tristate driver circuit is provided.
7. The CMOS according to claim 6, wherein a gate terminal of the S transistor is provided.
The output terminal of the CMOS level conversion circuit is connected to the output terminal of the CMOS type level conversion circuit, and the output terminal of the CMOS type level conversion circuit according to claim 7 is further connected to the gate terminal of the second conductivity type MOS transistor of the tristate driver circuit. It is possible to obtain an integrated circuit device that can effectively shut off power supply in the mode and reduce power consumption in an internal circuit during normal operation.

[Brief description of the drawings]

FIG. 1 is a block diagram of an integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a CMOS type input / output terminal according to the first embodiment of the present invention;

FIG. 3 is a block diagram of an integrated circuit device according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a potential difference detection circuit according to a second embodiment of the present invention.

FIG. 5 is an input / output terminal circuit diagram according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a conventional CMOS tristate driver.

FIG. 7 is a conventional output circuit diagram.

FIG. 8 is a truth table corresponding to a conventional output circuit.

FIG. 9 is a diagram of a conventional CMOS type level conversion circuit.

FIG. 10 is a conventional output circuit diagram.

FIG. 11 is an input / output circuit diagram using a conventional output circuit.

FIG. 12 is an input / output circuit diagram using another conventional output circuit.

FIG. 13 is a diagram of a conventional computer system.

FIG. 14 is an explanatory diagram of a conventional current inflow path at the time of power down.

FIG. 15 is a circuit diagram of a conventional CMOS tristate driver disclosed in Japanese Patent Application Laid-Open No. 8-307238.

FIG. 16 is a circuit diagram of a conventional CMOS tristate driver disclosed in Japanese Patent Application Laid-Open No. 9-64718.

FIG. 17 is a circuit diagram of a conventional CMOS tristate driver disclosed in US Pat. No. 4,963,766.

[Explanation of symbols]

Reference Signs List 18 power supply 19 power supply 20 ground power supply 18a power supply 19a power supply 20a ground power supply 26 P-channel transistor 27 N-channel transistor 32 output 33 output 40 output enable signal 41 output data signal 60 CMOS tristate driver circuit 61 P-channel transistor 62 N-channel transistor 70 CMOS type level conversion circuit 73 P-channel transistor 72 P-channel transistor 80 CMOS type level conversion circuit 81 N-channel transistor 83 N-channel transistor ND1 NAND circuit ND2 NAND
Circuit NR1 NOR circuit NR2 NOR circuit QH output QL output

Continued on the front page F term (reference) 5J055 AX06 AX52 AX64 BX16 CX24 DX22 DX56 DX72 DX83 EX07 EX21 EY21 EZ07 EZ25 EZ29 EZ39 FX12 FX17 FX35 5J056 AA00 AA05 AA11 BB49 CC00 DD13 DD28 EE04 FF07 FF08 GG12

Claims (9)

[Claims] 1. A source / drain terminal of a second conductivity type MOS transistor is connected to one source / drain terminal of a first conductivity type MOS transistor, and the other source / drain terminal and a back gate terminal are electrically connected. In an integrated circuit device provided with a tri-state driver circuit including the separated first conductivity type MOS transistor, a first power supply terminal for applying a first constant potential and a second power supply terminal for applying a second constant potential A second power supply terminal, a third power supply terminal for applying a third constant potential, and the other source / drain terminal of the first conductivity type MOS transistor are connected to the second power supply terminal; The first
A back gate terminal of the conductive type MOS transistor is connected to the third power supply terminal, and the other source / drain terminal of the second conductive type MOS transistor is connected to the first power supply terminal; A potential difference detecting means connected to the second power supply terminal and the third power supply terminal and detecting a potential difference between the second power supply terminal and the third power supply terminal; an output of the potential difference detecting means connected to the gate terminal of the first conductivity type MOS transistor; An integrated circuit device comprising: a gate potential control means for controlling a potential. 2. A source / drain terminal of a second conductivity type MOS transistor is connected to one source / drain terminal of a first conductivity type MOS transistor, and the other source / drain terminal and a back gate terminal are electrically connected. An integrated circuit device provided with a tri-state driver circuit including the separated first conductivity type MOS transistor, wherein the other source / drain terminal of the first conductivity type MOS transistor is connected to a second power supply terminal; A back gate terminal of the one conductivity type MOS transistor is connected to a third power supply terminal, and the other source / drain terminal and a back gate terminal of the second conductivity type MOS transistor are connected to a first power supply terminal; The integrated circuit device according to claim 1, further comprising a driver circuit. 3. A triode comprising a first conductivity type MOS transistor and a second conductivity type MOS transistor having one source / drain terminal connected to each other and the other source / drain terminal and back gate terminal electrically connected to each other. In an integrated circuit device provided with a state driver circuit, a first power supply terminal for applying a first constant potential, a second power supply terminal for applying a second constant potential, and a third constant potential are provided. A third power supply terminal for applying, a potential difference detection means connected to the second power supply terminal and the third power supply terminal, and detecting a potential difference between the third power supply terminal and the second power supply terminal; If a potential difference is detected between the third power supply terminal and the third power supply terminal, the potential difference is detected with respect to the gate terminal of the first conductivity type MOS transistor of the tristate driver circuit. Given the same potential as the potential of the third power supply terminal, providing the same potential as the potential of the first power supply terminal to the gate terminal of the second conductivity type MOS transistor of the tristate driver circuit C
An integrated circuit device comprising a MOS type level conversion circuit. 4. A triode comprising a first conductivity type MOS transistor and a second conductivity type MOS transistor having one source / drain terminal connected to each other and the other source / drain terminal and back gate terminal electrically connected to each other. In an integrated circuit device provided with a state driver circuit, a first power supply terminal for applying a first constant potential, a second power supply terminal for applying a second constant potential, and the second power supply terminal Switch means for electrically connecting or disconnecting between the transistor and one source / drain terminal of the first conductivity type MOS transistor; and gate potential control means for controlling the potential of the gate terminal of the first conductivity type MOS transistor. Power supply control means for controlling the switch means and the gate potential control means; and And a second block including the power control means. A back gate terminal of the first conductivity type MOS transistor is connected to the second power terminal. When the first block is powered down, the switch means electrically cuts off between the second power supply terminal and one of the source / drain terminals of the first conductivity type MOS transistor, thereby controlling the gate potential control. The integrated circuit device is characterized in that the means makes the potential of the gate terminal of the second conductivity type MOS transistor equal to the potential difference of the second power supply terminal. 5. An integrated circuit device having a CMOS type level conversion circuit, wherein said CMOS type level conversion circuit applies a first power supply terminal for applying a first constant potential, and applies a second constant potential. A first power supply type MOS transistor, a second first conductivity type MOS transistor, and a second power supply terminal, one of which has a source / drain terminal and a back gate terminal connected to the second power supply terminal. 3, a first second conductivity type MOS transistor, one of which has a source / drain terminal and a back gate terminal connected to a first power supply terminal, and a second second conductivity type MOS transistor. A fourth second conductivity type MOS transistor, and one source / drain terminal is connected to the first first conductivity type M
An OS transistor and the second source / drain terminal of the second first conductivity type MOS transistor are connected to each other, and the other source / drain terminal is connected to the second second conductivity type MO transistor.
A first second conductivity type MOS transistor connected to the other source / drain terminal of the S transistor and a back gate terminal connected to a first power supply terminal; a gate terminal of the second first conductivity type MOS transistor Is connected to the other source / drain terminal of the third second conductivity type MOS transistor and the fourth second conductivity type MOS transistor, and the gate terminal of the third first conductivity type MOS transistor is the first First conductivity type MOS
Transistor and the other source / drain terminal of the second first conductivity type MOS transistor, and the other source / drain terminal of the third first conductivity type MOS transistor is connected to the third second conductivity type MOS transistor. A first data input terminal connected to the other source / drain terminal of the transistor and the fourth second conductivity type MOS transistor, to which a gate terminal of the third second conductivity type MOS transistor is connected; One first conductivity type MOS transistor and the first conductivity type MOS transistor.
A second data input terminal to which a gate terminal of the second conductivity type MOS transistor is connected; a first mode control input terminal to which a gate terminal of the second second conductivity type MOS transistor is connected; And a second mode control input terminal to which a gate terminal of the second conductivity type MOS transistor is connected. 6. An integrated circuit device provided with a CMOS type level conversion circuit, wherein the other source / drain terminal of the first first conductivity type MOS transistor and the second first conductivity type MOS transistor and the first second conductivity type. 6. An integrated circuit device comprising the CMOS type level conversion circuit according to claim 5, further comprising an output terminal connected to one source / drain terminal of the type MOS transistor. 7. An integrated circuit device having a CMOS type level conversion circuit, wherein the other source / source of a third first conductivity type MOS transistor
6. The CMOS type level conversion circuit according to claim 5, further comprising a drain terminal and an output terminal connected to the other source / drain terminal of the third second conductivity type MOS transistor and the fourth second conductivity type MOS transistor. An integrated circuit device characterized by the above-mentioned. 8. A triode comprising a first conductivity type MOS transistor and a second conductivity type MOS transistor having one source / drain terminal connected to each other and the other source / drain terminal and back gate terminal electrically connected to each other. An integrated circuit device provided with a state driver circuit, wherein the first conductivity type MO of the tristate driver circuit is provided.
6. An integrated circuit device, wherein the CMOS level conversion circuit according to claim 5 is electrically connected to respective gate terminals of the S transistor and the second conductivity type MOS transistor. 9. A triode comprising a first conductivity type MOS transistor and a second conductivity type MOS transistor having one source / drain terminal connected to each other and the other source / drain terminal and back gate terminal electrically connected to each other. An integrated circuit device provided with a state driver circuit, wherein the first conductivity type MO of the tristate driver circuit is provided.
7. The CMOS according to claim 6, wherein a gate terminal of the S transistor is provided.
An output terminal of a type level conversion circuit is connected, and an output terminal of the CMOS type level conversion circuit according to claim 7 is connected to a gate terminal of said second conductivity type MOS transistor of said tristate driver circuit. Integrated circuit device.