JPS6014326A - 絶対値演算回路 - Google Patents

絶対値演算回路

Info

Publication number
JPS6014326A
JPS6014326A JP58121951A JP12195183A JPS6014326A JP S6014326 A JPS6014326 A JP S6014326A JP 58121951 A JP58121951 A JP 58121951A JP 12195183 A JP12195183 A JP 12195183A JP S6014326 A JPS6014326 A JP S6014326A
Authority
JP
Japan
Prior art keywords
circuit
binary number
signal line
absolute value
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58121951A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0149973B2 (enrdf_load_html_response
Inventor
Teru Ishizuka
輝 石塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58121951A priority Critical patent/JPS6014326A/ja
Publication of JPS6014326A publication Critical patent/JPS6014326A/ja
Publication of JPH0149973B2 publication Critical patent/JPH0149973B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/544—Indexing scheme relating to group G06F7/544
    • G06F2207/5442—Absolute difference

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
JP58121951A 1983-07-05 1983-07-05 絶対値演算回路 Granted JPS6014326A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58121951A JPS6014326A (ja) 1983-07-05 1983-07-05 絶対値演算回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58121951A JPS6014326A (ja) 1983-07-05 1983-07-05 絶対値演算回路

Publications (2)

Publication Number Publication Date
JPS6014326A true JPS6014326A (ja) 1985-01-24
JPH0149973B2 JPH0149973B2 (enrdf_load_html_response) 1989-10-26

Family

ID=14823950

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58121951A Granted JPS6014326A (ja) 1983-07-05 1983-07-05 絶対値演算回路

Country Status (1)

Country Link
JP (1) JPS6014326A (enrdf_load_html_response)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62142010U (enrdf_load_html_response) * 1986-03-04 1987-09-08
JPS63118835A (ja) * 1986-11-06 1988-05-23 Nec Corp 演算装置
JPH01205328A (ja) * 1988-02-12 1989-08-17 Matsushita Electric Ind Co Ltd 演算処理装置
EP0239276A3 (en) * 1986-03-28 1989-09-06 Texas Instruments Incorporated Alu for a bit slice processor with multiplexed bypass path
JPH0223746U (enrdf_load_html_response) * 1988-07-28 1990-02-16
JPH038018A (ja) * 1989-06-06 1991-01-16 Toshiba Corp 符号付き絶対値加減算器
EP0591846A3 (en) * 1992-09-30 1995-05-10 Texas Instruments Inc Subtraction method and arrangement in or related to signal processing techniques.
US5548675A (en) * 1993-04-02 1996-08-20 The Furukawa Electric Co., Ltd. Multifiber connector, a method of manufacturing the same, and a construction for connecting the multifiber connector to an optical device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62142010U (enrdf_load_html_response) * 1986-03-04 1987-09-08
EP0239276A3 (en) * 1986-03-28 1989-09-06 Texas Instruments Incorporated Alu for a bit slice processor with multiplexed bypass path
JPS63118835A (ja) * 1986-11-06 1988-05-23 Nec Corp 演算装置
JPH01205328A (ja) * 1988-02-12 1989-08-17 Matsushita Electric Ind Co Ltd 演算処理装置
JPH0223746U (enrdf_load_html_response) * 1988-07-28 1990-02-16
JPH038018A (ja) * 1989-06-06 1991-01-16 Toshiba Corp 符号付き絶対値加減算器
EP0591846A3 (en) * 1992-09-30 1995-05-10 Texas Instruments Inc Subtraction method and arrangement in or related to signal processing techniques.
US5548675A (en) * 1993-04-02 1996-08-20 The Furukawa Electric Co., Ltd. Multifiber connector, a method of manufacturing the same, and a construction for connecting the multifiber connector to an optical device

Also Published As

Publication number Publication date
JPH0149973B2 (enrdf_load_html_response) 1989-10-26

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