JPS60138957A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable to reduce the wiring capacity of the titled device and to perform the readout operation of the device at higher speeds by a method wherein wirings, by which a first multiplexer and an output buffer are mutually connected, and wirings, by which a second multiplexer and the output buffer are mutually connected, are provided. CONSTITUTION:There are eight wires of wirings between the terminals Mn (n=1...8) of a multiplexer 3 and the terminals Bn(n=1...8) of an output buffer 4. The half of the terminals Mn of the multiplexer 3, which have been connected to 4 wires of wirings equal to the half of the eight wires of wirings and have been provided on the side of the output buffer 4, are disposed on the opposite side of a memory cell region 7 to the half terminals of the multiplexer 3. A part of a current distributor 2 inclusive of terminals Dn(n=1...4), which had been ever disposed at the positions of the half terminals of the multiplexer 3, is disposed on the opposite side of the memory cell region 7 to the terminals Dn and near the remaining part of the current distributor 2 inclusive of the terminal Mn (n=5...8) of the multiplexer 3. By this chip layout, the wiring between the terminal M1 of the multiplexer 3 and the terminal B1 of the output buffer 4, whose length had been ever the longest and whose wiring capacity had been also the largest, is shortened. As a result, a reduction of the wiring capacity of the semiconductor memory device is contrived and the readout operation thereof can be performed at higher speeds.

Description

[Detailed Description of the Invention] Ramabl'e Reaj 0nly Memory
) regarding the chip layout.

(2) Prior Art and Problems As shown in the schematic plan view of FIG. C
D), Multiplexer (MPX).

Output buffer 4 (OB), memory cell area 7 (MC) in which memory cells are arranged at multiple intersections of word line 5 (WL) and bit line 6 (BL), address buffer 8 (ADD)
), a chip enable circuit (not shown), etc.

To electrically write data to this FROM, the decoder driver 1 selects the word line 5 corresponding to the memory cell to be written, and outputs the output terminal BnO (n=1..2..
3. ......8) The data obtained at the current distributor 2 is sent to the output terminal Bno (n=1°2.3.
...-...8) and terminal Dn (n=1.2.3.-
=8), and the decoder driver 1 causes a write current to flow from the current distributor 2 to the memory cell at the intersection of the bit line 6 connected thereto and the selected word line 5.

The write current blows out a fuse-type memory cell and short-circuits a junk-type memory cell. To read, the decoder/driver 1 selects the word line 5 where the memory cell to be read is located, the multiplexer 3 obtains data from the bit line 6 connected to the memory cell, and sends this data to the output buffer 4. Terminal Mn
t n=1.2゜3,...-8) and terminal Bn (1,
2, 3, . . . 8), is amplified by the output buffer 4, and then output. The address buffer 8 (ADD) u converts an external address input into an internal address signal and inputs it to a decoder such as a decoder/driver 1 (DD).

It takes about 50μB to write one data, and 4 to read it.
It takes about 0 to 100 nS. In this way, the read operation is faster than the write operation, and the multiplexer 3
If the wiring between the terminal Mn (n=112.31...8) of the output buffer 4 and the terminal Bn (n=1.2.3.-=8) of the output buffer 4 is long, the wiring capacitance will be large and the read operation will be slow. There were drawbacks. The read speed at this time is the longest wire,
It is determined by the line with the largest wiring capacity. As shown in FIG. 1, when the output buffer 4 has an 8-bit configuration and consists of 8 wires, and the length in the bit line 6 direction of the output buffer 4 is longer than the length in the word line 5 direction of the multiplexer 3, the output buffer 4
The wiring connected to the terminal B1 farthest from the multiplexer 3 is the longest. In other words, the read speed is determined by the wiring between terminal B1 and terminal M1.

To solve the problem of a drop in read speed due to wiring capacitance, as shown in Figure 2, an output buffer 4 is placed near the multiplexer 3, and the wiring between the multiplexer 3 and the output buffer 4 is made as short as possible. It is considered to do. However, in the arrangement shown in the figure, the overall length increases in the direction of the bit line 6, which imposes restrictions on the chip layout.

(3) Object of the Invention The object of the present invention is to arrange a decoder driver DD connected to a word WLK# on one side of the memory cell area MC in the word WL direction, and an output buffer OB on the other side.
In a FROM, a multiplexer MPX and a current distributor CD are arranged tangent to the bit line BL and the output buffer OB on both sides in the direction of the bit line BL intersecting the WL, and the multiplexer MPX and the output The present invention provides a semiconductor memory device that can substantially reduce the wiring length between 777108, reduce the wiring capacitance, and perform high-speed read operations.

(4) Structure of the invention, [.

According to the present invention, the above object is to provide a decoder/driver connected to the word line on one side of the memory cell region in the word line direction, an output buffer arranged on the other side, and A first multi-branch 2 placed on one side in the bit line direction and a first current ψ distributor placed on the other side are connected to the range 1 bit line group that intersects with the word line. , a second current distributor provided in parallel with the first bit line group, connected to the upper line group and disposed on the side where the first multiplexer is arranged in the bit line direction; , said second
a second multiplexer connected to the upper line group and arranged on the side where the first current distributor is arranged, the first multiplexer, the output buffer, the second multiplexer and the second output. This is achieved by having wiring that connects the buffers.

(5) Embodiment of the Invention An embodiment of the present invention will be explained using the schematic plan view of FIG. 3. As shown in the figure, a decoder/driver 1 is arranged on one side of the memory cell area 7 in the word line direction, not connected to the word line 5, and an output buffer 4 is arranged on the other side, and the word line 5 and Intersecting bit #j! Bit #I on both sides of direction 6! A multiplexer 3 and a current distributor 2 are connected to the output buffer 6, and the length of the output buffer 40 in the bit line direction is the word of the multiplexer 3.

Consider a case where the FROM is longer than the length in the linear direction and has an 8-bit configuration.

Terminal Mn of multiplexer 3 (n=1.2.3.
-8) and terminal Bn of output buffer 4 (n=1.2.3.
・There are 8 wires between z 8). 4, which is half of that number
Half of the output buffer 7 of the multiplexer 3 connected to the book wiring is placed on the opposite side of the memory cell area 70.

In addition, a portion of the current distributor 2 including the terminals Dn (n=1.2..., 4) arranged at that position is located on the opposite side of the memory cell area 70, and the terminals of the multiplexer 3. Mn (n=5.6...

8) Place it near the part containing it.

This chip layout makes it the longest ever
The wiring between the terminal M1 of the multiplexer 3, which has the largest capacity, and the terminal B1 of the output buffer 4 is short, thereby reducing the wiring capacitance and allowing a faster read operation. In addition, only the wiring between terminal M1 and terminal B1 is required, and the wiring between terminal M2 and terminal B2, between terminal M3 and terminal 33, and between terminal M4 and terminal 8 is sufficient.
The wiring between multiplexer 3 is also shorter than before, so
It can be said that the wiring between the output buffer 4 and the output buffer 4 is substantially short.

In this layout, the wiring between terminal Dn (n=1.2.3.-., 8) of current distributor 2 and output terminal 13no (n=1.2.3.-1.8) is essentially Although it is longer, this wiring is not used when reading data but is used when writing data, and a larger current flows at a lower speed than the wiring between multiplexer 3 and output buffer 4, so the increase in wiring capacitance in this case is Not a problem.

In this embodiment, an 8-bit configuration is used, and the wiring between the multiplexer 3 and the output buffer 4 is eight FROM ROMs, and the multiplexer 3 and output buffer 4 are provided on both sides of the memory cell area 7. I wired 4 wires from output buffer 4 to multiplexer 3, which is half of the total number,
The present invention does not necessarily limit the number of wires to be divided into half of the total number, but includes the output buffer 4 and the memory cell area 7.
′! By determining the number of divided stone wirings according to the size and positional relationship of the P-multiplexer 3 and performing wiring, the length of the wiring can be shortened, the wiring capacitance can be reduced, and the read operation can be made faster.

(6) Effects of the Invention According to the present invention, the decoder/driver DD is connected to the word line WL and arranged on one side of the memory cell area MC in the word 1 daughter direction, and the output buffer OB is arranged on the other side. and intersects with word -WL -t7y k' -y h
8 RL (iD direction OjtjHlllt K e ,
y h m B L K ”: Once connected, the multiplexer MPX and current decoder □ Inutribeater CD is placed, and the output tool:::111 The length of the rough OB in the bit H direction is multiplexed. 1:
PROm which is longer than the length of MPX in the cross direction: 1
Then, divide the multiplexer MPX into 2+ and write the memo ,'
147L = engineering. . □411 K'fi 1it-r
岑. 5, → 11 The layout between the multiplexer IVI P
The wiring capacitance can be reduced: 1 can speed up the read operation. 1□:1

[Brief explanation of drawings]

1 and 2 are schematic plan views of a conventional example of FROM, and FIG. 3 is a schematic plan view for explaining an embodiment of the present invention. In the figure, ] is the decoder driver (DD), 2 is the current distributor (CD), 3 is the multiplexer (NPX), 4 is the output buffer (OB), 5-digit word line (WL), 6 is the pin, m (BL), 7 is memory k L area (MC), 8 is atlus buffer (ADD
).

Claims (1)

[Scope of Claims] A decoder/driver connected to a word line and arranged on one side of the memory cell area in the word line direction; an output buffer disposed on the other side; a first multiplexer connected to a first bit line group crossing the word line and disposed on one side in the bit a direction; and a first multiplexer disposed on the other side. The first one. Ka V 7 h, 74-', 'J ez J' and before! 12th. 1. A second current distributor connected to a second bit line group provided in parallel to the bit line group and not disposed on the side where the first multibranch in the bit line direction is arranged; The first current 1. is connected to the second bit line group. A second cable tip is placed on the side where the distributor is placed. A semiconductor memory device characterized in that a lexer, a wire connecting the first multiplexer and the output buffer, and a wiring connecting the second multiplexer and the output cover and the buffer are connected to each other.