JP2564507B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a spare memory element, and in the case where a main (normal) memory element has a fault and is used by switching to the spare memory element. Is to prevent the access time from becoming too long.

[Conventional technology]

In a large-capacity semiconductor memory device, a spare or redundant memory element is provided in advance in order to prevent the failure of a small number of memory elements to result in a defective product, and a defective memory element is found in the main memory element group by inspection. When the address is accessed, the spare memory element is accessed instead of the defective memory element. The replacement of the failed main memory element by the spare memory element is extremely effective for improving the yield, but in the conventional device, it takes more time when the spare memory element is accessed than when the main memory element is accessed.

[Problems to be solved by the invention]

This will be described with reference to FIG. 8. (a) shows the operation when a normal address (main memory element) is selected, and (b) shows the operation when a defective address (spare memory element) is selected. There are 5 steps from address input acquisition to sensing and output, whereas in (b) there are 6 steps, which is increased by 1 step (comparison between address input and defective address).

The semiconductor memory device has many word lines and bit lines,
Storage elements are arranged at these intersections, but four word lines are used.
FIG. 9 (a) shows the essential part of the bit line in a simplified manner. X _{0 to} X ₃ are word lines, B ₀ and B ₁ are bit lines, C ₀₀
~ C ₃₁ is a memory element. In the case of SRAM (static ram), each bit line consists of two lines, and the memory element is a flip-flop. In case of DRAM (dynamic ram), one word line and one bit line, and one memory element is generally used.
Although it is a transistor 1 capacitor, these are simply represented in FIG. 7 as shown. G _{0 to} G ₃ are address decoders, which select word lines by inputting predetermined ones of the address signals A ₀ , ₀ , A ₁ , ₁ generated by the address buffer AB by the row addresses A ₀ , A ₁ . CG ₀ and CG ₁ are bit line selection gates, and Y ₀ and Y ₁ are outputs of a column decoder that opens and closes the gates. DB is a data bus, and IOB is a buffer for input (write) data D _IN and output (read) data D _OUT . Ga and Gb are comparison units for address input and defective address, and Gc is a preliminary decoder. In this example, a spare memory element is provided for one word line, C ₀ and C ₁ are the spare memory elements, and X _R is a spare word line.

The defective address is stored in a ROM (read-only memory), and the ROM is shown in FIGS. 7B and 7C. This is a fuse type, F is the fuse, and Q is a fuse blow control transistor. Memory (semiconductor memory device)
If there is a defective cell (faulty memory element), the program signal is set to L (low) level, so that the output of the inverter I in FIG. 7C is H (high) level, the transistor Q is on, and the fuse F is blown. The signal ROMr becomes L. If the defective row address is, for example, A ₀ = A ₁ = L, the output of the NOR gate G in FIG. 7B is A ₀ = L and H, the transistor Q is on, the fuse F is blown, and the signal ROM ₀ is It becomes L.
Although not shown, a circuit similar to that shown in FIG. 7B is provided for the address A ₁ , and the output ROM ₁ of the circuit becomes L. Therefore, in FIG. 7A, when the input addresses A ₀ and A ₁ are both L (when a defective address is selected), the exclusive OR gates Ga and Gb
Output of L and the output of NOR gate Gc become H, so that the spare word line X _R is selected and the word decoders of the main memory element group are simultaneously deselected.

The address input fetch in Fig. 8 means the row address.
A _0, A ₁ uptake, i.e. address input pins A _0, A address buffer output A ₀ from the address signal is set in _1,
0 , A ₁ , until the output signal corresponding to ₁ is output. In addition, address input and comparison of defective addresses are gate G
The operations of a and Gb are referred to, and the main decoder operation of is the operations of the word decoders G _{0 to} G ₃ . And are done at the same time.
The word line rising operation is a quad line drive by a word decoder which has produced an H level output, whereby the transfer gate of the memory cell becomes conductive and cell storage information (potential) appears on the bit line. Says this. When the cell storage potential is output to the bit line, the sense amplifier operates and the potential pulled up / down to H and L is taken out to the data bus DB through the gate ( _one of Q ₀ and Q ₁ ) selected by the column address. And is sent to the outside through the buffer IOB. Says this. The normal case is as shown in FIG. 8 (a), but if there is a defective memory chip cell, FIG. 8 (b) is shown.
When the address input of and the defective address are compared and the outputs of the gates Ga and Gb become L, the preliminary decoder G
c operates (produces H level output), the operation of the main decoder is prohibited, and the spare word line X _R is selected. After that, although it is the same as in the normal case, it is needless to say that the stored information in the spare storage element is read. When there is this defective cell, the word decoder (Gc) operation comes next, and it is delayed by one step.

The present invention aims to make this delay inconspicuous by increasing the operation speed of the device. Speaking of Fig. 8 + '
It is intended to be + '+' + '+++.

[Means for solving problems]

The present invention relates to a semiconductor memory device having a spare memory element, and if the main memory element has a failure, the spare memory element is accessed instead of the defective main memory element. It is characterized in that the word line is made of a material having a resistance lower than that of the word line in which the main memory element group is arranged.

[Operation and Example]

As the spare memory element, the same one as the main (normal) memory element is generally used. For example, if the main memory element is a flip-flop composed of four or six MOS transistors, the spare memory element also has the same four or six memory cells. It is a flip-flop composed of individual MOS transistors. In this type of memory, the word line also serves as the gate of the transfer gate transistor, and is therefore usually made of polycrystalline silicon. However, since the polycrystalline silicon has a large sheet resistance, RC delay due to the resistance is introduced and the operation speed becomes slow. Therefore, in the present invention, the word line for the spare memory element is made of aluminum having a low resistance to increase the operation speed. In this way, the delay due to the introduction of the steps described above is offset, and the same access time as when the main memory element is selected can be obtained when the spare memory element is selected.

FIG. 1 shows the word line WL of the spare memory element Cr in this embodiment.
r is made of aluminum (Al), and the word line WL of the main memory element Cm is made of polycrystalline silicon. FIG. 1A shows an outline of a plane pattern, and FIG. 1B is an equivalent circuit diagram thereof.
Reserve storage element includes a MOS transistor Q ₃ to Q ₆ and a pair of load resistors, main storage element Cm is similarly MOS transistor Q
₃ 'to Q _6' and consists of a pair of load resistors. Q ₁ and Q ₂ are MOS transistors that pull up the bit lines BL and ▲ ▼ to the power supply Vcc, and CG and ▲ _η ▼ are column select gates that connect the bit lines BL and ▲ ▼ to the data bus DB and ▲ ▼. The MOS transistor Y is the selection signal.

When the word line WL of the main memory element is selected, this word line has a large resistance, so that it becomes dull like WLw in FIG. 1 (c) at the portion far from the word decoder, and it takes time to read the cell memory data. A delay of Δt occurs. Since the worst case must be assumed for the memory, the reading will be after Δt time. Although the decoding operation of the spare memory element is delayed for the above reason, the resistance of the word line WLr is small,
The place far from the word decoder is also like WLrw in FIG. 1 (c), and there is no particular difference from the place near (WLr). Then, it is possible to match the access delay of the spare memory element with the Δt.

The word line is orthogonal to the bit line, and the bit line is made of aluminum. Therefore, if the word line is also made of aluminum, it becomes a two-layer aluminum wiring, which is difficult to manufacture. So first
As shown in the figure, when the spare memory element is arranged at the upper end of the bit line (the side opposite to the data bus), pull-up transistors Q ₁ and Q ₂ are formed in this portion, and the bit line starts after this. Therefore, as shown in the figure, by passing the word line WLr formed of aluminum over Q ₁ and Q _2, it is possible to avoid the intersection with the bit line and avoid the aluminum two-layer wiring.

The spare memory elements may be arranged in the bit line direction instead of the word line direction as shown in FIG. In addition, a memory device (memory chip) generally has one address 1 bit such as 16K × 1bit and many addresses (16K in this example), but one address multiple such as 4K × 4bit or 2K × 8bit. Some are bit. In the latter one-address multi-bit memory chip, the storage element group is divided into blocks as shown in FIG. 3, and a data bus and an I / O buffer are provided for each so that a plurality of bits can be simultaneously input / output. In order to provide a group of spare storage elements arranged in the bit line direction in such a blocked memory, FIG. 3A or FIG.
I am doing like. (A) is the row decoder RD of each block
A spare column (a group of spare memory elements in the bit line direction) is provided on the side opposite to the above, and conversely, it is provided on the row decoder side in (b). Since the word line is output from the row decoder RD in the horizontal direction in the drawing, the word line in the spare column N of the last block rises at the end of the word line in (a), and the above-mentioned delay is added to this. Access to the spare column N is delayed considerably. In (b), the word line in the spare column N rises by τ rather than the word line end of the block N rises.
₁ (Signal propagation delay time for word line length in block)
However, the delay must be absorbed within this τ ₁ .

In the present invention, the spare columns are arranged close to the row decoder side as shown in FIG. In this way, it is sufficient to absorb the delay within the delay time τ ₂ and the design and manufacture of the preliminary row can be facilitated.

The spare column in the bit line direction is selected by the bit line select gate. That is, referring to FIG. 9, a spare bit line Br similar to the bit lines B ₀ and B ₁ is provided, and a spare bit line Br is provided at each intersection of the word lines X _{0 to} X ₃ (in this case, X _R is not provided). A memory element is provided and Br is selected by a gate corresponding to G _{a to} G _c .

FIG. 5 is a diagram showing spare bit lines and bit line selection gates. B _{0 to} B _n are bit lines for the main memory element group, Br is a bit line for the spare memory element group, and CG _{0 to} CG _n and CG _r are These are selection gates for these bit lines. If the defective address storage device input to the coincidence circuit (exclusive OR gate) Gd does not match the input address information, that is, if the memory access address is not the address of the defective cell (column), the output of the gate Gd is at the H level, The column decoder CD outputs the bit line selection output Y _{0 as} usual, that is, according to the input column address.
Output ~ Y _n . On the other hand, if the above two pieces of information match, the output of the gate Gd becomes L level, which prohibits the operation of the column decoder CD, and the spare column decoder (nand gate in this case) Gf produces an H level output. , The gate CGr is turned on to select the spare bit line Br.

The column decoder CD has column addresses b ₀ , b ₁ , ...
, B ₀ or ₀ , b ₁ or ₁ , ... Are input, and the transistors are connected in parallel and a common load thereof. Since a NOR gate is provided for each bit line, therefore, in order to prohibit the operation of the column decoder CD by the output of the gate Gd, a transistor is added in parallel to each transistor of the NOR gate for each bit line, and the additional transistor is gated.
It can be turned on and off with the inverted output of Gd.

However, in the circuit of FIG. 5, since the spare bit line Br is also connected to the same data bus DB as the bit lines B _{0 to} B _n for the main memory element group, the spare memory element bears the same load as the main memory element. Become. Further, the operation of the column decoder CD is prohibited by adding transistors to the NOR gates for the bit lines B _{0 to} B _n as described above, and the configuration is complicated.

FIG. 4 is an improvement of this, in which gates CGs are added to separate the data bus DB for the bit lines B _{0 to} B _{n from} the data bus DB ′ of the I / O buffer, and the spare bit line is the data bus DB. Not be connected to. This gate (MOS
Transistor) CGs are opened and closed by the output of the matching circuit Gd,
When the memory access address is not a defective address, the gate CGs is made conductive to connect the bus DB to the bus DB '.
When the access address is a defective address, the output of the gate Gd is L and the output of the gate Gf is H, so that the gate CGs is non-conductive and CGr is conductive. According to this circuit, the spare memory element does not need to drive the data bus DB, so that high speed operation is possible and it is useful for absorbing the delay. Also, since it is sufficient to select with the gate CGs, it is not necessary to disable the column decoder CD even when accessing a defective address.
Therefore, it is not necessary to provide the above-mentioned additional transistor, and the configuration is simplified. As described above, according to the circuit of FIG. 4, the operation of the auxiliary memory element can be speeded up and the overall speed power product can be improved.

When the spare memory element group is provided in the word line direction, it becomes as shown in FIG. 9 and as shown in FIG. 7 (a), and has the same length as the word line passing through the main array (main memory element array). When the spare word line passes through the spare array (preliminary memory element array) and the word line is made of a high sheet resistor such as polycrystalline silicon, it also has a large RC time constant. Therefore, the m × 1 bit (of course, m × 2 bit or the like may be used) spare array is separated from the main array, and k × l (of course k
When a memory of × 1 = m × 1) bits is configured, this spare memory has a short word line length and a small bit line length, and can operate at high speed. FIG. 6 shows another embodiment of the present invention based on such a principle. Since the spare array also constitutes one memory (although it is constructed on the same chip as the main array), a row decoder and a column decoder are required, and RDe and CDr are these decoders. The address signals input to the decoders RDr, CDr are the addresses input to RD, CD of the main array as A ₀ , A
_{1, ...... b 0, b 1} , as shown in the figure to the ...... b ₀ and b _1, b ₂ and b
₃ , the match circuit Gd inputs the defective address storage information as a defective row address, and if this matches the input memory access row address, the output of the exclusive OR gate Gd is L,
The output of the NAND gate Gf becomes H, and the column decoder CDr
Is valid and the column decoder CD is disabled.

〔The invention's effect〕

As described above, in the present invention, the access to the spare memory element is made faster than that of the main memory (normal) memory element, so that the delay occurring when the spare memory element is selected is canceled,
Preliminary memory element selection can be performed in the same manner as normal element selection, and is extremely effective.

[Brief description of drawings]

FIG. 1 shows a first embodiment of the present invention, (a) is a schematic plan view, (b) is a circuit diagram, and (c) is a waveform diagram for explaining the operation. FIG. 2 is an explanatory diagram showing a second embodiment of the present invention, and FIGS. 3 (a) and 3 (b) are explanatory diagrams of a conventional example with respect to FIG. FIG. 4 is a circuit diagram showing a third embodiment of the present invention, and FIG. 5 is a circuit diagram showing a conventional example for FIG. FIG. 6 is a block diagram showing a fourth embodiment of the present invention, and FIG. 7 is an explanatory view of the principle of FIG. FIG. 8 is an explanatory diagram of a read operation in a conventional memory, and FIG. 9 is a circuit diagram of a main part of the conventional memory. In the drawing, C ₀ and C ₁ are spare memory elements, C ₀₀ , C ₀₁ ... are main memory elements, X _R is a spare word line, and CGs are gates.

 ─────────────────────────────────────────────────── --Continued front page (56) References JP-A-57-198593 (JP, A) Nikkei Electronics [252] (Published November 24, 1980) Nikkei McGraw-Hill P. 82-100, "Silicide technology to reduce wiring delay in high-speed, highly integrated LSI"

Claims (2)

(57) [Claims] 1. A semiconductor memory device having a spare memory element and configured to access the spare memory element instead of the defective main memory element if the main memory element has a fault,
A semiconductor memory device, characterized in that a spare word line on which a group of spare memory elements is arranged is formed of a material having a resistance lower than that of a word line on which a group of main memory elements is arranged. 2. The spare word line is formed by the same wiring layer as the bit line so as not to cross the plurality of bit line groups along the ends of the plurality of bit line groups. The semiconductor memory device according to claim 1.