JPS60138637A - Multiplier - Google Patents

Abstract

PURPOSE:To attain high density mounting and a high-speed operation of a system by providing a selection circuit at the output side of a multiplication circuit which obtains the product data and outputting the high-order and low-order product data through one of both terminal groups to which multiplier and multiplicand data are supplied. CONSTITUTION:A multiplier has terminal groups 1 and 3 containing terminals of (n) bits respectively together with input registers 2 and 4, a multiplication circuit 5 and output registers 6 and 7 respectively. While a selection circuit 8 selects and outputs high-order and low-order data of the product data in response to a control signal. This output data is supplied to the terminal group 3 via a tristate buffer 12, and high-order and low-order product data are outputted successively from the group 3. Therefore the terminal group exclusive for output can be omitted, and furthermore, 3n pieces of connection lines can be reduced down to 2n pieces for a system which contains just a pair of buses.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a multiplier particularly intended for application to general-purpose systems.

[Technical background of the invention]

FIG. 1 is a block diagram showing the configuration of a conventional multiplier.

From terminal group 1 having terminals for n bits to input renostar 2
n bits of multiplier data stored in the input register 4 from the terminal group 3 having terminals for n bits.
The bit multiplicand data is multiplied by the multiplier circuit 5 to obtain 2n-bit product data. The upper n bits of this product data are sent to the output register 6.
The lower bit data is once stored in another output register 7, respectively. In addition, the above-mentioned city power register 6
, 7 are supplied in parallel to a selection circuit 8, and the upper and lower data selected by this selection circuit 8 are sent from the terminal group 1o via a tri-state buffer 9 whose output state can be in a high impedance state. Output. Further, only the lower-order data stored in the one output register 7 is outputted from the terminal group 3 via another tri-state buffer 11 whose output state can similarly be a high impedance state.

That is, in this multiplier, multiplier data and multiplicand data are respectively input from terminal group 1.3, and upper and lower data of the product data are sequentially output from terminal group 10. , terminal group 1 is used as an input-only terminal group, and terminal group 1o is used as an output-only terminal group.

As is well known, using a terminal group as input or output only, compared to using it as a common input/output terminal group, eliminates the need for control for input/output switching.
The control circuit becomes simpler, unnecessary waiting time that occurs when switching input and output is eliminated, and high-speed operation becomes possible.
There are advantages such as

[Problems with background technology]

However, when the conventional multiplier shown in FIG. 1 is applied to a system, the following problems remain in terms of versatility. First, when using the above conventional multiplier in a system in which only one set of n common signal bus lines (hereinafter referred to as paths) is provided, a total of 3n of terminal groups 1, 3° 10, It is necessary to connect two signal lines, which reduces the mounting density on printed circuit boards and the like.

Further, an example in which the present invention is used in a system in which two sets of n paths are provided will be explained using the system block diagram shown in FIG. In FIG. 2, the multiplier in FIG. J1 is shown as a multiplier M, and this multiplier M has three terminal groups 1.3.1.
0 is set. First, the multiplier data is one path B
When the multiplicand data is supplied from the other path B2, both data are taken into the multiplier M through the terminal groups 1 and 3 connected to the paths B1 and B2. Multiplier M performs multiplication and outputs product data as a result to terminal groups 1o and 3. The terminal group 1o has n signal lines 2
1, the above path B1 and the terminal group 3 are connected to n signal lines 2.
2 to the above-mentioned path B2. Furthermore, although a plurality of functional blocks are normally connected to the paths B1 and B2, only two functional blocks Fl and F2 that require product data are shown. From the conditions determined by this system, when the functional block F1 is connected to the path B1 via n signal lines 23, and the functional block F2 is connected to the path B2 via n signal lines 23, the node Since the product data of upper and lower parts is output to bus B-41, there is no problem with function block F1, but only lower data is output to bus B2, so function block F2 also requires upper data. In this case, this functional block F2 is connected to the node B by n signal lines 25.
I have no choice but to connect with No.

When there are many such functional blocks in a system configuration, the extra wiring increases in proportion to the number of functional blocks, which not only reduces the mounting density of cylinder boards, etc., but also increases the load on the paths and reduces the operating speed. A problem arises.

[Purpose of the invention]

This invention was made in consideration of the above circumstances, and its purpose is to provide a multiplier that can realize high-density packaging and high-speed operation of the system when applied to a system. It's about doing.

[Summary of the invention]

In order to achieve the above object, the present invention provides a selection circuit on the output side of a multiplier circuit that obtains product data of multiplier data and multiplicand data, and selects the upper and lower product data as the selection output of the multiplier. Data and multiplicand data are sequentially output from at least one of the terminal groups to which they are supplied.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing the configuration of a multiplier according to an embodiment of the present invention. In FIG. 3, numerals 1 and 3 are terminal groups each having terminals for n-bits and 5, numeral 2.4 is an input register, 5 is a multiplication circuit, and 6 and 7 are output registers. Reference numeral 8 denotes a selection circuit to which the upper and lower data stored in the output register 6.7 are supplied in parallel, and selectively outputs either the upper or lower data in response to a control signal (not shown). The circuit of this embodiment differs from that of FIG. 1 in that the output of the selection circuit 8 is outputted from the terminal group 3 via a tri-state buffer 12. The tri-state buffer 12 includes the tri-state buffer 9,
Similarly to No. 11, the output state can become a high impedance state in response to a control signal (not shown).

In such a configuration, the selection circuit 8 selectively outputs the upper and lower data of the product data according to the control signal, and this output data is supplied to the terminal group 3 via the tristate buffer 12, so that this terminal Top from group 3,
Lower product data is output in sequence. Since the terminal group 10 dedicated to one output is removed compared to the conventional one shown in FIG. 1, the number of terminals is reduced compared to the conventional one, and high-density packaging can be realized as a single multiplier.

Furthermore, when using this multiplier in a system with only one set of paths, it is possible to reduce the number of signal lines that needed to be connected between the paths to 2n instead of the conventional 3n. , high-density packaging can be achieved as a system.

FIG. 4 is a system block diagram showing an example of application in which the multiplier according to the above embodiment is used in a system in which two sets of paths are provided. In addition, in FIG. 4, Bl, B
2 is pass, Fl.

F2 is a functional block and M is a multiplier according to the above embodiment shown in FIG. First, multiplier data is sent from path B1 via signal line 31, and multiplicand data is transferred to signal line 32.
from path B2 to terminal group 1.3 of multiplier M. Multiplier M takes in both of the above data and outputs the product data to terminal group 3. This terminal group 3 is also connected to the path B1 via a signal line 33, and both the upper and lower data of the product data are supplied to the nodes B1 and B2. Therefore, the functional blocks Fl and F2 can be connected to nodes determined only by the system conditions, ignoring the relationship between upper and lower product data. As a result, system design becomes easier, and moreover, as in the case of Fig. 2, when the functional block F2, which also requires upper-level data, needs to be connected to both Bl and B2 paths, there is no need to use extra signal lines. connection becomes unnecessary. Therefore, not only the packaging density is improved, but also the load on the paths B1 and B2 is reduced, allowing high-speed operation.

By the way, in the multiplier of this embodiment shown in FIG. 3, when outputting product data from the terminal group 3, upper data and lower data are output in a time-sharing manner. Regarding the waiting time required when switching between the upper and lower data, due to the nature of the calculation method of the multiplication circuit 5 that obtains the product data, the lower data is determined more quickly than the upper data. with the f system that outputs the above data later.

is not a problem. However, upper and lower data cannot be output simultaneously.

FIG. 5 is a block diagram showing the configuration of a multiplier according to another embodiment of the invention. This embodiment is designed to further eliminate the above-mentioned disadvantages of the multiplier shown in FIG. A buffer 14 has been added. Similar to the selection circuit 8, the selection circuit 13 is supplied with the upper and lower data stored in the output registers 6 and 7 in parallel, and either the upper or lower data is selectively output according to a control signal (not shown). be done. The output of this selection circuit 13 is outputted from the terminal group 1 via a triste taper and a filter 14.

In such a configuration, since the selection circuits 8 and 13 can output either the upper or lower data of the product data, the selection circuits 8 and 130 control select the upper and lower data of the product data from the terminal groups 1 and 3. can be output simultaneously. Further, since the product data is also output from the terminal group 1, the connection by the signal line 33 in FIG. 4 is unnecessary. Furthermore, according to the control signals given to the selection circuits 8 and 13, various combinations of output data can be obtained from the terminal groups 1 and 3, such as a combination of the same data, a combination of different data, etc., as shown in FIG. This increases the versatility of the system.

FIG. 7 is a block diagram showing the configuration of a multiplier according to still another embodiment of the invention. In this embodiment, the upper data stored in the output register 6 is supplied to the terminal group 1 via the switch circuit 15, and the output register 7
The lower data stored in .
Another switch circuit 17 is connected between the 16 outputs.

Each of the switch circuits 15, 16, 11 is made conductive or non-conductive between its input and output based on a control signal (not shown).

FIG. 8 shows one bit out of n bits when the switch circuits 15, 16, and 17 are constructed using tristate buffers TB.

Switch circuits 15 and 16 each include one tri-state buffer TBI, TB2.

In addition, since the switch circuit 17 outputs upper data to the lower side and lower data to the upper side, the data transfer direction needs to be bidirectional. Therefore, in this switch circuit 12, the input and output terminals are in antiparallel. Two connected tri-state buffers TBS and TB4 are provided for each bit. FIG. 9 collectively shows the relationship between data output from the terminal group 1.3 when each of the tri-state buffers TBI to TB4 is set to the on or off state. Note that combinations other than those shown in FIG. 9 are omitted because the prohibited number of cases and product data are not valid. Further, the on state of the tri-state buffer means that the input and output are in a conductive state, and the off state means that the tristate buffer is in a non-conducting state and the output state is in a high impedance state.

FIG. 10 shows the switch circuit 1 in the embodiment shown in FIG. 7 above.
5, 16, and 17 are configured using a transfer adder (TG). In FIG. 10, the switch circuits 15 and 16 each include one transfer dart TGI, TG2 ff:
The switch circuit 17 also includes one transfer gate TG3. That is, transfer f −) T G
is originally bidirectional, so the 1701-bit switch circuit that requires bidirectionality requires one transferer)
T.G.? This has been realized. FIG. 11 summarizes the relationship between the data output from the terminal group 1.3 when each of the above-mentioned transfer groups TGJ to TG3 is set to the on or off state. In addition, N-channel, P-channel MO is used as TG)
A single channel type using either one of 8FETs or a C-MOS type using both can be used. Further, in this embodiment, switch circuits 15 and 16
．． 17 uses a dry state muffer TB or a transfer dart TG, but any type of device may be used as long as the input and output can be brought into a conductive or non-conductive state.

In this embodiment circuit shown in FIG.
, 7 and the switch circuits 15 and 16, only 2n wires are required, and the output register 6 in the embodiment circuit shown in FIG.
, 7 and the selection circuit 8.13 is half the wiring 4n, and as a result, the mounting density has been improved and the circuit configuration has been simplified compared to Fig. 5. FIG. 2 is a block diagram showing the configuration of a multiplier according to another embodiment of the present invention. In each of the above embodiments, the product data obtained by the multiplication circuit 5 is once stored in the output register 6.7 and then output from the terminal group 3 or the terminal group 1.3. Therefore, in this embodiment, in order to shorten the calculation time, the output register 6 is
, 7, etc., so as to provide a data route that does not pass through the network. That is, in this embodiment circuit, two switch circuits 18 and 19 are newly added to the embodiment circuit shown in FIG. The input end of one switch circuit 18 is connected to the output end of the multiplication circuit 5, and the output end is connected to the output end of the switch circuit 15.The input end of the other switch circuit 190 is connected to the output end of the multiplication circuit 5, and the output end is connected to the output end of the multiplication circuit 5. The end is switch circuit 1
6 output terminals, respectively. In this embodiment circuit, if it is necessary to output product data quickly, the output register 6 can be made conductive by making the switch circuits 18 and 19 conductive and making the switch circuits 15 and 16 non-conductive.
, 7, the product data is led to the terminal group 1.3.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, in the above embodiment, a case has been described in which one terminal group is commonly used for data input/output, but this may be used independently for input and output.

〔Effect of the invention〕

As described above, according to the present invention, when applied to a system, it is possible to provide a multiplier that can realize high-density packaging and high-speed operation of the system.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional multiplier, Figure 2 is a system block diagram of a system using the multiplier in Figure 1, and Figure 3 is a block diagram of a system using the multiplier in Figure 1.
Figure 4 is a block diagram of a multiplier according to an embodiment of the present invention, Figure 4 is a system block diagram of a system using the multiplier of Figure 3, and Figure 5 is a multiplier according to another embodiment of the invention. , FIG. 6 is a diagram collectively showing the output data of the multiplier in FIG. 5, FIG. 7 is a block diagram of a multiplier according to still another embodiment of the present invention, and FIG. 8 is a part thereof. 9 is a diagram showing all the output data from the circuit in Figure 8, Figure 10 is a concrete circuit diagram of a part of the circuit in Figure 7, and Figure 11 is the output from the circuit in Figure 10. FIG. 12 is a schematic diagram of a multiplier according to another embodiment of the present invention. 1.3...Terminal group, 2.4...Input register, 5.
...Multiplication circuit, 6, 7... Output register, 8. No. 3・
... Selection circuit, 12.14... Tri-state buffer, 15, 16, 17.18.19... Switch circuit. Applicant's Representative Patent Attorney Takehiko Suzue Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 8 Figure 9 Figure 10 (Figure + 2

Claims (6)

[Claims] (1) First. a second terminal group; a first input register that stores multi-bit multiplier data supplied to the first terminal group; and a first input register that stores multi-bit multiplicand data supplied to the second terminal group. a second input register; and the first input register. a multiplication circuit that performs multiplication between multiplier data and multiplicand data stored in a second input register to obtain product data; a first output register that stores upper data of the product data; a second output register storing lower-order data among the first and second output registers; A multiplier comprising output control means for sequentially outputting upper data and lower data stored in a second output register from at least one of the first and second terminal groups. (2) The output control means includes the first output control means. The upper data and lower data stored in the second output register are supplied in parallel, and the upper data and lower data are selected in accordance with the control signal. The multiplier according to claim 1, comprising a selection circuit that sequentially supplies at least one of the second terminal group. (3) The output control means includes the first output control means. The upper data and lower data stored in the second output register are supplied in parallel, and the upper data and lower data are selected in accordance with the control signal. 2. The multiplier according to claim 1, comprising first and second selection circuits that sequentially supply signals to the second terminal group. (4) The output control means includes the first output control means. The first . a second switch circuit; and the first switch circuit.
The multiplier according to claim 1, further comprising a third switch circuit provided between the output ends of the second output register. (5) The multiplier according to claim 4, wherein the third switch circuit is configured to transfer data bidirectionally. (6) The product data is the first. 2. The multiplier according to claim 1, further comprising a data path that is supplied to said output control means without going through a second output resistor.