JPS60137178A - Solid-state image pickup device - Google Patents

Solid-state image pickup device

Info

Publication number
JPS60137178A
JPS60137178A JP59257530A JP25753084A JPS60137178A JP S60137178 A JPS60137178 A JP S60137178A JP 59257530 A JP59257530 A JP 59257530A JP 25753084 A JP25753084 A JP 25753084A JP S60137178 A JPS60137178 A JP S60137178A
Authority
JP
Japan
Prior art keywords
charge transfer
horizontal
transfer element
solid
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59257530A
Other languages
Japanese (ja)
Inventor
Shinya Oba
大場 信弥
Masaaki Nakai
中井 正章
Toshibumi Ozaki
俊文 尾崎
Kenji Takahashi
健二 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59257530A priority Critical patent/JPS60137178A/en
Publication of JPS60137178A publication Critical patent/JPS60137178A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To improve the performance of a two-dimensional solid-state image pickup device provided with charge transfer elements by driving the charge transfer element of a horizontal register on three-phase basis. CONSTITUTION:When a three-phase register is used as the charge transfer element 8, information can be stored at positions corresponding to two phases among three phases. Therefore, two signals from two picture elements can be stored in the charge transfer element 8. Consequently, a vertical signal line 4 is swept in the beginning of a horizontal blanking period to sweep excessive charges out through a gate 10, and picture elements (a) and (b) and signals charges on one lateral line are read in the charge transfer element 8. Gates 5 and 6 are turned off during a horizontal scanning period to read a signal successively.

Description

【発明の詳細な説明】 本発明は、受光部にホトダイオードアレーを設け、読み
出し用水平レジスタとして電荷転送素子(Charge
 T ransfer D evice、以下CTDと
略す)を設けた2次元固体撮像装置に関するものである
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a photodiode array in the light receiving section, and uses a charge transfer element (Charge) as a readout horizontal register.
The present invention relates to a two-dimensional solid-state imaging device equipped with a transfer device (hereinafter abbreviated as CTD).

第1図は、受光部にダイオードアレーを、読み出しレジ
スタにCTDを設けたホ1−センサの1例を示すもので
ある(実願昭54−157030号)。
FIG. 1 shows an example of a sensor having a diode array in the light receiving section and a CTD in the readout register (Utility Application No. 157030/1983).

図中、■はホトダイオード、2は垂直スイッチM I 
S l−ランジスタ、3は垂直走査回路、4は垂直信号
線、5(5’ )、6(6’ )はグー1−Ml5トラ
ンジスタ、7(7’)は出力アンプ、8(8’)は水平
レジスタとしてのcTD、9(9’)4iCTDの入力
部であり、10(10’ )はブルーミング抑圧回路で
ある。普通、CTD8(8’ )は2相(Hl、l−1
2パルス)もしくは擬4相で駆動される。水平走査期間
中に垂直信号線4に7.ミ積された、ブルーミングや垂
直スメアなどの擬似信号を、水・平ブランキング期間の
最初にゲー1〜5と10を通して外部に掃き出す。その
後、第1図■で示した横−行の画素が選択され、−行分
の信号は一括して上方の■チャネルのCTDレジスタ8
に移送され、そ九ぞれのメモリ部にス1へアされる。
In the figure, ■ is a photodiode, 2 is a vertical switch MI
S l-transistor, 3 is vertical scanning circuit, 4 is vertical signal line, 5 (5'), 6 (6') are Goo1-Ml5 transistor, 7 (7') is output amplifier, 8 (8') is cTD as a horizontal register, 9(9') is an input part of 4iCTD, and 10(10') is a blooming suppression circuit. Normally, CTD8 (8') consists of two phases (Hl, l-1
2 pulse) or quasi-4 phase. 7. to the vertical signal line 4 during the horizontal scanning period. The accumulated pseudo signals such as blooming and vertical smear are swept out through the gates 1 to 5 and 10 at the beginning of the horizontal and horizontal blanking periods. Thereafter, the pixels in the horizontal row indicated by ■ in FIG.
The data is transferred to the memory section 1 of each memory section.

以上の動作を水平ブランキング期間の前半に行ない、後
半は同゛様に第1図下方の■チャネルのCTDレジスタ
に図中■で示したホ1−ダイオードの横−行分の信号を
移動しス1へアする。水平走査期間はゲート6.6′を
offとし、CTDを駆動して出力アンプ7,7′から
2ラインの信号が同時に読み出される。2ラインの信号
を同時に読み出すのは、単板カラーセンサとしての画像
の解像度を向上させるためである。第2図に各パルス、
特に水平ブランキング期間前甲、のタイミングチャー1
−を示しである。
The above operation is performed in the first half of the horizontal blanking period, and in the second half, the signal corresponding to the horizontal row of the diode indicated by ■ in the figure is transferred to the CTD register of the channel ■ in the lower part of Figure 1. Go to step 1. During the horizontal scanning period, the gates 6 and 6' are turned off, the CTD is driven, and two lines of signals are simultaneously read out from the output amplifiers 7 and 7'. The purpose of reading two lines of signals at the same time is to improve the resolution of the image as a single-plate color sensor. Figure 2 shows each pulse,
In particular, the timing chart 1 of the front part of the horizontal blanking period
− is indicated.

さて、以上の例には以下に示す問題点がある。Now, the above example has the following problems.

■ ■、■2チャンネルのCT Dおよびゲー1〜を駆
動するため、チップのビン数が多い。
■ ■, ■ The number of chip bins is large because it drives two channels of CT D and G1~.

■ 第1図においてゲート5と5′のしきい電圧のばら
つきを補正するため、ブルーミング抑圧回路10′から
外部電荷を一度、垂直信号線4へ移し、その後、再びゲ
ート10′を通して外部に電荷を掃き出す操作が必要で
ある。
■ In FIG. 1, in order to correct variations in the threshold voltages of gates 5 and 5', external charges are transferred from the blooming suppression circuit 10' to the vertical signal line 4, and then the charges are transferred to the outside through the gates 10' again. A sweeping operation is required.

■ したがって、欲しい信号電荷をCTD■や■に移送
する時間が短かくなる。
(2) Therefore, the time required to transfer the desired signal charge to the CTD (2) and (3) is shortened.

■ 両CTDの出カフ、7′の利得が異なるので雑、音
が発生する。
■ Since the gains of the output cuffs and 7' of both CTDs are different, noise and noise are generated.

本発明は以上の問題点を解決して、固体撮像装置の性能
を向上させるものである。
The present invention solves the above problems and improves the performance of solid-state imaging devices.

第3図に本発明の実施例を示す。この実施例の特長は、
水平レジスタとしてのCTD8が、たとえば第4図に示
した断面構造を有する3相駆動CTD (特許N〆’2
8711 )である事である。
FIG. 3 shows an embodiment of the present invention. The features of this example are:
The CTD 8 as a horizontal register is, for example, a three-phase drive CTD (Patent N〆'2) having the cross-sectional structure shown in FIG.
8711).

第4図のCTDの断面図(A)において、41は第1の
電極材料、42は第2の電極である。46は酸化膜、4
3は例えばll形Si層、44は43とは逆型のP形S
1である。45は、第1電極41の間にボロンなどの不
純物をイオン打ち込みした層である。このCTDの特長
は、第1の電極と第2の電極を1つずつ接続したものを
一組として、3相パルス(B)のうちの1つのパルスを
印加するものである。したがって、各相のパルスに対応
する領域、例えば第4図中■の領域を考えると、チャネ
ル43の内のポテンシャルが不均一となっている。
In the cross-sectional view (A) of the CTD in FIG. 4, 41 is the first electrode material, and 42 is the second electrode. 46 is an oxide film, 4
3 is, for example, an ll-type Si layer, and 44 is a P-type S layer, which is the opposite type to 43.
It is 1. 45 is a layer in which impurities such as boron are ion-implanted between the first electrodes 41; The feature of this CTD is that one of the three-phase pulses (B) is applied to a pair of first and second electrodes connected to each other. Therefore, considering the region corresponding to the pulse of each phase, for example, the region 3 in FIG. 4, the potential within the channel 43 is non-uniform.

さて、第3図に話を戻す。第3図のよっにCTDとして
3相のレジスタを用いると、3相のうちの2つの相に対
応する箇所に情報を蓄積する事が出来。したがって、2
画素(図中■と■)からの2つの信号を−っのCT D
 8にストアする事が出来る。この実施例においては水
平ブランキング期間(1−IBL)の動作は次のように
なる。
Now, let's return to Figure 3. If a three-phase register is used as a CTD as shown in FIG. 3, information can be stored in locations corresponding to two of the three phases. Therefore, 2
CT D of two signals from pixels (■ and ■ in the figure)
8 can be stored. In this embodiment, the operation during the horizontal blanking period (1-IBL) is as follows.

■ 水平ブランキング期間の最初に垂直信号線4を掃除
し、信号ではない余分な電荷をゲートlOを通して外部
へ掃き出す。
■ At the beginning of the horizontal blanking period, the vertical signal line 4 is cleaned and excess non-signal charges are swept out through the gate IO.

■ 画素■およびその横方向−行分の信号電荷をCTD
8に読み込む。
■ CTD the signal charge of the pixel ■ and its horizontal direction - rows.
Load into 8.

■ CTDを1相分だけシフトする。■ Shift CTD by one phase.

■ 次いで画素■に該轟する一行分の信号電荷をCTD
8に読み込む。
■ Next, the signal charge for one row that resounds in the pixel ■ is CTD
Load into 8.

水平走査期間はゲート5,6を。ffL、て、CTDを
駆動し、信号を順次読み出す。
Gates 5 and 6 are used during the horizontal scanning period. ffL drives the CTD and sequentially reads out the signals.

このようにすれば、従来の実施例で同居であった点を解
決する事が出来、本発明適用により固体撮像装置の性能
の著しい向上を期待する事が出来る。
In this way, it is possible to solve the problems that existed in the conventional embodiments, and it is possible to expect a significant improvement in the performance of solid-state imaging devices by applying the present invention.

第5図には本発明の他の実施例を示す。本装置は呼び水
転送方式の撮像素子(S 、 Terakava et
al ; I E E E 、Electron De
vice Letter。
FIG. 5 shows another embodiment of the invention. This device uses a priming transfer type image sensor (S, Terakava et al.
al; IEEE, Electron De
vice Letter.

No、5. 1980)である。この場合でもCTDを
3相駆動のレジスタとする事により、2画素の信号を同
時に読み出して、高解像度の画像を得る事が出来る。
No, 5. 1980). Even in this case, by using the CTD as a three-phase drive register, signals from two pixels can be read out simultaneously to obtain a high-resolution image.

なお、第3図、第5図の実施例において、CTD8を2
相駆動、もしくは4相駆動のレジスタにして、且つ、水
平画素数の2倍の段数を有するように形成すれば、3相
駆動CTDを用いる場合に比べると、より微細加工技術
が要求されるが、一本のレジスタで2画素の信号を読み
出す事が可能である。
In addition, in the embodiments shown in FIGS. 3 and 5, CTD8 is set to 2.
If a phase drive or four-phase drive register is used and the number of stages is twice the number of horizontal pixels, more microfabrication technology will be required than when using a three-phase drive CTD. , it is possible to read the signals of two pixels with one register.

第6図の実施例では、3相C’r’D8.8’ を上下
に設けである。この時、図中■、■で示した画素の情報
を読む前に、余分な雑音電荷を上。
In the embodiment shown in FIG. 6, three phases C'r'D8.8' are provided above and below. At this time, before reading the information of the pixels indicated by ■ and ■ in the figure, remove the excess noise charge.

下のCTD8,8’あるいは一方のCTDに読み出す。Read out to lower CTD 8, 8' or one CTD.

このようにすれば、2画素の信号■。If you do this, you will get a 2-pixel signal ■.

■と雑音電荷■を読み出し、最後に雑音電荷■のみを外
部へ掃き出す事が出来る。
It is possible to read out the noise charge ■ and the noise charge ■, and finally sweep out only the noise charge ■ to the outside.

第7図の実施例では、4相CTI’)8を一つだけ設け
て、それぞれ、雑音電荷■と2画素の信号■、■を読み
出すものである。
In the embodiment shown in FIG. 7, only one four-phase CTI') 8 is provided to read out the noise charge (2) and the signals (2) and (2) of the two pixels, respectively.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はCTDレジスタ読み出し方式によるMO3型撮
像装置の構成を示す図、第2図は第1図における駆動パ
ルス(■チャンネル分)を示す図、第3図は本発明の実
施例を示す図、第4図は3相駆動CTDの構造(A)と
駆動パルスCB)を示す図、第5図、第6図、第7図は
本発明の他の実施例を示す図である。 1 ・ホ1−ダイオード、2・・垂直スイッチ(絶縁グ
ー1〜型電界効果トランジスタ等)、3・・・垂直走査
回路、4・・・垂直信号出力線、5,6・・・転送ゲー
ト(絶縁グー1〜型電界効果1−ランジスタ等)、8・
・・CTD、10・ リセソ1〜ゲー1〜(絶縁グー1
〜型電界効果トランジスタ等)。 第 5 図 8 第 6 図
Fig. 1 is a diagram showing the configuration of an MO3 type imaging device using the CTD register readout method, Fig. 2 is a diagram showing the drive pulse (for channel ■) in Fig. 1, and Fig. 3 is a diagram showing an embodiment of the present invention. , FIG. 4 is a diagram showing the structure (A) of a three-phase drive CTD and drive pulse CB), and FIGS. 5, 6, and 7 are diagrams showing other embodiments of the present invention. 1 ・Ho 1 diode, 2 ・Vertical switch (insulated G1~ type field effect transistor, etc.), 3 ・Vertical scanning circuit, 4 ・Vertical signal output line, 5, 6 ・Transfer gate ( Insulating goo 1 ~ type field effect 1 - transistor etc.), 8.
・・CTD, 10・ Recesso 1 ~ Game 1 ~ (Insulation Goo 1
~ type field effect transistor, etc.). Figure 5 Figure 8 Figure 6

Claims (1)

【特許請求の範囲】 ■、 水平ブランキング期間に垂直信号線の擬似信号を
読み出し、その後、垂直信号線の信号を水平レジスタで
ある電荷転送素子に読み出し、水平走査期間中は上記電
荷転送素子を駆動して信号読み出しを行なう固体撮像装
置において、上記水平レジスタである電荷転送素子を3
和駆動する事を特徴とする固体撮像装置。 2、特許請求の範囲第1項において、上記水平レジスタ
である電荷転送素子は2相駆動され、且つ、水平画素数
の2倍の段数を有する事を特徴とする固体撮像装置。 3、 特許請求の範囲第1項において、2ライン同時読
み出しを行ない、且つ、上記3相分の電荷転送素子の2
つの電極に信号を蓄積し、移送し、信号読み出しを行な
う事を特徴とする固体撮像装置。
[Claims] ■. During the horizontal blanking period, the pseudo signal on the vertical signal line is read out, and then the signal on the vertical signal line is read out to a charge transfer element, which is a horizontal register, and during the horizontal scanning period, the charge transfer element is switched off. In a solid-state imaging device that is driven to read out signals, the charge transfer element, which is the horizontal register, is
A solid-state imaging device characterized by sum drive. 2. The solid-state imaging device according to claim 1, wherein the charge transfer element serving as the horizontal register is driven in two phases and has twice the number of stages as the number of horizontal pixels. 3. In claim 1, simultaneous reading of two lines is performed, and two of the charge transfer elements for the three phases are read out simultaneously.
A solid-state imaging device that stores signals in two electrodes, transfers them, and reads out the signals.
JP59257530A 1984-12-07 1984-12-07 Solid-state image pickup device Pending JPS60137178A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59257530A JPS60137178A (en) 1984-12-07 1984-12-07 Solid-state image pickup device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59257530A JPS60137178A (en) 1984-12-07 1984-12-07 Solid-state image pickup device

Publications (1)

Publication Number Publication Date
JPS60137178A true JPS60137178A (en) 1985-07-20

Family

ID=17307570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59257530A Pending JPS60137178A (en) 1984-12-07 1984-12-07 Solid-state image pickup device

Country Status (1)

Country Link
JP (1) JPS60137178A (en)

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