JPH0263277A - Charge transfer pickup element and its drive method - Google Patents

Abstract

PURPOSE:To attain two kinds of noninterlace and interlace operations by forming N sets of transfer electrodes (M is an integer being 3 or over) corresponding to each photoelectric conversion element to a vertical register and connecting transfer electrodes at an interval of (2N-1) electrodes in common. CONSTITUTION:For example, three transfer electrodes corresponding to number of photo diodes 101 are formed to the vertical register 103. Moreover, the electrodes for a transfer gate 102 are in common use with the transfer electrodes of the vertical register. The transfer electrodes are connected in common at an interval of 6 electrodes in the unit of repetition of two photo diodes and provided with 6 terminals A-F to which a drive pulse is impressed. Thus, the operation of two kinds, interlace and noninterlace is realized in one and the same image pickup element.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a charge transfer image pickup device, and particularly to an interline transfer type charge transfer image pickup device and a method for driving the same.

[Conventional technology]

FIG. 5 shows an example of an interline transfer type charge transfer image sensor (Japanese Patent Application No. 55-51271 and Japanese Patent Application No. 55-130).
517), which includes a photoelectric conversion element (hereinafter referred to as a photodiode) 501, a transfer gate 502, a vertical register 503, a horizontal register 504, and a charge detection section 505.

FIGS. 6(a) to 6(c) show an example of driving the ink-lace operation in the field accumulation mode in the image sensor shown in FIG. 5 (publication No. 60-46594).

The example in the figure assumes a four-phase drive vertical register in which one stage is composed of four electrodes corresponding to two adjacent photodiodes, and the transfer gate electrode is connected to the transfer electrodes φv1 and φv1 of the vertical register. It is assumed that φν3 also serves as the function.

FIG. 6(a) shows the driving pulse waveform applied to each transfer electrode of φv1 to φ■4, and FIG. 6(b) and (c) show the driving pulse waveform applied to each transfer electrode of φv1 to φ
FIG. 3 is a schematic diagram showing the operation of the element according to the drive pulse of a).

In the first field, the period during the vertical blanking period ■
By setting φVl to the ■H level, the signal charges accumulated in the photodiodes 601 and 603 are read out to the corresponding vertical registers. Next, in period (3), the signal charges are vertically transferred by 1/2 stage and accumulated under the electrodes in φV21φv3. After that, by setting φvS to ■H level in period ■, the signal charges accumulated in the photodiodes 602 and 604 are read out, and the signal charges stored in the photodiodes 602 and 604 are read out.
1,603 signal charges, and outputs the mixed charges as signals of unit pixels 607, 608 of the first field.

In addition, in the second field, the signal charge accumulated in the photodiode 602 is read out to the corresponding vertical register by setting φv3 to the level ■8 in the period ■.
1/2 step vertical transfer in period ■φv4. Accumulates under the φv1 electrode. Next, in period (3), by setting φv1 to VH level, the signal charge accumulated in the photodiode 603 is read out, mixed with the signal charge, and output as a signal of the unit pixel 609 of the second field. In the manner described above, 2:1 interlace operation in field storage mode can be realized.

FIGS. 7(a) and 7(b) show an example in which the image sensor shown in FIG. 5 is subjected to a sequential scanning operation (hereinafter referred to as non-interlaced operation). In the example shown in the figure, we assume a three-phase drive vertical register in which one stage is composed of three electrodes corresponding to each photodiode, and the transfer gate electrode is also the transfer electrode φv2 of the vertical register. shall be.

FIG. 7(a) is a schematic diagram showing the driving pulse waveform applied to each transfer electrode of φV21φv3 during one frame period, and FIG. 7(b) is a schematic diagram showing the operation of the element by the driving pulse of FIG. 7(a). be.

By setting φ9□ to VH level during the period ■ during the vertical blanking period, the photodiodes 701 to 703
All the signal charges accumulated in the pixel are simultaneously read out to the corresponding vertical registers, and these charges are independently outputted as a unit pixel signal.

[Problem to be solved by the invention]

In the examples shown in FIGS. 6(a) to 6(c), 2:1 interlaced operation compatible with the standard television system is possible.
Since one stage of vertical register transfer electrodes is formed corresponding to two adjacent photodiodes, it is impossible to simultaneously and independently output signal charges from all photodiodes.

On the other hand, in the examples shown in FIGS. 7(a) and 7(b), one stage of vertical register transfer electrodes is formed corresponding to each photodiode, and the signal charges of all photodiodes can be output simultaneously and independently. , it is possible to obtain high-quality reproduced images due to non-interlaced operation. However, it is impossible to perform an interlace operation as shown in FIG. 6 in which the signal charges of two adjacent photodiodes are mixed in a vertical register and output as a signal of a unit pixel.

As described above, the conventional image pickup device has the drawback that it is impossible to perform interlace operation driving and non-interlace operation driving with the same element.

An object of the present invention is to provide a new charge transfer image sensor and a method for driving the same, which eliminates such conventional drawbacks.

[Means for Solving the Problems] According to the present invention, a plurality of photoelectric conversion elements are arranged two-dimensionally on a semiconductor substrate, and a vertical transducer that transfers signal charges accumulated in the photoelectric conversion elements in parallel. It includes at least a register and a transfer gate that transfers charges from each of the photoelectric conversion elements to the vertical register, and the vertical register has N transfer gates (N is an integer of 3 or more) corresponding to each of the photoelectric conversion elements. A charge transfer image sensor is obtained in which electrodes are formed and every (2N-1) transfer electrodes are commonly connected.

Further, according to the present invention, in the above-described method for driving a charge transfer image sensor, a drive pulse in which one stage is composed of N electrodes corresponding to one photoelectric conversion element is applied to the transfer electrodes of the vertical register. In the method for driving a charge transfer image sensor and the method for driving the charge transfer image sensor described above, a drive pulse in which one stage is composed of 2N electrodes corresponding to two vertically adjacent photoelectric conversion elements is set in a vertical register. A method for driving a charge transfer image sensor is obtained, which is characterized in that a voltage is applied to the transfer electrode of the charge transfer image sensor.

[Effect]

In the present invention, N (
N is an integer of 3 or more) transfer electrodes are formed, and (2N
-1) Since every other transfer electrode is provided with a vertical register connected in common, a drive pulse forming one stage corresponding to one photodiode, or one driving pulse corresponding to two photodiodes is provided. By applying drive pulses forming stages, it is possible to realize two types of operation, interlaced and non-interlaced, in the same image sensor.

〔Example〕

FIG. 1 is a schematic diagram showing an embodiment of the present invention.

In the vertical register 103 of this device, three transfer electrodes are formed corresponding to each photodiode 101. Further, the electrode of the transfer gate 102 also serves as the transfer electrode of the vertical register. Transfer electrode is photodiode 2
Each unit is a repeating unit, and every fifth unit is commonly connected.
It has six terminals A to F for applying driving pulses.

FIG. 2 is a schematic diagram showing an embodiment of a driving method for causing the image sensor shown in FIG. 1 to operate in a non-interlaced manner.

In this embodiment, φV1 is connected to terminals A and D in FIG.
, B and E are applied with a drive pulse of φ9□, and drive pulses of φsj3 are applied to C and F. That is, it functions as a three-phase drive vertical register in which one stage is composed of three electrodes corresponding to each photodiode, and its operation is the same as the example shown in FIG.

FIG. 3 shows an example of driving the image sensor shown in FIG. 1 in interlace operation in field accumulation mode.

In the example shown in the figure, φV1 is connected to terminals A and B in FIG.
, C and D, and a drive pulse of φV3 is applied to E and F. That is, it functions as a three-phase drive vertical register in which one stage is composed of three electrodes corresponding to two photodiodes.

FIGS. 3(a) and (b) are schematic diagrams showing the operation of the element during the vertical blanking period of the first field and the second field, respectively, and FIGS. 3(C) and (d) represent the driving pulse waveforms. FIG.

In the first field, the signal charges accumulated in the photodiodes 301 and 303 are read out to the corresponding vertical register by setting φVl to the VH level during the period (3).

Next, in the period ■■, the signal charge is vertically transferred to 2/3 stages and φ
Accumulates under the V3 electrode. After that, in period ■, φV3 is set to VH
By leveling the photodiodes 302, 30
The signal charges accumulated in the photodiodes 301 and 303 are read out, and the signal charges of the respective photodiodes 301 and 303 are mixed, and the mixed charges are transferred to the unit pixels 307 and 308 of the first field.
output as a signal. In addition, in the second field, the signal charge accumulated in the photodiode 302 is read out by setting φV3 to the ■H level in the period ■,
During the period ■, the data is vertically transferred by 1/3 stage and accumulated under the φVl electrode.

Next, in period (■), φ9 is set to ■H level, thereby reading out the signal charge accumulated in the photodiode 303, mixing it with the signal charge, and outputting it as a signal of the unit pixel 309 of the second field. In this manner, a 2:1 interlaced operation in field storage mode can be realized, similar to the conventional example shown in FIG.

FIG. 4 shows an example of driving the image sensor shown in FIG. 1 in an interlace operation in a field accumulation mode different from that shown in FIG.
Drive pulses of φVl to φv6 are applied to. That is,
It functions as a six-phase drive vertical register in which one stage is composed of six electrodes corresponding to two photodiodes.

FIGS. 4(a) and (b) are schematic diagrams showing the operation of the element during the vertical blanking period of the first field and the second field, respectively, and FIGS. 4(C) and (d) represent the drive pulse waveforms. FIG.

In a charge transfer element in which the transfer electrode has only an accumulation region and no barrier region, there is a period during which the transfer electrodes for two phases are off in order to separate adjacent signal charges during charge transfer, and the maximum signal charge amount is restricted in this state.

In the example shown in Figure 3, one photodiode corresponds to two photodiodes.
Since in-phase pulses are applied every two electrodes to the six electrodes that make up the stage, assuming that all electrode lengths are the same, the maximum signal can be achieved with the amount of charge that can be accumulated in 2/6 electrodes per stage. Amount is specified.

On the other hand, in the example shown in Figure 4, pulses of different phases are applied to six electrodes that constitute one stage corresponding to two photodiodes, and can be accumulated in 4/6 electrodes per stage. Since the maximum signal amount is defined by the amount of charge, it is twice as large as the example shown in FIG.

In the first field, the signal charges accumulated in the photodiodes 401 and 403 are read out to the corresponding vertical registers by setting φV2 to the ■H level during the period ■ when φv1 to φv4 are in the on state.

Next, in period ■, the signal charge is vertically transferred by 1/2 stage and φv
Accumulates under the 4 to φv1 electrodes. After that, φV5 in period ■
By setting the voltage to VH level, the photodiode 402
, 404 are read out and mixed with the signal charges of the photodiodes 401, 403, respectively, and the mixed charges are transferred to the unit pixels 407, 404 of the first field.
Output as a 408 signal.

In addition, in the second field, the signal charges accumulated in the photodiodes 402 and 404 are read out by setting φV to the ■□ level during the period ■ when φV4 to φVl are in the on state, and the signal charges accumulated in the photodiodes 402 and 404 are read out in the period ■. 2-stage vertical transfer φ
Accumulates under the v1 to φv4 electrodes. Next, in period (3), by setting φV1 to the VH level, the signal charge accumulated in the photodiode 403 is read out, mixed with the signal charge, and output as a signal of the unit pixel 409 of the second field.

As described above, in this embodiment as well, 2:1 interlace operation in the field accumulation mode can be realized, similar to the conventional example shown in FIG.

In addition, in the embodiment described here, an example was described in which three electrodes are formed for one photodiode, but it is clear that the present invention can be applied to cases in which four or more electrodes are formed. .

In addition, 2 according to the field accumulation mode described in the embodiment:
Not only 1:1 interlace operation but also 2:1 interlace operation with frame accumulation mode is possible.

Further, although this embodiment shows an example in which the transfer electrode of the vertical register also functions as the transfer gate electrode, the present invention can be applied even if the transfer gate electrode has an independent configuration.

〔Effect of the invention〕

As explained above, according to the present invention, N transfer electrodes (N is an integer of 3 or more) are formed corresponding to one photodiode, and every (2N-1) transfer electrodes are formed. In a charge transfer image sensor equipped with commonly connected vertical registers, non-interlaced operation can be achieved by applying a drive pulse that constitutes one stage corresponding to one photodiode, and it can also be applied to two photodiodes. Interlace operation can be realized by applying driving pulses constituting one stage. In other words, non-interlaced and interlaced images are recorded on the same image sensor.
This has the effect of enabling different types of operations.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of an interline transfer type charge transfer image sensor according to the present invention, FIG. 2 is a schematic diagram showing non-interlaced operation according to the present invention, and FIGS. 3(a) to (d) are field accumulation diagrams according to the present invention. Schematic diagrams and waveform diagrams showing interlacing operation depending on the mode, FIGS.
The figure is a schematic diagram of a conventional interline transfer type charge transfer image sensor, Figures 6 (a) to (c) are waveform diagrams and schematic diagrams showing interlace operation in field accumulation mode in the conventional element, and Figure 7 (a). . (b) is a waveform diagram and a schematic diagram showing non-interlace operation in a conventional element. 101.201~204,301~304°401~4
04,501,601-604,701-703...
Photodiode, 102,205.305,405,
502,605,704...Transfer gate, 1
03,206,306°406.503,606,70
5... Vertical register, 307, 308. 407.
408. 607. 608... Unit pixel of first field, 309.409609... Unit pixel of second field, 504... Horizontal register, 505... Charge detection section.

Claims (3)

[Claims] (1) A plurality of photoelectric conversion elements two-dimensionally arranged on a semiconductor substrate, a vertical register that transfers signal charges accumulated in the photoelectric conversion elements in parallel, and from each of the photoelectric conversion elements to the vertical register. The vertical register includes at least a transfer gate for transferring charges, and the vertical register has N (N is an integer of 3 or more) transfer electrodes corresponding to each of the photoelectric conversion elements, and (2N-1) transfer electrodes. A charge transfer image sensor characterized in that alternate transfer electrodes are commonly connected. (2) Driving the charge transfer image sensor according to claim (1), characterized in that a drive pulse in which one stage is composed of N electrodes corresponding to one photoelectric conversion element is applied to the transfer electrode of the vertical register. Method. (3) Claim (1) characterized in that a drive pulse in which one stage is formed by 2N electrodes corresponding to two vertically adjacent photoelectric conversion elements is applied to the transfer electrode of the vertical register.
A method of driving the charge transfer image sensor described above.