JPS60136365A - Semiconductor device - Google Patents

Abstract

PURPOSE:To miniaturize the chip size by means of reducing the current required for writing in by a method wherein the end of an emitter opening and the edge of a contact hole are preliminarity formed a little bit shifted manner so that the contact hole may slightly jut outward an emitter opening not to be perfectly overlapped. CONSTITUTION:At least two layers of e.g. the first and the second insulating films are formed on a diffusion layer while the openings for electrode contact to be formed in the first and the second insulating films are respectively formed slenderly in the two directions perpendicular to each other with the end of one opening jutting outward the end of the other opening. For example, in case of a base open type transistor to be a memory cell in a bipolar type PROM, a slender opening 5a is formed in the longitudinal direction of a base region 8 opposing to an insulating film 5 while a slender contact hole 12a is formed in the lateral direction perpendicular to the emitter opening 5a opposing to an interlayer insulating film 11 so that the edge of the contact hole 12a may be prevented from entering inside the end of the emitter opening 5a.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is effective when applied to semiconductor technology and also to the manufacturing process of semiconductor devices. Regarding technology.

[Background Art] In semiconductor memories such as bipolar FROMs (read-only memories), as the capacity increases, there is a demand for reductions in the size of memory cells. Conventionally, the format of memory cells in bipolar FROM is as follows:
There are fuse-cutting types and diode junction-breaking types using open-base bipolar transistors (for example, "Integrated Circuit Application Handbook" published by Chokoku Shoten Co., Ltd. on June 30, 1981). P.

371-P, 379).

Among these, in the junction destruction type FROM, writing is performed by destroying the PN junction between the base and emitter of the open-base bipolar transistors that constitute a pair of diodes connected back to back.
Sign.

In this case, it is known that the smaller the area of the emitter region, the smaller the required write current. Therefore, by reducing the emitter area, it is possible to reduce the size of the memory cell and the area occupied by the peripheral circuits.

In other words, the larger the write current, the larger the current needs to flow through the write circuit and other peripheral circuits, so the dimensions of the elements that make up the peripheral circuit must be made larger.However, by reducing the emitter area, the required write current can be reduced. The smaller the number, the smaller the area occupied by the peripheral circuits and the smaller the chip size.

Therefore, the present inventor developed a structure as shown in FIG. 1 as a structure of an open base transistor constituting a junction destruction type memory cell.

That is, the separation region between the base diffusion layer 8 and the N-type diffusion layer 7, which is formed to be continuous with the N+ buried layer 2 in the substrate 1 and serves as a collector extraction port, is eliminated, and the emitter diffusion layer 9 Both sides of the transistor are regulated by an isolation oxide film (LOCOS) surrounding the transistor. By adopting a so-called walled emitter structure,
The idea is to reduce the area of memory cells (transistors).

However, in the structure shown in Figure 1, if the emitter region is formed using conventional lithography technology, the processing accuracy of the current lithography technology (the length of the emitter region and the width in the horizontal direction of the drawing) (1.5-2μm)
cannot be smaller than the dimensions determined by Therefore, with conventional techniques, it has not been possible to realize an emitter diffusion layer of 1.5 μm or less.

[Object of the Invention] An object of the present invention is to provide a semiconductor technology that exhibits remarkable effects compared to the prior art.

Another object of the present invention is to reduce the effective emitter area to less than the area determined by the processing accuracy of phosphorography technology when applied to, for example, a junction-destructive bipolar FROM. The purpose is to reduce the write current that is passed during the process, thereby reducing the chip size.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Outline of the Invention] Representative inventions disclosed in this application will be summarized as follows.

In other words, the present invention is based on the fact that mask alignment accuracy is higher than processing accuracy in current lamination technology, and that the effective area of the emitter is determined by the size of the emitter window, that is, the emitter region (diffusion layer) and emitter electrode ( Focusing on the fact that this is determined by the area of overlap with the aluminum electrode (aluminum electrode), the edge of the emitter opening and the edge of the contact hole are aligned in advance so that the contact hole does not completely overlap the emitter opening but protrudes slightly outward. By staggered formation, the overlapping area between the emitter and the electrode is reduced,
This achieves the above objective of making it possible to suppress the effective area of the emitter to less than the processing precision of lithography technology, thereby reducing the required write current and reducing the chip size. .

The present invention will be specifically explained below using the drawings.

[Embodiment] FIGS. 2 to 4 show an embodiment in which the present invention is applied to an open-base transistor serving as a memory cell in a bipolar FROM, in the order of manufacturing steps.

In this embodiment, first, an oxide film is formed on a semiconductor substrate 1 made of P-type silicon, and then a hole for a buried diffusion pattern is formed at an appropriate position in the oxide film. Using this oxide film as a mask, an N-type An N+ buried layer 2 is partially formed by thermally diffusing impurities. Then, after removing the oxide film, a P+ type diffusion layer 3 for a channel stopper is formed, and an N- type epitaxial layer 4 is grown on it by vapor phase growth, and an oxide film (SiOz) 5 and a nitride layer are formed on the surface. A film (Si3N4) is formed. Thereafter, the oxide film 5 and the nitride film are partially removed by photoetching, and using this as a mask, a relatively thick oxide film 6 for isolation is formed in that part, and then the nitride film is removed. Then, masking again with a nitride film or the like, selective thermal diffusion treatment of N-type impurities is performed on the part that will become the pull-up port of the collector region to form an N+ diffusion region 7, and selectively on the N- type epitaxial layer 4. A P-type base region 8 is formed by implanting and thermally diffusing P-type impurities (FIG. 2).

In this case, the N+ diffusion region 7 which becomes the collector outlet
An isolation oxide film, which is formed in a normal bipolar transistor, is not formed between the base region 8 and the base region 8. This reduces the overall length of the memory cell.

Next to the state shown in FIG. 2, an emitter opening 5a is formed in the oxide film 5 above the base region 8 by photoetching. Then, polysilicon (polycrystalline silicon) is deposited over the entire substrate by the CVD method, and an N-type impurity such as arsenic is ion-implanted into the polysilicon, followed by heat treatment. Then, an emitter N-type diffusion layer 9 is formed by impurity diffusion from the polysilicon. Thereafter, unnecessary portions of the polysilicon layer are removed by photoetching, and a polysilicon electrode 10 is formed on the emitter N-type diffusion layer 9, as shown in FIG.

Next, an interlayer insulating film 11 such as a P, S G film (phosphorus silicate glass film) is deposited on the polysilicon electrode 10, and then emitter and collector regions are formed with respect to this glabellar insulating film 11. contact hole 12a to
12b is formed. Thereafter, aluminum is deposited on the glabella insulating film 11, and wiring, emitter electrode 13a, and collector electrode 13b are formed by photoetching, and then a passivation film 14 is deposited thereon by CVD.
The completed state shown in FIG.

Therefore, in this embodiment, as shown in FIG. 5, an elongated emitter opening 5a is formed in the insulating film 5 along the length direction (left direction in the drawing) of the base region 8, and the emitter opening 5a is formed in the insulating film 5. An elongated contact hole 12a is formed in the interlayer insulating film 11 in the width direction (vertical direction in the drawing) perpendicular to the contact hole 5a.
form against. Furthermore, the etching is performed while positioning so that the edge of the contact hole 12a does not enter inside the end of the emitter opening 5a.

With current phosphorography technology, mask positioning accuracy is higher than processing accuracy.

The size of the emitter window (the shaded area in the figure) in which the emitter opening 5a and the contact hole 12a overlap can be made smaller than the processing dimension of the lithography technique.

For example, if lithography technology with a processing size of 1.5 μm is used in the process, the actual mask positioning accuracy can be approximately 0.5 μm.
a and the width 11+12 of each of the contact hole 12a
is 1.5 μm, and if positioning is performed so that the width 1o of the overlapping part is 0°7 ± 0.25 μm considering the alignment margin of the mask, it will be 1.5X (0.7 ± 0.25) μm.
However, in the above case, the width of the contact hole 12a is 1.5".
The size of the window does not change even if it is more than μm.

On the other hand, in the past, the size of the emitter window was determined by the size of the contact hole 12a, so 1.
When using 5μm glue lithography technology, 1.5X1.
It was not possible to form a window of 5 μm 2 or less.

Therefore, according to this embodiment, the size of the emitter window can be reduced to 1/3 to 2/3 compared to the conventional one. However, in a memory cell composed of an open-base bipolar transistor as described above, the emitter electrode 1
When a write current is applied to 3a, the current is concentrated exclusively in a part of the emitter region directly below the emitter window and flows toward the base side. Therefore, the effective area of the emitter is approximately the same size as the emitter window.

Therefore, when the size of the emitter window is smaller than the conventional one as in the above embodiment, the effective area of the emitter is reduced, and the write current destroys the PN junction between the emitter and base to write data. can be done. Furthermore, this also reduces the current flowing through the circuits surrounding the memory, making it possible to reduce the dimensions of the elements constituting one peripheral circuit, thereby reducing the area occupied and the chip size.

As a result of prototype tests, it has been found that the structure of the above-described embodiment reduces the current of about 50 mA to about 20 to 30 mA.

In the above embodiment, the reason why the contact hole 12a is made longer in the width direction is to eliminate variations in the size of the emitter window due to positional deviation in this direction.

Further, the emitter N-type diffusion layer 9 of the above embodiment is formed to have a walled emitter structure in which both sides are regulated by isolation oxide films 6.degree.6, as shown in FIG. This reduces the width of the transistor and enables higher integration of memory cells.

However, this invention has a walled emitter structure.
The present invention is not limited to transistors, but can also be applied to transistors having a normal emitter structure in which the emitter region is not restricted by the isolation oxide film 6.

Furthermore, in the above embodiment, the structure is such that the base region 8 and the collector lead-out lower part are not separated by an oxide film or the like. Of course, a separation region may also be formed.

Furthermore, in the above embodiment, the emitter opening 5a is formed long and thin along the length direction of the base region, and the contact hole 1'2a is formed long and thin along the width direction. The opening 5a is formed long and thin along the width direction of the base region, the contact hole 12a is formed long and thin along the length direction, and by slightly shifting them from each other, an emitter window smaller than the minimum processing dimension is formed. It's okay.

However, in a memory cell of the junction destruction type, the symbol A is shown in FIG.
Since the write current is likely to concentrate in the locations shown in
If the emitter opening 5a is formed to be elongated in the length direction as in the embodiment described above, the current can be concentrated more easily, and the write current can be reduced accordingly.

[Effect] In the open-base transistor that constitutes the memory cell of the junction-destructive bipolar FROM, contact 1 to
The edge of the emitter opening and the edge of the contact hole are offset from each other in advance so that the hole does not completely overlap the emitter opening but protrudes outward a little. The effective area of the emitter is reduced by forming the emitter to a size smaller than the minimum processing dimensions of the emitter, making it possible to reduce the current required for writing, thereby reducing the dimensions of the elements that make up the peripheral circuit. This has the effect of reducing the area occupied by peripheral circuits and reducing the chip size.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, isolation between elements around the transistor is provided by LOG:O5.

It may be a field oxide film or a U-groove isolation region using an isobrainer. Further, it is not necessary to provide a polysilicon electrode on the emitter.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to the field of application which is the background of the invention, a junction-destructive bipolar FROM. It can also be used as an element for redundant setting of a semiconductor memory equipped with a semiconductor memory.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an example of the configuration of a bipolar transistor in a conventional semiconductor integrated circuit. 2 to 4 are cross-sectional views showing one embodiment of the present invention applied to a bipolar integrated circuit process in the order of steps; FIG. 5 is an explanatory plan view thereof; and FIG. It is a sectional view along the BB line in . l... Semiconductor substrate, 2... N0 buried layer, 4...
...N- epitaxial layer, 5, 6... Insulating film (oxide film), 5a... Opening, 8... P-type diffusion region (base region), 9... N+ type Diffusion region (emitter region), 10... polysilicon layer, 11... absolute R film (interlayer insulating film), 12a, 12b... contact hole, 13a... emitter electrode, 14... ...
passivation film. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 6

Claims (1)

[Claims] 1. A semiconductor device in which an electrode formed on the main surface of the semiconductor substrate is brought into contact with a diffusion layer formed on the main surface of the active region with an insulating film interposed therebetween, At least first and second insulating films are formed on the diffusion layer to a thickness of 2N, and an electrode contact opening A formed in the first insulating film and a second insulating film are formed on the diffusion layer.
The electrode contact openings formed in the insulating film are formed elongately in two directions perpendicular to each other, and the end of one opening is located outside the end of the other opening. A semiconductor device characterized in that it is formed so as to 2. The semiconductor device according to claim 1, wherein the diffusion layer is an emitter region of an open-base bipolar transistor constituting a memory cell in a junction-destructive read-only semiconductor memory device. .