JPS5867062A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the area of a wiring layer connecting to a gate electrode, and to enlarge the degree of freedom on design by forming the wiring layer so as to cross transversely on a source region or a drain region. CONSTITUTION:An impurity diffusion region 1 functioning as the source region and the drain region, the gate electrode 2 of polycrystal silicon shaped onto the region 1 and the wiring layers 3 of the same polycrystal silicon are formed to a single crystal silicon substrate 4. Here, the wiring layers 3 required for connection with other elements are shaped onto the source region or the drain region at the same time as the gate electrode 2. When the width of the wiring layers 3 is L and the junction depth of the source region and the drain region is Xj, diffusion layers are also shaped under the wiring layers 3 when the relationship of L<2Xj is formed, and the source region or the drain region substantially causing no trouble is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and relates to a silicon wiring of a MOG type field effect transistor/distor having a polycrystalline silicon gate.

Conventional MOS (metal oxide semico
In a semiconductor integrated circuit using a field effect transistor (type field effect transistor), self-line technology is used for impurity diffusion in the source and drain regions, so the polycrystalline silicon wiring in the same layer as the gate electrode is Cannot cross the area. In this rounding, the wiring layer made of polycrystalline silicon in the same layer as the gate electrode is arranged so as not to cross over the diffusion layer. In order to connect to other elements, it is necessary to draw it out without crossing the diffusion layers of the source and drain regions, and then connect it to other elements.

An object of the present invention is to provide a semiconductor device without such wiring restrictions.

The present invention resides in a semiconductor device including a field effect transistor in which a wiring layer following a gate electrode is formed to cross over a source region or a drain region.

Next, the present invention will be explained in detail with reference to the drawings. J (Ml is 1) the gate electrode of the embodiment of the present invention,
FIG. 1(b) is a plan view showing portions such as a wiring layer, a source region, a drain region, etc., and FIG. 1(b) is a cross-sectional view taken along line A-A/arrow in FIG. 1(a). In these figures, a single crystal silicon substrate 4 is provided with an impurity diffusion region 1 that becomes a source region and a drain region, a gate electrode 2 made of polycrystalline silicon formed between the regions, and a polycrystalline silicon substrate made of the same polycrystalline silicon as the gate electrode. A wiring layer 3 made of crystalline silicon is formed.

Here, a wiring layer 3 made of polycrystalline silicon necessary for connection with other elements is formed on the source region or the drain region at the same time as the gate electrode 2.

If the width of this wiring layer 3 is L and the junction depth of the source region and drain region is Xj, then a diffusion layer is formed also under the wiring layer 3 if there is a relationship of L<2Xj.

Therefore, even if the wiring layer 3f is formed, a source region or a drain region with virtually no problems can be obtained.

Note that in FIG. 1(a), the wiring silicon film 5 on the surface of FIG. 1(b) is omitted.

This equivalent circuit is shown in FIG. 2, which is a plan view of the semiconductor device of the sense amplifier circuit. In these figures, a first MO8 type field effect region is formed, which is composed of a first impurity diffusion region 1 that becomes a source region and a drain region, a first gate electrode 2 above the first impurity diffusion region 1, and a first source and drain interconnection layer 11.12. A transistor, a second impurity diffusion region 1' serving as a source region and a drain region, and a second gate electrode 2 therebetween.
' and a second MO8 type field effect transistor comprising second source and drain wiring layers 11' and 12'.

In this second field effect transistor, one gate electrode wiring layer and the other source or drain wiring layer are connected through contact holes 7, 7'. The wiring layers 8, 8' are connected to other elements and the like.

As is clear from these figures, the wiring following the gate electrodes 2, 2' does not cross over the source region and the drain region 1.1'.

FIG. 4 (11) is a plan view of a semiconductor device of a sense amplifier circuit to which an embodiment of the present invention is applied. FIG. 4 (bl is a sectional view taken along the line BB' in FIG. 4 (al).

In these figures, parts similar to those in FIG. 3 are given the same reference numerals.

The difference from FIG. 2 is that wiring layers 3 made of the same polycrystalline silicon are formed across impurity diffusion regions 1 and 1'. These wiring layers 3 are connected from gate electrodes 2, 2' to source regions or drain regions of other transistors via contact holes 7', 7.

It can be seen that the configuration shown in FIG. 4 (al) has a smaller area for wiring compared to FIG. 3.

Note that the wiring layer 3 is as shown in FIG. 4(a).

It is preferable to use double wiring.

As described above, according to one aspect of the present invention, the area of the wiring layer can be reduced and the degree of freedom in design can be increased.

[Brief explanation of the drawing]

FIG. 1 (al is a plan view showing a semiconductor device according to an embodiment of the present invention, FIG. 1(b) is a cross-sectional view taken along the line A-A' of FIG. 1 (al). FIG. 2 is a sense amplifier circuit diagram, 3 is a plan view of a semiconductor device configured with the circuit shown in FIG. 2 using a conventional technique. FIG. 4(a) is a plan view of a semiconductor device configured with the circuit shown in FIG. Figure 4(b) is a cross-sectional view taken along the line B-B/arrow of Figure 4 (al). , 3... Wiring layer, 4... Single crystal silicon substrate, 5... Silicon oxide film, 6...
...Silicon oxide film, 7...Contact hole,
8...Aluminum wiring layer.轡〜IF口/flノ! A1 Ward (I:)) 8'3 Suth? Ward

Claims (2)

[Claims] (1) A semiconductor device including a field effect transistor in which a wiring layer following a gate electrode is formed to cross over a source region or a drain region. (2) The semiconductor device according to claim 11, wherein the wiring layer is made of the same material as the gate electrode.