JPS60134336A - Display control device - Google Patents

Abstract

PURPOSE:To reduce the cost of a display control device by providing a dot selecting means and plural dot buffers which can store a data of one dot corresponding one to one to the respective display units. CONSTITUTION:In case for instance, four display units 22 are used, a refresh address counter 23 divides one dot time into four in timings A1, A2, and switches an address to each divided time. As a result, picture information to be displayed on four display units 22 in one dot time is read out of a picture by one character each in time division. On a display controlling circuit 27, a dot buffer 28 which can store a data of one dot is provided as one to one to the display unit 22. Each dot buffer 28 sends out a dot data inputted from a selector 29, as a display signal in timings T1, T2, T3 and T4 of four phases from the refresh address counter 23.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a display control device that controls a plurality of display units, and particularly to a display control device that transmits dot data of a display pattern to each display unit substantially simultaneously in series. The present invention relates to a display control device.

[Background of the invention]

A conventional configuration of a display control device that controls a plurality of display units will be explained with reference to FIG. In this figure, 4
is a screen memory in which display information for each display unit (CRT unit) 11 is stored. Reference numeral 2 denotes a refresh address counter. By inputting the addresses generated here to the screen memory 4 via the address selector 3, screen information is sequentially read out from the screen memory 4. Assuming that the number of connectable display units 11 is N, screen information for N display units is sequentially read character by character in a time-sharing manner within the character time of the display units 1101. An address for writing new information into the screen memory 4 is given from the address path 1 via the address selector 4.

Reference numeral 5 denotes a pattern generation unit, which generates a display pattern (character code) corresponding to the screen information (character code) read from the screen memory 4.
Outputs one raster worth of parallel dotbacks of the character pattern). This parallel dot data is input to the display signal control circuit 8.

This display signal control circuit 8 includes a combination of a pattern buffer 9 and a shift register 10 for each display unit) 11.
provided for each. The parallel dot data for each display unit 11 outputted from the pattern generator 5 is held in the pattern buffer 9 corresponding to that display unit, is converted from parallel to serial by the shift register 10 paired with it, and is converted dot by dot. The signal is sent to the corresponding display unit 11 as a display signal.

As described above, conventionally, it is necessary to provide as many pattern buffers 9 capable of holding parallel dot data and shift registers 1O for converting parallel dot data into serial data as many as there are display units 11 to be connected. Therefore, when the number of connected display units increases, the display signal control circuit 8 needs to be large-scaled, and the display control device becomes expensive.

[Purpose of the invention]

An object of the present invention is to provide a display control device that reduces the amount of means for converting parallel dot data into serial data and sending it to a display unit.

[Summary of the invention]

The display control device according to the present invention is provided with a dot selection means and a plurality of dot buffers each capable of storing data of one dot in one-to-one correspondence with each display unit. Parallel dot data in raster units for each display unit is sequentially generated from the pattern generation means in a time division manner within one dot time, and one dot data to be displayed by the dot selection means is generated from each of the parallel dot data. is selected. The selected data is stored in the corresponding dot buffer and sent to each corresponding display unit.

Embodiment of the Invention] FIG. 2 is a block diagram showing an embodiment of the invention, and FIG. 3 is a timing diagram for explaining its operation.

In FIG. 1, numeral 21 is a screen memory, and display information for each display unit (CRT unit) 22 is stored here. 23 is a refresh address counter, and the address generated here is sent to the address selector 24.
The screen information is sequentially read out from the screen memory 21 by inputting the screen information to the screen memory 21 via the screen memory 21 . If the number of connectable display units 22 is N, display unit 2
Within one dot time of 2, screen information for N display units is sequentially read character by character in a time-division manner.

In this embodiment, since there are four display units 22, the refresh address counter 23 has timings Al,
One dot time is divided into four by A2, and the address is switched at each divided time. As a result, in 1 dot time, 4
Screen information to be displayed on the display unit 22 of the stand is read out character by character from the screen memory 21 in a time-sharing manner.

An address for loading new information into the screen memory 21 is given from the address bus 25 via the address selector 24.

Reference numeral 26 denotes a pattern generation section, which outputs parallel dot data for one raster of a display pattern (character pattern) corresponding to the screen information (character code) read out from the screen memory 21. This parallel dot data is transmitted to the display signal control circuit 2.
7 is input.

This display signal control circuit 27 is provided with dot bags 728 each capable of storing one dot of data, or in a one-to-one correspondence with each display unit 22. In this embodiment, four dot buffers 28 are provided.

The display signal control circuit 27 further includes a selector 29 for selecting one dot of data to be displayed from the parallel dot data.
and a counter 30 for controlling the selection of this selector 29.
is provided.

In this embodiment, as shown in FIG. 3, since the number of dots per raster of the display pattern (character pattern) 31 is 5 (this is just an example), the counter 30 is set to 5. A forward counter is used and is counted up at timing A2. In one character time, the same display pattern for each display unit 22 is repeated 5 times and output from the pattern generator 26, and the value of the counter 30 is 0.1.
．． 2.3.4. In other words, counter 30
The value indicates the number of characters that should be displayed.

The selector 29 selects one dot data corresponding to the dot number counted by the counter 30 from the parallel dot data for each display unit 11 outputted from the pattern generating section 5, and inputs it to each dot buffer 28. That is, when parallel data is first input to each display unit 22,
Select the first dot data, and when inputting the second dot data, press 2.
Similarly, when inputting for the fifth time, the fifth dot data is selected.

Each dot buffer 28 receives dot data input from the selector 29 at four-phase timings TI, T2 . T3. T4
, respectively, and temporarily hold them. These timings T1 to T4- have a time relationship with timing A1 as shown in FIG. 3. Therefore, dot data for each display unit 22 is held in the corresponding dot buffer 28 and sent to the cough pad display unit 22 as a display signal.

Note that in FIG. 2, VD1 to VD4 are dot data sent to each display unit 22.

It is clear that the display signal control circuit 27 of this embodiment has far fewer components than the display control circuit 8 shown in FIG. This effect of reducing the amount becomes even more pronounced as the number of connected display units increases.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the amount of means for serially sending parallel dot data one dot at a time to the display unit can be significantly reduced compared to the conventional method, and the cost of the display control device can be reduced. be able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional display control device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a timing diagram. 21...Screen memory, 22...Display unit, 23
...Refresh address counter, 24...Address selector, 26...Pattern generation section, 27...
Display signal control circuit, 28... dot buffer, 29.
...Selector, 30...Counter. Figure 3

Claims (1)

[Claims] (1) A display control device that serially transmits dot data of a display pattern one dot at a time to a plurality of display units substantially simultaneously, the display control device transmitting dot data of a display pattern in series, one dot at a time, to a plurality of display units, the pattern generation means, the dot selection means, and each of the display units. It is equipped with a plurality of dot buffers each capable of storing data of one dot in a one-to-one correspondence, and sequentially receives parallel dot data in rask units from the pattern generation means for each of the display units in a time-sharing manner within one dot time. The dot selection means selects one dot of data to be displayed from each of the parallel dot data, stores the selected data in the corresponding dot buffer, and stores the data stored in each of the dot buffers. A display control device characterized in that the display control device transmits data to each of the corresponding display units.