JPS60133794A - Method of producing multilayer printed board - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for surface treatment of a conductor pattern in an intermediate layer constituting a multilayer printed circuit board.

(2) Background of the technology When forming a desired conductor pattern on a plurality of intermediate printed circuit boards and laminating them with a prebrag interposed to form a multilayer printed circuit board, the adhesive strength between each printed circuit board and the prebrag In order to ensure this, a method is used to increase the bonding area by roughening the surface of the conductor pattern on the printed circuit board.

(3) Prior art and problems Figure 1 shows a cross-sectional view of a multilayer printed circuit board, and Figure 2 shows a cross-sectional view of a through hole. The board, 3 is a conductor pattern, 4 is a pre-prepared layer, 5 is a surface layer printed board, 6 is a through hole, 7 is a land, and 8 is a pattern. As shown in Figure 1, the multilayer printed board l is A double-sided surface layer printed circuit board 5 and a plurality of intermediate layer printed circuit boards 2
and a prebrag layer 4 for bonding the respective printed circuit boards.The respective printed circuit boards 2 and 5 are bonded via the prebrag layer 4, and the surfaces of the respective printed circuit boards 2 and 50 and the prebrag layer 4 are bonded to each other. The bonding strength between the printed circuit boards 2 and 5 is influenced by the bonding state between the printed circuit boards 2 and 5.

Therefore, in order to increase the bonding strength between the respective printed circuit boards 2 and 5, the surfaces of the conductor patterns 3 formed on the printed circuit boards 2 and 5 that are in contact with the prepreg layer 4 are roughened to increase the surface area of the conductor patterns 3 that are bonded to the prepreg layer 4. A common method is to increase the anchoring effect of the joint.

For this reason, the surface of the conductor pattern 30 is roughened by blackening with a solution containing sodium hypochlorite and caustic soda as main ingredients, and the needles of cupric oxide with a diameter of 1 to 2 μm and a length of 2 μm are formed. The conductor pattern 30 is formed in a dense manner to increase the effective surface area per unit area of the conductor pattern 30, and is laminated to form an anchoring effect with the epoxy resin of the prebrag layer 4. A through-hole 6 obtained by drilling a hole-to-be-hole portion is electrolessly plated.

At this time, the land 7 to be connected on the intermediate layer printed circuit board 2 exposes the inner wall of the through hole 6.

As a pretreatment for performing electroless plating on the through-hole holes 6, a dilute hydrochloric acid bath of 10 degrees Celsius is applied. The cupric oxide on the surface is easily reduced, and the acicular cupric oxide inward from the inner wall surface is removed, forming a cavity and forming a haloing state. After penetrating and remaining, it is subjected to electroless plating and electrolytic plating to form a multilayer printed circuit board l, and when it is used as a package to mount components and configure electronic equipment, migration occurs due to the potential difference between land 7 and pattern 8. , the insulation resistance between them may deteriorate to 1/1,000,000 times less than normal, and the package may lose its function.

Conventionally, when the minimum distance between the land 7 and the pattern 8 was 500 μm or more, there was no practical problem because the insulation resistance value was high and the deterioration time was short, but recently the pattern density has increased. becomes dense and the minimum distance between the land 7 and the adjacent pattern 8 is about 100μrrL, the insulation resistance value is low and the deterioration time becomes short, so it is no longer possible to maintain the insulation resistance of 19r between the circuits. .

(4) Purpose of the Invention The present invention solves the above-mentioned drawbacks of the conventional art, and the land of the conductor pattern on the bonding surface of the printed circuit board (1) is exposed to the through hole. The object of the present invention is to provide a method for manufacturing a multilayer printed circuit board in which a land that does not cause haloing is formed using a pre-surface for electrolytic plating.

(5) Structure and object of the invention According to the present invention, the second oxide @ obtained by blackening the conductor pattern of the printed circuit board to be bonded.
This is achieved by providing a method for manufacturing a multilayer printed circuit board, which is characterized in that it is reduced in advance to form cupric oxide or copper oxide, which is then laminated and molded.

(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 3 is a schematic diagram of the needle state caused by cupric oxide on the surface of the conductive pattern, and FIG. 4 is a schematic diagram showing the reduction of the cupric oxide in FIG. 3.

In the figure, 9 represents copper foil, IO represents cupric oxide, 11 represents secondary oxide steel, 12 represents reduced d, and 13 represents imidazole coating.

A schematic enlarged sectional view of the surface of the conductor pattern 30 on the laminated surface of the intermediate layer printed circuit board 4 and the surface layer printed circuit board 5 constituting the multilayer printed circuit board l is shown in FIG. The surface of the copper foil 9 is blackened to form cupric oxide 10, and protrusions with a diameter of 1 to 2 μm and a length of about 2 μm grow densely.

In the present invention, prior to laminating cupric oxide 10 shown in FIG. 3, cuprous oxide 11 which is not easily reduced with a strong acid such as dilute hydrochloric acid
Alternatively, convert it into reduced copper 12, and after laminating, drill holes 6 for through-hole plating at desired positions on the inner wall, where the conductor pattern 30 land 7 is exposed, the part ζ of the through-hole hole 6. When the inner wall is subjected to a dilute hydrochloric acid bath as a pretreatment for electroless plating, the easily reduced cupric oxide 10 is mixed with cuprous oxide 11 and reduced copper 12 on the surface of the land 7 exposed in the through hole 6. Since no haloing occurs, no cavities are formed at the bond between the copper foil 9 and the prebrag layer 4, and no penetration of the electrolyte bath solution occurs, migration between adjacent patterns 8 is avoided. There isn't.

In order to convert this cupric oxide 10 into cuprous oxide 11 and reduced copper 12, pensotriazole of imidasol yarn, which has a slow reducing action, is used, and as shown in Fig. 4, cupric oxide 10
The oxidation #1@tl and the reduction@12 are the pharyngeal #1 and the reduction @12.
A rust-preventing imidazole 13 on the thigh is formed on the surface of @ll to a thickness of about 1 μm, and the adhesion to the resin of the prepreg 4 is increased.

(7) Effects of the Invention As is clear from the above explanation, the method for manufacturing a multilayer printed circuit board of the present invention prevents migration between the land in contact with the inner wall of the through-hole and the adjacent pattern. Even if there is a single printed circuit board with a similar pattern and extremely narrow spacing between lands and patterns, a highly reliable package can be formed because there is no deterioration in insulation resistance.

[Brief explanation of the drawing]

Fig. 1 shows a cross-sectional view of a multilayer printed circuit board, Fig. 2 shows a cross-sectional view of a through hole, Fig. 3 shows a schematic diagram of a needle state caused by cupric oxide on the surface of a conductor pattern, and Fig. 4
The figure is a schematic diagram showing the cupric oxide reduction of FIG. 3.

Claims (1)

[Claims] Cupric oxide obtained by solubilizing the surface of the conductor pattern on the joint surface of the surface layer and intermediate layer printed circuit board constituting the multilayer printed circuit board is melted in imidazole form. A method for manufacturing multilayer printed circuit boards that is similar to that of % reduction and then lamination.