JPS60132328A - Photoresist pattern forming method - Google Patents

Photoresist pattern forming method

Info

Publication number
JPS60132328A
JPS60132328A JP24034183A JP24034183A JPS60132328A JP S60132328 A JPS60132328 A JP S60132328A JP 24034183 A JP24034183 A JP 24034183A JP 24034183 A JP24034183 A JP 24034183A JP S60132328 A JPS60132328 A JP S60132328A
Authority
JP
Japan
Prior art keywords
pattern
side wall
photoresist
substrate
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24034183A
Other languages
Japanese (ja)
Inventor
Asamitsu Tosaka
浅光 東坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP24034183A priority Critical patent/JPS60132328A/en
Publication of JPS60132328A publication Critical patent/JPS60132328A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Abstract

PURPOSE:To form a microscopic pattern in excellent reproducibility by a method wherein a side wall of narrow width is formed leaving a thin film only formed on the side face of a pattern, and after a photoresist has been roller coated on the whole surface, the side wall material is exposed by removing the film only on the surface of the side wall. CONSTITUTION:A pattern 12 is formed on a substrate 11 using Al and the like, and after SiO213, for example, has been coated on the whole surface by performing a CVD method, the film 13 located on the surface of the Al pattern 12 and the substrate 11 is removed. Then, when the Al pattern is removed using phosphoric acid and the like, a side wall 14 only is left. At this point, when a photoresist 15 is rotary painted on the whole surface, the photoresist is thinly coated on the upper surface of a side wall 15, and the upper surface of the side wall 15 is exposed by performing an etching using an RIE method again. Then, the exposed side wall is removed using phosphoric acid, and a microscopic photoresist pattern corresponding to the thickness of the side wall can be obtained.

Description

【発明の詳細な説明】 本発明は、ホトレジストパターン形成方法に関し、とく
に電子ビーム露光等の特殊な手段によらずに、0.5μ
m以下の微細パターンを貴男住良く形成できるホトレジ
ストパターン形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a photoresist pattern, in particular a method for forming a photoresist pattern of 0.5 μm without using special means such as electron beam exposure.
The present invention relates to a photoresist pattern forming method that allows fine patterns of less than m in size to be easily formed.

ここ数年集積回路技術の進歩は著しく、数百キロビット
からなる記憶用大規模集積回路(LSI )も各所で試
作されるに至っている。このような技術の流れの中でパ
ターンの微細化は非常に重要な意味をもつことは、いわ
ゆるスケーリング則をまりまでもなく衆目の一致する所
である。一方最近特に化合物半導体デバイスに於ては、
パターンの微細化によって、従来の延長上では推測でき
なかったような新しい現象、例えばバリスティック・ト
ランス、t’−卜現i、ベロシティ・オーバーシ−ト現
象が生じることが判明し、パターンの微細化は一層注目
され始めている。このように、半導体技術全般に亘って
、パターンの微細化は1つの重要な柱であシ、それのも
たらす効果は測り知れないものがあるといえる。
In recent years, integrated circuit technology has made remarkable progress, and large-scale integrated circuits (LSIs) for storage, each consisting of several hundred kilobits, are now being prototyped in various places. It is widely agreed that the miniaturization of patterns has a very important meaning in this technological trend, as is the case with the so-called scaling law. On the other hand, recently, especially in compound semiconductor devices,
It has been found that pattern miniaturization causes new phenomena that could not be predicted from the conventional extension, such as ballistic trance, t'-burden i, and velocity oversheet phenomena. is starting to attract more attention. As described above, pattern miniaturization is one of the important pillars of semiconductor technology in general, and it can be said that the effects it brings are immeasurable.

このような観点から、これまで種々の微細パターン形成
方法が研究開発されてきた。その1つとしては例えば電
子ビームを用いた露光(EB露光)によるホトレジスト
微細パターン形成方法がある。
From this point of view, various fine pattern forming methods have been researched and developed. One such method is, for example, a method of forming a fine photoresist pattern by exposure using an electron beam (EB exposure).

この方法においては、0.5μm以下の微細パターンの
形成も可能であるが、パターンが微細化すればする程露
光時間も長くなり、いわゆるスループットが低下すると
いう欠点があった。またEB露光装置そのものも椿めて
高価であるとともに日常の管理すなわちメンテナンスに
も多くの費用を必要とした。EB露光の他にもX線露光
技術、イオンビーム露光技術などが研究開発されている
が、先、のBB露光技術に比べてもさらに不利な状況に
あるといえよう。
In this method, it is possible to form fine patterns of 0.5 μm or less, but there is a drawback that the finer the pattern, the longer the exposure time, resulting in a reduction in so-called throughput. Furthermore, the EB exposure apparatus itself is extremely expensive, and daily management, that is, maintenance, requires a large amount of cost. In addition to EB exposure, other technologies such as X-ray exposure technology and ion beam exposure technology are being researched and developed, but it can be said that these technologies are even more disadvantageous than the previously mentioned BB exposure technology.

本発明は現状のホトレジスト微細パターン形成技術にお
ける上記の如き欠点に鑑みてなされたものであり、その
目的はEB露光装置の如き特殊な装置を用いずに0.5
μm以下の微細パターンを再現性良く形成できるホトレ
ジストパターン形成方法を提供することにある。
The present invention was made in view of the above-mentioned shortcomings in the current photoresist fine pattern forming technology, and its purpose is to provide a 0.5
It is an object of the present invention to provide a photoresist pattern forming method capable of forming fine patterns of micrometers or less with good reproducibility.

本発明の構成を実施例を用いて詳しく説明する。The configuration of the present invention will be explained in detail using examples.

第1図は本発明によるホトレジスト微細パターン形成方
法を説明するだめの図であり、まず(a)のように基板
11上に第1の物質例えばアルミニウム(Aυよpなる
パターン12を形成する。次に(b)において、全面に
第2の物質例えば5i0213を厚さ3000λだけ通
常の化学的気相成長(CVD)法で被着せしめる。次に
基板11に対し垂直方向から、異方性ドライエツチング
例えば平行電極形リアクティブ・イオン・エツチング(
几IE)により前記AIパターン12の上表面上、およ
び基板11の表面上の前記8 i02膜13を除去する
。このとき、AIパターン側面には、被着せしめたS 
iozが側壁14として形成される(同図(C))。次
に前記AIパターンを例えばリン酸を用いてエツチング
除去すると同図(d)のようにSiO□側壁14のみが
基板11上に残る。
FIG. 1 is a diagram for explaining the photoresist fine pattern forming method according to the present invention. First, as shown in FIG. 1, a pattern 12 of a first material such as aluminum (Aυ, p) is formed on a substrate 11. In (b), a second material, such as 5i0213, is deposited on the entire surface to a thickness of 3000λ using a conventional chemical vapor deposition (CVD) method.Next, anisotropic dry etching is performed from a direction perpendicular to the substrate 11. For example, parallel electrode type reactive ion etching (
The 8i02 film 13 on the upper surface of the AI pattern 12 and on the surface of the substrate 11 is removed by (IE). At this time, the side surface of the AI pattern is coated with S.
ioz is formed as the side wall 14 ((C) of the same figure). Next, when the AI pattern is etched away using, for example, phosphoric acid, only the SiO□ sidewall 14 remains on the substrate 11, as shown in FIG.

次に(e)のように全面にホトレジスト15を回転塗布
する。このとき前記側壁15の上表面のホトレジストは
基板11上に比べて薄く被着される。次に再びRIE法
によシホトレジストをエツチングすると同図(f)のよ
うに側壁15の上表面が露出する。
Next, as shown in (e), a photoresist 15 is spin-coated over the entire surface. At this time, the photoresist on the upper surface of the side wall 15 is thinner than that on the substrate 11. Next, the photoresist is etched again by the RIE method, and the upper surface of the side wall 15 is exposed as shown in FIG. 3(f).

た微細なホトレジストパターンが得られる。パターン寸
法dは(b)の工程においてAIパターンの側面に被着
した5i02膜の厚みに相当、するものであシ、OVD
装置にも依存するが、はソ基板上に被着せしめた5i0
2の厚み(この実施例では3ooo、i= )に相当す
る。なお、所望の寸法のパターンを精度よく得るために
は、基板上に被着せしめたS iozの厚みと、側壁の
厚みとの関係t−,tbらがしめ測定しておけばよい。
A fine photoresist pattern can be obtained. The pattern dimension d corresponds to the thickness of the 5i02 film deposited on the side surface of the AI pattern in the step (b).
Although it depends on the equipment, the 5i0 deposited on the
2 (in this example, 3ooo, i= ). In order to obtain a pattern with desired dimensions with high precision, it is sufficient to measure the relationship t-, tb between the thickness of Sioz deposited on the substrate and the thickness of the side wall.

さて、以上の説明のごとく、本発明においては、第2の
物質(5i02)の膜の厚さに相当した極めて微細なパ
ターンを形成できることがわかる。更に本発明における
方法のもう1つの重要な特長は、その時のホトレジスト
膜の厚みも側壁の高さにはソ相当した、すなわち最初の
第1の物質(A1)の厚さに相当した厚みまで厚くでき
る点であり、いわゆるアスペクト比の大きいパターンが
得られる点である。一実施例においてはパターン長0.
1μm (’ 1000^゛)、パターン厚み07μm
(、7000λ“)のアスペクト比7のパターンを再現
性良く得ることができた。
Now, as described above, it can be seen that in the present invention, an extremely fine pattern corresponding to the thickness of the film of the second material (5i02) can be formed. Furthermore, another important feature of the method of the present invention is that the thickness of the photoresist film at that time is also thick enough to correspond to the height of the side wall, that is, to a thickness corresponding to the thickness of the first first material (A1). It is possible to obtain a pattern with a so-called large aspect ratio. In one embodiment, the pattern length is 0.
1μm ('1000^゛), pattern thickness 07μm
It was possible to obtain a pattern with an aspect ratio of 7 (,7000λ") with good reproducibility.

次に本発明の他の実施例として、本発明によるホトレジ
スト微細パターン形成方法の応用例として、0.2μm
長ゲートを有するGaAsショットキー障壁ゲート型電
界効果トランジスタ(GaAs MESFET)の製造
方法を示す。第2図はその工程図を示し、(a)におい
て牛絶縁性GaAs基板21上に形成した厚み2000
X゛、キアリア密度1.5X10 cm の動作結晶層
22上の所望の領域に厚み0.7μmのA1パターン1
2を形成する。以下、第1の実施例の場合と全く同じプ
ロセスで第2図(b)のような微細なパターンを形成す
る。但し本実施例においては、被着5i02の厚みを2
000λ゛としているために、パターン寸法dは200
0λ’(0,2μm)となっている。
Next, as another example of the present invention, as an application example of the photoresist fine pattern forming method according to the present invention, a 0.2 μm
A method for manufacturing a GaAs Schottky barrier gate field effect transistor (GaAs MESFET) with a long gate is shown. FIG. 2 shows the process diagram, and in (a), the thickness of 2000
A1 pattern 1 with a thickness of 0.7 μm is placed on a desired region on the active crystal layer 22 with a chiaria density of 1.5×10 cm
form 2. Thereafter, a fine pattern as shown in FIG. 2(b) is formed using exactly the same process as in the first embodiment. However, in this example, the thickness of the deposit 5i02 is 2.
000λ, the pattern dimension d is 200
0λ' (0.2 μm).

またホトレジスト厚みは約07μmでろる。次に全面に
ゲート電極となるA123を04μm蒸着しく同図(c
))、リフトオフすることによシ、同図(d)のように
、長さ0.2μm1厚み0.4μmのゲート電極24が
形成される。次に(e)のように通常の方法によシAu
Ge7Niよシなるオーム性電極25 、26を形成す
れば、ゲート長0.211m (D GaAs M、E
SFETが完成する。
Further, the photoresist thickness is approximately 0.7 μm. Next, A123, which will become the gate electrode, is evaporated to a thickness of 04 μm over the entire surface.
)) By performing lift-off, a gate electrode 24 having a length of 0.2 μm and a thickness of 0.4 μm is formed as shown in FIG. Next, as shown in (e), the Au
If ohmic electrodes 25 and 26 made of Ge7Ni are formed, the gate length will be 0.211 m (D GaAs M, E
SFET is completed.

以上、本発明におけるホトレジスト微細パターン形成方
法について示したが、本方法はこの他にもポリイミド樹
脂膜(PIQ )など流動性を有する物質の微細パター
ン形成には十分適用される。
The method for forming a photoresist fine pattern according to the present invention has been described above, but the present method is also fully applicable to forming a fine pattern of a material having fluidity such as a polyimide resin film (PIQ).

まだ実施例では第1、第2の物質として、各々、Al5
SiChを用いたが、5102、S i 3N4の組み
合わせでも、またS ioz、A1の組み合わせでもよ
く種種選択できることは言うまでもがい。
In the embodiment, Al5 is used as the first and second substances, respectively.
Although SiCh was used, it goes without saying that a combination of 5102 and Si 3N4 or a combination of Sioz and A1 can be used to select the species.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(9)、第2図(a)〜(e)は本発明
の各−実施例を説明するための図でちり、11・・・・
・・基板 12・・・・・・AIパターン13・・・・
・・5i02膜 14・・・・・・側壁15・・・・・
・ホトレジスト 21・・・・・・GaAs基板22・
・・・・・動作結晶層 23・・・・・・A1ゲート金
属24・・・・・・ゲート電極 25,26・・・・・
オーム性電極手続補正書(方式)′ 特許庁長官 殿 1、事件の表示 昭和58年 特許 願第240341
号2、発明の名称 ホトレジストパターン形成方法3、
補正をする者 事件との関係 出 願 人 東京都港区芝五丁目33番1号 (423) 日本電気株式会社 代表者 関本忠弘 4、代理人 5、補正命令の日付 昭和59年3月27日(発送日) 6、補正の対象 明細有:の図面の簡単な説明の(閘 7、補正の内容 (1) 明細1第7頁第14行目ζこ[第1図(a) 
〜(f) Jとあるのを「第1図(a)〜仮)」と補正
しすす。
Figures 1 (a) to (9) and Figures 2 (a) to (e) are diagrams for explaining each embodiment of the present invention.
... Board 12 ... AI pattern 13 ...
...5i02 film 14...Side wall 15...
・Photoresist 21...GaAs substrate 22・
・・・Active crystal layer 23 ・・・A1 gate metal 24 ・・・gate electrode 25, 26 ・・・
Ohmic Electrode Procedure Amendment (Method)' Director General of the Patent Office 1, Case Description 1981 Patent Application No. 240341
No. 2, Title of the invention Photoresist pattern forming method 3,
Relationship with the case of the person making the amendment Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative: Tadahiro Sekimoto 4, Agent 5 Date of amendment order: March 27, 1980 (Delivery date) 6. Brief description of the drawings with specifications subject to amendment (7, Contents of amendment (1) Specification 1, page 7, line 14 ζ
~(f) Correct the text "J" to "Figure 1 (a) ~ tentative)".

Claims (1)

【特許請求の範囲】[Claims] 一 基板上の所望の領域に第1の物質よりなるパターン
を形成する工程と、−該第1の物質よシなるパターンの
上面、側面および前記基板表面を覆うごとく第2の物質
からなる薄膜を形成する工程と、基板に対し垂直方向か
ら異方性ドライエツチングによシ前記1Xxの物質から
なるパターンの上表面および前記基板の表面に被着せし
第2の物質から成る薄膜を除去し、前記第1の物質の側
面にのみ前記第2の物質からなる薄膜を残して側壁を形
成する工程と、前記第1の物質を除去する工程と、ホト
レジスト膜を全面に回転塗布する工程と、ドライエツチ
ングにより前記第2の物質からなる側壁の上表面のホト
レジスト膜を除去する工程と、露出したる第2の物質を
除去する工程よυ成ることを特徴とするホトレジストパ
ターン形成方法。
(1) forming a pattern made of a first material in a desired area on a substrate; - forming a thin film made of a second material so as to cover the top and side surfaces of the pattern made of the first material and the surface of the substrate; removing the thin film of the second material deposited on the upper surface of the pattern of the 1Xx material and the surface of the substrate by anisotropic dry etching from a direction perpendicular to the substrate; A step of forming a sidewall by leaving a thin film made of the second material only on the side surface of the first material, a step of removing the first material, a step of spin-coating a photoresist film over the entire surface, and a step of dry etching. A method for forming a photoresist pattern, comprising the steps of: removing the photoresist film on the upper surface of the side wall made of the second material; and removing the exposed second material.
JP24034183A 1983-12-20 1983-12-20 Photoresist pattern forming method Pending JPS60132328A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24034183A JPS60132328A (en) 1983-12-20 1983-12-20 Photoresist pattern forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24034183A JPS60132328A (en) 1983-12-20 1983-12-20 Photoresist pattern forming method

Publications (1)

Publication Number Publication Date
JPS60132328A true JPS60132328A (en) 1985-07-15

Family

ID=17058041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24034183A Pending JPS60132328A (en) 1983-12-20 1983-12-20 Photoresist pattern forming method

Country Status (1)

Country Link
JP (1) JPS60132328A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01110727A (en) * 1987-10-23 1989-04-27 Nec Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01110727A (en) * 1987-10-23 1989-04-27 Nec Corp Manufacture of semiconductor device

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