JPS5940583A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a slender gate electrode by a method wherein a source and drain regions which sandwich the gate region are formed in a semi-insulation GaAs substrate, an SiO2 film adhered thereon is changed columnar and then surrounded by resin, and the gate electrode is buried into the hole generated by drawing off the SiO2 film at the time of providing the gate electrode on the gate region. CONSTITUTION:Si ions are implanted into a semi-insulation GaAs substrate 1 and heat-treated, resulting in the formation of an N type gate region 4, and an SiN protection film 8, SiO2 film 12 and a polycrystalline Si film 11 are laminated and adhered over the entire surface. Next, the lower layer 12 is side-etched in opposition to the upper layer 11 with a photo resist pattern 10 as the mask, the Si ions of high density are implanted and heat-treated, resulting in the formation of the P type source and drain regions 2 and 3 on both sides of the resion 4. Thereafter, the pattern 10 and the upper layer 11 are removed, the polymer resin 16 is coated over the entire surface, thus filling the lower layer 12 which remains, the lower layer 12 is drawn off, the exposed film 8 is removed, and then the gate electrode 7 is buried therein. Then, the resin 16 becoming unnecessary is removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of manufacturing a semiconductor device such as a GaAs-FET (field effect transistor).

[Prior art]

FIG. 1 is a sectional view showing a GaAs-FET. In the figure, 1 is a GaAs substrate, 2 is a source region, 3 is a drain region, 4 is a gate region formed between source region 2 and drain region 3, and 5, 6.7 are a source electrode, a drain electrode, and a gate, respectively. The electrode 8 is a protective film.

In such a GaAs-FET, in order to improve the performance of the device, it is necessary to make the distance between the source region 2 and the drain region 3 as narrow as possible, and also to make the gate electrode 7 thinner. The capacitance of the capacitance must be reduced. In the conventional photolithography processing technology, due to the wavelength limit of light,
Since the following patterns cannot be processed with good reproducibility and it is difficult to achieve overlay accuracy of ±1 μm or less, satisfactory performance cannot be obtained. Therefore,
A manufacturing method using Selfa Line has been proposed.

FIG. 2 is an explanatory diagram of a conventional method of manufacturing a semiconductor device using Selfa Line. In this manufacturing method, first, 81 ions are implanted into required portions of the substrate 10 using a pattern using photoresist as a mask, and then heat treated to form an n-type active layer 9. Next, a protective film made of SiN of 50 m thick is formed. 8 (Fig. 2(a)). After this, from the bottom, 800 nm of Si0g film, 3001m of Poly
- Laminated and deposited Si film, photoresist pattern 10
Using carrier gas CF4+02 as a mask, the PoAy'-'Sl film was etched using carrier gas C
The Sj, 02 film is etched using ci, p2 to form a patterned upper layer 11 and lower layer 12. In this case, by taking advantage of the fact that each film can be etched almost independently by selecting a carrier gas,
The lower layer 12 is processed so as to be side etched with respect to the pattern of the upper layer 11.

Next, after pattern processing, a high concentration of 81 ions is implanted, and heat treatment is performed at 850°C to form an n+ layer.
A source region 2 and a drain region 3 are formed on both sides of 0 (FIG. 2(b)). A resist pattern 10. Upper layer 1
1 serves as a mask and no n+ layer is formed. Note that the protective film 8 protects the substrate 1 during heat treatment and etching.

Next, a polymer resin 13 such as photoresist is applied to embed the lower layer 12 (FIG. 2(C)). After this, after removing the resist pattern ]0° upper layer 11, the lower layer ]2 is etched with carrier gas CC12F2, and the protective film 8 is etched with Gearia gas CF40N2.
The hole 14 is machined (FIG. 2(d)). Subsequently, a Schottky barrier forming metal layer 15 is deposited by successively depositing, for example, Ti, Pt, and Au (Fig. 2(e)
)). Next, the unnecessary metal layer 1 is removed by lift-off processing.
5. The polymer resin 13 is removed to form the gate electrode 7 (FIG. 2(f)). Thereafter, the source region 2. A source electrode 5. is placed on the drain region 3. A drain electrode 6 is formed (FIG. 2(g)).

In this manufacturing method, the source region 2. Since the panning positions of the drain region 3 and the gate electrode 7 are self-aligned, accurate positioning can be achieved. However, when side-etching the lower layer 12, it is not possible to accurately measure the amount of side etching of the lower layer 12 due to the resist pattern 10° and the upper layer 11.
It is impossible to confirm that the amount of side etching of the lower layer 12 has become sufficiently large. Therefore, if etching is stopped before the amount of side etching becomes sufficiently large, the gate electrode 7 will become thicker and the performance of the device will deteriorate. Also, when applying the polymer resin 13, the resist pattern 10. Because of the upper layer 11, it is difficult to apply the polymer resin 13 without any gaps, and if a gap occurs in the polymer resin 13, the gate electrode 7 will become thicker, and in the worst case, a short circuit between the terminals may occur. The device may become defective.

[Purpose of the invention]

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a method for manufacturing a semiconductor device that can improve element performance and yield.

[Summary of the invention]

To achieve this objective, in the present invention, a source region and a drain region are formed on both sides of a gate region using a pattern consisting of an upper layer and a lower layer, and a resin is applied and side etched with respect to the upper layer. In the method for manufacturing a semiconductor device in which a gate electrode is formed after the lower layer is buried and the lower layer is removed, the resin is applied after the upper layer is removed.

[Embodiments of the invention]

FIG. 3 is an explanatory diagram of a method for manufacturing a semiconductor device according to the present invention. In this manufacturing method, first, semi-insulating GaA
s 81 ions are implanted into required parts of the substrate 10 and heat treated.
A shape motion region 4 is formed. Next, from the bottom, a protective film 8 made of SiN, a 5in2 film +2. The Po1Y-8i film 11 is laminated and deposited, and then the poly-8i film II, Sin, film] 2 is formed using the photoresist pattern 10 as a mask.
Select and etch. By this etching, the lower layer 12 is processed so as to be side-etched with respect to the pattern of the upper layer 11. Next, after pattern processing, high concentration 81 ions are implanted, heat treatment is performed, and the gate region 4 is
0 source area 2 on both sides. A drain region 3 is formed (FIG. 3(a)). The above steps are similar to those shown in FIG. After this, only the upper layer 11 is removed (Fig. 3(b)).
). Subsequently, a polymer resin I6 such as photoresist is applied to a thickness of about 3 μm on the surface of the substrate 10 to embed the lower layer 12 and flatten the surface (FIG. 3(C)). next,
0□After removing the upper part of the polymer resin 16 by dry etching such as plasma to make the surface of the polymer resin 16 at the same height as the upper surface of the lower layer 12, the lower layer 12. The protective film 8 is selectively removed to form the hole 14 (see Fig. 3(d)
)). The following steps are the same as in the case of FIG.

That is, when the metal layer 15 is deposited (see FIG. 3(e)),
Unnecessary metal layer 15. The polymer resin 16 is removed to form the gate electrode 7 (FIG. 3(f)), and then the source electrode 5 is formed in a predetermined area. Form the drain electrode 6 (see Fig. 3 (g)
)).

In this manufacturing method, since the polymer resin 16 is applied after removing the upper layer 11, the amount of side etching of the lower layer 12 can be accurately measured with the upper layer 11 removed. When the side etching amount of the lower layer 12 is insufficient, it is possible to make the side etching amount of the lower layer 12 an appropriate value by performing additional etching. Also, the coating of the polymer resin 16 is applied to the upper layer 1.
Since this is done after removing the polymer resin 16, the polymer resin 16 can be applied without any gaps.

In the above-mentioned embodiment, the polymer resin 16 was applied immediately after removing the upper layer 11, but as shown in FIG. 4(a)
As shown in , the upper layer 11 is removed, and then the SiN film 1 is removed.
After depositing, for example, about 400 nm of 7, the polymeric resin I6 may be applied. In this case, as shown in FIG. 4(b), the surface irregularities of the finished zero are reduced, resulting in a structure suitable for (iii) c conversion. In FIG. 4, the same parts as in FIG. 3 are designated by the same reference numerals.

FIG. 5 is an explanatory diagram of another method of manufacturing a semiconductor device according to the present invention. In this manufacturing method, 81 ions are first implanted into the required portions of the substrate 10 and heat treated to form an operating region, then a protective film 8 made of SjN is applied, and a SiO□ film 19 of approximately 1 μm is laminated on this base. and coat it. Next, a photoresist pattern that will become the upper layer 18 of the pattern is formed, and the 5iO9 film is etched using this photoresist pattern to form the lower layer 19 of the pattern.

Next, after such pattern processing, high concentration 81 ions are implanted (FIG. 5(a)). Thereafter, the lower layer 19 is side etched (FIG. 5(b)). Continuing, remove the top layer 18, measure the bottom layer 190, and measure the bottom layer 190.
If layer 9 is too thick, additional etching is performed to form the lower layer 19.
(Figure 5 (C)). Next, heat treatment is performed after ion implantation, and a polymer resin 16 is applied to a thickness of about 3 μm to reduce surface irregularities (FIG. 5(d)). The following steps are the same as in the case of FIG.

In the above embodiments, a method for manufacturing a GaAs-FET was described, but the present invention can also be applied to a method for manufacturing a semiconductor device using an ultra-high frequency crystal such as InP as a substrate. .

Furthermore, in the following embodiments, the explanation has been made based on a pattern of a two-layer structure consisting of an upper layer and a lower layer, but the upper layer and the lower layer may be formed by laminating two or more layers.

As explained above, in the method for manufacturing a semiconductor device according to the present invention, since the side etching amount of the lower layer of the pattern can be set to an appropriate value, it is possible to make the gate electrode thinner, and the device The performance can be improved.Also, since the resin can be applied without any gaps, the gate electrode does not become thicker, and the lead and retention are greatly improved.In this way, the effects of this invention are as follows: Remarkable.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a GaAs-FET, FIG. 2 is an explanatory diagram of a conventional semiconductor device manufacturing method, and FIGS.
Each figure is an explanatory diagram of a method for manufacturing a semiconductor device according to the present invention. 1...GaAs substrate 2...Source region 3...
Drain region 4... Gate region 7... Gate electrode IJ... Upper layer 12 Lower layer 1
4... Holes] 6... Polymer resin 18... Upper layer 19.
Lower layer representative patent attorney Junnosuke Nakamura 11 Figure 3 t4 Figure (Q) (b) 1'5 Figure 399-

Claims (1)

[Claims] forming a desired pattern consisting of at least two layers, an upper layer and a lower layer, on a predetermined substrate; using this pattern, forming a source region and a drain region on both sides of the gate region;
A step of forming a resin layer on this substrate and embedding the lower layer, removing this lower layer, forming an inverted pattern of the desired pattern with the resin, and then forming a gate electrode using the inverted pattern. In the method for manufacturing a semiconductor device, the resin layer is formed on the substrate with the upper layer of the desired pattern removed and with the lower layer narrower in width than the upper layer. A method for manufacturing a semiconductor device.