JPS60132241A - Data processing device - Google Patents

Abstract

PURPOSE:To cope efficiently with a request of a large quantity of continuous memories and a request of memory extension by providing a means for securing a necessary memory area by coupling plural memory area pieces on a main memory. CONSTITUTION:When it is decided by a controlling circuit 6 that an instruction code stored in an instruction register 7 is a memory access instruction, an A1 field of an operand of the instruction register 7 is stored in an address register 2, and an A2 field is stored in a register 21 of a differential circuit 3 through a data bus 37. The controlling circuit 6 reads out a main memory 1 by using a value stored in the address register 2 as an address. The read-out contents of the main memory consist of an Li part for showing the length of a memory area and an Ri part having an address of the next continuous memories, and the Li is stored temporaily in a buffer register 4 through a bus 38, and sent to the differential circuit 3 in order to be compared with an operand part of the memory access instruction stored in the register 21. The Ri is stored in the address register 2 for the purpose of preparation for executing access to the next memory area.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device that can efficiently execute a program that dynamically expands and releases memory during execution.
In particular, the present invention relates to a data processing device that directly executes operands expressed as logical addresses in instructions with high performance using dedicated hardware.

When processing data using an electronic computer, PROLOG and LI, which are high-level languages suitable for symbolic processing, are recently used.
Although programs are often programmed using MP or the like, programs written in these languages dynamically consume a large amount of memory when executed. Processing systems that execute these languages also consume a large amount of memory, but they may request a large amount of memory at once, or expand the size of a previously requested memo during execution. There are many. Many of the tables maintained within the processing system require this function.

However, in the past, these processes were performed using software, and dynamic expansion of memory during execution was often not allowed to prevent a decline in processing efficiency. Also, if a memory area with the memory length requested by the programmer does not exist, the program will terminate there, or the original processing will be temporarily interrupted and the garbage collector will be activated. Garbage collectors collect small discrete pieces of memory, make them into larger pieces of memory, and create a contiguous area on main memory, so they do not necessarily have high performance. Although there are various garbage collection methods, the programs are generally provided as software, and starting the garbage collector program involves a significant decrease in system efficiency.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that exclusively executes a memory management method that efficiently realizes requests for large amounts of continuous memory and requests for expansion of memory length.

Another object of the present invention is to provide a data processing apparatus that employs the above-mentioned memory management method to detect an access error that causes an address boundary in a source program to be crossed during execution.

Using the data processing apparatus of the present invention, the situations in which the garbage collector needs to be activated are greatly reduced, resulting in a significant increase in system efficiency.

When the data and program necessary for processing a given task request a contiguous memory area in the main memory, the data processing device of the present invention physically contiguously stores the memory area of the requested size in the main memory. Even if you do not allocate the memory area to the base address of the continuous memory and the offset from the base address, the request can be satisfied by combining memory area pieces on multiple main memories that are below the required value. The main memory, an address register indicating the position in the main memory, and the address ζ of the set representation when executing the instruction having the address of the set representation in the operand part. It is determined in which memory area piece of the plurality of memory area pieces on the main memory that replaces the continuous memory area the corresponding location on the main memory exists, and the memory area is a differential circuit that performs the process of calculating an offset from one side; a buffer register that temporarily stores the input from the king memory to the differential circuit; an instruction register that stores instructions; ”
It consists of an adder that calculates the base address of the disconnected memory area piece and the offset calculated by the difference circuit, and a control circuit that controls the whole.

It often happens that a program dynamically requests a contiguous memory area or wants to expand that memory area during execution.

For example, if you request N1 bytes of contiguous memory, which is one of the functions of the system description language C, alloc (Nl) (N1 bytes of contiguous memory), the area will be allocated only if contiguous memory of that size or more exists, and the area will be reserved. (The start address is returned as a function value) will be explained in detail.

In conventional data processing devices, the above-mentioned language C statements are processed by a translation program called a compiler that (1) examines the list of unused memory and (2) sets the variable N.
Find an unused memory contiguous area larger than 1 (3) If it exists, return the address of that memory 1 (4
) Machine language that performs a series of processes such as starting a program that calls the garbage collector if it does not exist, collecting all unused portions of main memory, and adding them to the unused memory list.t5) Returning to (2) After being converted into a sequence of instructions, the machine language instructions are executed sequentially.

When requesting a large amount of memory at once, alloc is called. On the other hand, when requesting an expansion of the memory length, the programmer (1) calls alloc with the expanded memory length as an argument.

(2) Copy the data in the memory before expansion to the memory obtained in (1).

(3) Change the address in the program that referred to the memory before expansion to the memory address obtained in (1).

You must perform a series of four steps.

Since all of the above operations are performed by software, their execution efficiency is extremely low.

On the other hand, the memory management method using the present invention allows contiguous memory of a certain size to be realized by combining multiple pieces of memory of smaller size, so it is possible to realize a large amount of contiguous memory in al IOC. It is easy to acquire, and the same function can perform memory-efficient processing for dynamic expansion requests during continuous memory execution. In addition, since the data processing device using the present invention implements the memory management method described above in hardware, sufficient execution performance can be obtained.

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing the structure of data on a main memory used in the memory management method used in the present invention.

In FIG. 1, there are three memory areas Ml on the main memory.

M2 and M3 are connected using a part of each leading word.

The first word of each memory area is two fields L1゜Ri
(i=1.2.3), and the upper field Li
represents the length of each memory area, and the lower field Ri points to another memory area or contains the terminal symbol 0. In the example of FIG. 1, 0 indicating the end is stored in R3 of the memory area M3 at the end of the connection. Ml, M2. Finding M3 and setting values to Li and Ri corresponds to, when the programmer requests a continuous area of a certain size, finding multiple memory areas of smaller size and combining them. This processing needs to be prepared in software or hardware as a memory management mechanism separate from the data processing device of the present invention.

Next, the flow of memory access processing will be briefly explained using FIG. In FIG. 1, 1ft indicates an instruction register in which memory access instructions are stored.

The operand part is divided into AI and A2, where A1 is the starting address of the continuous memory requested by the programmer, and A2 is a virtual offset from the starting word of the continuous memory. The process of extracting the actual destination address from this virtual offset is performed as follows.

The A1 field of the operand points to Ml. When A2, which is a virtual offset, is less than or equal to the size L1 of Ml, that is, when A2≦L1, the destination address exists in Ml. At this time, the value of Al+A2 becomes the destination address. A2) The 1,1 crest performs the same operation as the processing performed for M1 in the memory area M2 pointed to by R1 in the first word of Ml. That is, (A2-LL)≦L
2, the destination address is R1+(A2-LL), and when (A2-Li)>R2, it is understood that the destination address does not exist in M2. Therefore, next, M3 pointed to by R2
Perform the same process with .

Let us consider the execution of a certain memory access instruction, which will be explained using a simple example. 10 in the A1 field of the operand of the instruction register
00, and 50 is stored in the A2 field. Figure 1: The first address of continuous memory M1 is 1000,
The memory length is 30, the first address of M2 is 2000,
The memory length is 50, the first address of M3 is 3000,
Let the memory length be 20.

Under the above assumption, the glue M1 in FIG. 1 is 30. 20 horses
00, R2 of M2 is 50, k”z is 3000
, 1Vi3 Nori.

is 20. Bird becomes O.

The memory access instruction having the continuous memory in the operand field is logically capable of accessing a continuous memory with a memory length of 100. The length of Ml is 30 and %A2
Since A is larger, M2 is accessed by using the first shift of the field while maintaining the 20 difference in length between A and Ml. The length of M2 is 50, so 20 < 50,
Address 2020, which is the starting address 2000 of M2 plus 20, is the destination address expressed in the operand part of the memory access instruction.

FIG. 2 is a block diagram showing one embodiment of the present invention.

The data processing device of the present invention shown in FIG. 2 includes a main memory for storing instructions, data, etc., and an address register 2 that indicates the storage location of the main memory.

and an instruction register 7 for instructing program execution.

A difference circuit 3 which has a function of comparing and storing the difference between the address indicated by the operand field of the mower and Ll, which is a part of the first word of the continuous memory on the raw juice, and the input to the difference circuit 3. A buffer register 4 that temporarily stores Li, which is a part of the first word of the continuous memory that is passed as data, an adder 5 that is used to finally generate a destination address on the main memory, and an instruction fetcher and an instruction It is comprised of a control circuit 6 that controls code determination and processing specified by memory access commands.

The main memory is constituted by an ordinary semiconductor memory, and the program operation progresses by sequentially sending the program from the main memory 11 to the instruction register 7 via the data bus 32 for execution. When the control circuit 6 determines that the instruction code stored in the instruction register 7 is a memory access instruction,
The AI field of the operand of the instruction register 7 is stored in the address register 2, and the A2 field is stored in the register 21 of the differential circuit 3 via the data bus 37.

The address register 2 is a normal register, and the control circuit 6 reads out the main memory using the value stored in the address register 2 as an address. The read 11 main memory is the first
As shown in the figure, it consists of an Li section indicating the length of the memory area and an Ri section containing the address of the next consecutive memory or 0. Li is temporarily stored in the buffer register 4 via 38 in order to check whether the address indicated by the operand part of the instruction held in the instruction register 7 exists in this continuous memory. Ri is stored in address register 2 in preparation for accessing the next memory area. The contents of the buffer register 4 are sent to the differential circuit 3 via 39 for comparison with the operand part of the memory access instruction stored in the register 21.

FIG. 3 is a block diagram showing an embodiment of the detailed configuration of the differential circuit 3, which is composed of a normal register 21 and a decimator 22 that performs binary decimation. The subtracter 22 is connected to the data bus 3
When the result of subtracting the input n from the data bus 39 from the content N of the register 21 input via the register 6 is N -n > 0, a binary a straight 1 is output to the signal 41.

This means that the target address indicated by the operand of the instruction register 7 does not exist in the currently targeted memory area. When the control circuit 6 decodes the binary value data 1 of the signal 41, it stores the calculation result N-n of the subtracter 22 in the register 2] and checks the contents of the address register 2. When this value is O, it means that the operand section of the instruction register 7 attempts to access an address that is out of range, so error handling is performed. If it is not 0, the contents of the address indicated by the address register 2 are read from the main memory 1. This content consists of the continuous memory size Li+x and the next continuous memory address Ri+, Li-+
, + are stored in the buffer register 4, and fl and Ri part 1 are stored in the address register 2. The same processing is performed again in the difference circuit 3.

The calculation result of the subtracter 22 N −n ((When 1,
O is output to the signal 41. This means that the target address indicated by the operand of instruction register 7 is included in the currently targeted memory area.

When the control circuit 6 decodes the binary value data 0 of the signal 41, the value 33 of the register 21 and the value 3 of the address register 2 are obtained.
4 as the human power of adder 5, performs addition, and outputs 3
5 is stored in address register 2. The operation of this adding unit has the meaning of traversing through a piece of memory area, and when it reaches the memory area that includes the destination address, it adds the base address of that memory area and the offset from there to the destination address. .

The control circuit 6 uses g in the address register 2 to read data from the main memory 1. The value obtained thereby is the content of the target address in the memory access instruction.

The present invention has been described above in detail with reference to several embodiments.

When a data processing device according to the present invention is used, memory requests and memory expansion requests during program execution can be processed with much higher processing efficiency than conventional methods.

Another advantage of the data processing apparatus using the present invention is that it is possible to detect errors in the source program, such as accessing an address in the main memory that is not normally allowed, by hardware at the time of execution. This has the effect of being very effective as program device information.

[Brief explanation of the drawing]

FIG. 1 is a left diagram of a structure 1 for explaining the memory management method used in the present invention. FIG. 2 is a block diagram showing one embodiment of the present invention. FIG. 3 is a block diagram showing one embodiment of the above-mentioned three differential circuits. In the figure, 1 is the main memory, 2 is the address register, 3 is the differential circuit,
4 is a buffer register, 5 is an adder, 6 is a control circuit, 7
is an instruction register, 21 is a register, 22 is a subtracter, 31
, :32, 33, 34, :35, , u6, 37, 38, :;9 is a data bus, and 41 is a signal line.

Claims (1)

[Claims] When data and programs necessary to execute a certain task request a contiguous memory area on main memory, the request can be processed even if the requested size of memory area is not physically allocated contiguously on main memory. It satisfies the above requirement by combining memory area pieces in multiple main memories that are less than or equal to the value, and has an operand that expresses a position in the main memory by a pair of a base address of the continuous memory and an offset from the base address. It includes a main memory, an address register indicating a location in the main memory, and when an instruction having an address of the above group expression in the operand part is executed, the location in the main memory corresponding to the address of the above group expression is the above. continuous
determining in which of the plurality of memory area pieces on the main memory that replaces the memory area the memory area exists;
a differential circuit that performs a process of calculating the height offset from the base of the memory area piece; a buffer register that temporarily stores input from the main memory to the differential circuit;
an instruction register that stores instructions; an adder that adds the base address of the memory area piece determined by the difference circuit to the offset calculated by the difference circuit to generate a target address; and a control circuit that performs overall control. A data processing device comprising: