JPS60132221A - Abnormality detecting method of clock pulse - Google Patents

Abstract

PURPOSE:To take easily measures against an unstable or incorrect operation of a CPU due to a frequency variation of a clock pulse by detecting a frequency abnormality of the clock pulse. CONSTITUTION:A test routine is provided on a part of a program, and in accordance with it, a counter is constituted in a CPU2, a clock pulse CK is divided by a frequency divider 4 and a clock pulse LCK is counted. This counting is executed only in a period in which a gate pulse SO is given. That is to say, when an address designating signal AD for generating a decoding output Q3 and a write signal WR are sent out, an output of an AND gate 8c is converted to ''H'', by which a pulse generator 9 genertes as ''H'' a gate pulse of a prescribed time width. In accordance with the end of the gate pulse SO, a count value of this time is compared with the upper limit frequency value and the lower limit frequency value of the divided clock pulse LCK, and in accordance with it, whether the frequencyh of the clock pulse CK is abnormal of normal is decided, and if it is abnormal, an operation of the CPU2 is stopped, or a measure for sending out an alarm, etc. is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for detecting that the frequency of a clock pulse used to regulate the operation of a processor is outside a specified range.

[Prior art]

A clock pulse with a constant frequency is used to regulate the operation of a processor, and a crystal oscillator is generally used to generate this clock pulse to keep the frequency of the clock pulse stable, but for some reason the frequency may change. When this changes, the execution speed of the program by the processor also changes, and the control situation becomes unstable, as the control timing for external devices becomes inconsistent, and if the processor is performing temporal control. This causes problems such as inaccuracy.

However, in the past, although the operating status of the processor was monitored, the clock pulse frequency was not monitored, which resulted in the drawback that it was difficult to discover the aforementioned problems caused by abnormal clock pulses. ing.

[Summary of the invention]

The present invention aims to fundamentally eliminate the drawbacks of the conventional technology, and includes a counter that counts clock pulses in the processor, and a pulse generator that generates gate pulses with a fixed time width in the processor. The clock pulse is driven by a clock pulse, and while this gate pulse is given to the processor, the counter is counted, and based on this count value, it is determined whether the frequency of the clock pulse is above the upper limit value or below the lower limit value. The present invention provides an extremely effective method for detecting abnormalities in clock pulses.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to figures showing examples.

FIG. 1 shows a block diagram in which a clock pulse CK from an oscillator 1 such as a crystal oscillator is given to a processor (hereinafter referred to as CPU) 2 such as a microprocessor, and based on this, the timing of the operation of the CPU 2 is regulated. In addition, it executes the program stored in the memory 3 and performs control or data processing operations while accessing necessary data to the memory 3.

In addition, a test routine is provided as a part of the program, and a counter is configured in the CPU 2 according to the test routine to count the divided clock pulse LCK obtained by dividing the clock pulse CK by the frequency divider 4. However,
This counting is performed only during the period when the gate pulse S0 is applied.

On the other hand, while executing the test routine, the CPU 2 sends out the address designation signal AD from the address bus 5 and also sends out the write signal WR, and repeats this while changing the contents of the address designation signal AD. Then, depending on the contents of the address designation signal AD, the decoder 6
is the decoded output. ,~Q3 sequentially 'H'' (high level)
At the same time, the write signal WR is applied to each section as 1H'' via the buffer circuit 1.

FIG. 2 is a flowchart showing the control status of the CPU 2 according to the test routine). First, the decode output Q+
When the address designation signal AD and write signal WR are sent, the output of the AND gate 8a becomes H", the pulse generator 9 such as a monostable multivibrator is reset, and the flip-flop circuit is reset. (Hereinafter, FF
C) 10 is also reset, 1 initialization '101 is performed, and then.

9. by sending an addressing signal AD and a write signal WR which produce a decode output Q2; When the output voltage of the AND gate 8b becomes H', the p'FFc setting 102 is performed.

Then, the output Q of FFC10 changes to ``H#'', and AN
While the D gate 11 is in the on state, preparations are made to send out the gate pulse S0.

At this time, the pulse generator 9 is not yet driven and the gate pulse S0 is "L" (low level).
Therefore, 5O=L? 103 is checked, and in response to y (YES), the address designation signal AD and write signal WR that generate the decode output Qs are sent out, and the output of the AND gate 8c changes to 'H', thereby 1 pulse generator drive ``104'' is performed, and the pulse generator 9 generates a gate pulse with a constant time width as ``H'', so that the gate pulse SO becomes ``H#'' υ, ``5''.
O=H? In response to the Y of '105, the counter in the CPU 2 performs one step of the lock pulse 'LCK count'106, and then outputs the N of '5O=L?'107.
(No), and the comparison between the count value C of the counter, the frequency upper limit value of the frequency-divided clock pulse LCK, and the corresponding upper limit count value Cu is premised on ``'C>cu?''108ON, and steps 10G and subsequent steps are repeated.

When step 107 becomes Y in response to the end of the gate pulse SO, counting by the counter is stopped, and the count value C at this time is compared with the lower limit count value Cd corresponding to the frequency lower limit value of the frequency-divided clock pulse LCK. 'C C
d? “109 is performed, and if it is N, the test routine is ended and the process returns to the main routine.

Regarding the above, N in steps 103 and 105, and
At Y in steps 108 and 109, it is detected that the count value is greater than or equal to the upper limit count value or less than the lower limit count value. Since it can be determined that the frequency of the clock pulse CK is abnormal, the operation of the CPU 2 may be stopped or
Alternatively, it becomes possible to take measures such as sending out a warning.

However, depending on the conditions, the frequency divider 4 may be omitted and the clock pulses CK may be directly counted. If an output port and an input port exclusively for the test routine are provided,
A separate timing signal is sent instead of the write signal WR, and even if the bumper circuit 7, FFCl01AND gate 111, etc. are omitted, the same result will occur.
Various modifications are possible, such as using K as an interrupt signal, executing a test routine in response, and performing parallel processing with other programs.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, an abnormality in the frequency of the clock pulse can be detected by adding a simple circuit, and measures can be taken against instability or inaccuracy in the CPU operation due to changes in the frequency of the clock pulse. can be easily performed, and a remarkable effect can be obtained for the purpose of monitoring the clock pulse frequencies of various processors.

[Brief explanation of the drawing]

The figures show embodiments of the present invention, with Figure 1 being a Pronk diagram and Figure 2 being a Pronk diagram.
The figure is a flowchart showing the control status of the CPU. 1... Oscillator, 2... CPU (processor),
4... Frequency divider, 6... Decoder, 9... Pulse generation f5. CK...Clock pulse, LCK
...Divided clock pulse, SO...e gate pulse. Patent applicant Yamatake Honeywell Co., Ltd.

Claims (1)

[Claims] A counter for counting applied clock pulses is configured in the processor, the processor drives a pulse generator that generates a gate pulse of a constant time width, and the counter is configured to count the applied clock pulses during the period when the gate pulse is applied to the processor. , and compares the counted value with an upper limit count value corresponding to the frequency key limit value of the clock pulse, and determines that there is an abnormality when the count value exceeds the upper limit count value, and
The count value is compared with a lower limit count value corresponding to a frequency lower limit value of the clock pulse in response to the end of the gate pulse, and when the count value is less than or equal to the lower limit count value, an abnormality is determined. A method for detecting abnormalities in clock pulses.