JPS60129998A - Decoder circuit of redundancy constitution mos memory - Google Patents

Abstract

PURPOSE:To attain high speed operation by changing the connecting position of a programmable element. CONSTITUTION:A potential holding MOS transistor (TR)9 whose source is connected to a common potential is added to a precharge MOSTR2, a gate of the potential holding MOSTR9 is controlled by an output of a redundancy circuit A, which is provided with a programmable element 14. The redundancy circuit A controls the potential of a node 7 by transmitting information set to the programmable element 14 connected to the potential holding MOSTR9. The adverse effect to be connected with the programmable element in series with a word line drive signal is excluded and it gives much contribution to the high speed operation of the MOS memory.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a decoder circuit in a redundant MOS memory, and particularly to a decoder circuit that operates at high speed.

<Prior Art> The entire decoder circuit of a commonly used redundant configuration MOS memory is shown in FIG.

In the same figure, it is a lid word line selection M 0 S + - transistor, and an address signal φ. ~φAN razor,
Connect to the gate of it to determine selection or non-selection.
l,ru. A drain precharging MOS transistor 2, which is commonly connected to the MOS transistors 1, is connected thereto. A precharge signal φ is applied to the gate of the precharge MOS transistor 2.

or connected. The train of the M0S transistor 1 for word line selection has a master transfer cable 1-.
31, (through which the gate of l0SI/Lannonstar 4 is connected to the word line section dvJ.
The drain I/lt word line 21 of the OS transistor 4 is connected to the drive signal φ3, and the word line and drive signal φ3 are all led out to the word line 6 under the control of the gate signal.

Here, the word line 6 is programmed by a laser beam or other external factor, and is normally set to a conductive state, in order to create a decoder circuit suitable for a redundant MOS memory. Enable element 5 is inserted,
If there is a defect in the memory cell connected to the word line 6, the programmable element 5 is disconnected to completely prohibit access to the defective memory cell.

FIG. 7 is an operation timing diagram of the decoder circuit shown in FIG. 6 above.

φP is a precharge signal input to the gate of precharge MO8) transistor 2, and during the precharge period, MO3+-
5) Node 7 which is the drain of transistor 1 and MO
A word line and a node 8, which is the gate of the driving MOS transistor 4, are precharged via the S transistor 3. When entering the active period, address signals φAO to φAN are input and decoding is performed, and the nodes of the unselected decoder circuit and node 8 fall to the ground potential, and the nodes 7 and 8 of the selected decoder circuit fall to the ground potential. Node 8 is held at a high potential. Next is the transfer signal φ. 1, the transfer gate 3 is turned off, the node 7 and the node 8 are cut off, and the drive signal φ3 is input to the word line driving M0S I-run register 4 to select the decoder circuit. block on the word line 6 of the block, driven through the RAM enable element 5-! The lll1 signal φ3 is output.

2. In the conventional decoder circuit, since the stray capacitance C of the word line 6 is generally large, a large signal delay occurs due to the resistance of the programmable element 5 formed by the polygon 81 or the like. It is generally difficult to reduce the resistance of the programmable element 5, and in the conventional method shown in FIG. 6, this phenomenon is a major factor in slowing down the access time of the memory element.

<Object of the Invention> The present invention provides a decoder circuit for a redundant configuration M 0 S memory which eliminates all the drawbacks of the conventional circuit and achieves high-speed operation by changing the connection position of programmable elements.

<Embodiment> FIG. 1 shows a first embodiment of a decoder circuit according to the present invention, and FIG. 2 shows an operation timing diagram of the decoder circuit.

The Tekoter circuit has the same circuit configuration as the conventional circuit with regard to address selection, and uses an address signal φa. ~φA
N is connected to M'O3) for address signal decoding, and selection or non-selection is determined. The common connection of the transistor I (MO5) for the charge code, and the node 7 which is the train, is connected to the precharge MOS l-.
A transistor 2 and a transfer gate 3 are connected to each other, and word lines and driving 11.
1 OS) Transistor 4 is connected to lead word line drive signal φ3 to word line 6. A programmable element is connected to the word line 6 as in the conventional circuit, but in the decoder circuit of the present invention, a potential holding MO whose source is connected to the ground potential is connected to the transistor 2.
All S transistors 9 are added, and the potential holding MOS transistors 90 are controlled by the output of the full redundant circuit A, and the redundant circuit A is provided with a programmable element 14.

The above redundant circuit Ai+-1, potential holding MOS )U'
In order to control the potential at the node 7 by transmitting information to the programmable element 14 in the register 9, the configuration is as follows. The driving M0S transistor 1O is connected to the driving M0S transistor 10'i1. Ru. A second drive signal φ2 is connected to the drain of the drive MOS transistor 10, and the gate () is connected to the second drive signal φ2.
It is connected to the connection point ()-15) between the second precharge MOS transistor 12 and the programmable element 14 via the ir and Jl transfer gates 11i. "Nili's second free charge M OS"
The gate of the +- transistor 12 is connected to the transistor No. 3 φ in the same way as the MOS transistor 2, and precharges the node 15 and the node 16i to a high potential during the precharge period. The other end of the programmable element 14 is M 0 S to which the first drive signal φ1 is applied to the gate.
It is grounded via a transistor 13. Like the elements of the conventional circuit, the programmable element 14 is normally set to a conductive state, and is disconnected only when a defective memory cell is present on the word cell 6, so that memory cell information is permanently recorded.

When the Teyoda circuit having the above configuration enters the active period following the precharge period, the first drive signal φl is input to the MOS transistor 130 gate, and if the programmable element 14 is in a conductive state, the node I5 and the node I
6 is discharged to the entire ground potential, and as a result, the drive MOS transistor 10 becomes cut off, and even if the second drive signal φ2 is input, the potential holding MOS transistor 9 maintains the cut off state. This decoder is the address signal φAO
- Perform operations according to the combination of φAN. On the other hand, when the programmable element 14 is disconnected, the nodes 15 and 16 remain at high level even if the first drive signal Il+ is input, and therefore the second drive signal φ
2 is input i9. Then, the potential holding MOS transistor 9 is connected via the driving MOS 'l-transistor 10' (i).
, the gate of - node 7 and node 8 become ground potential regardless of the state of address signal φho''l□hh, and word line 6 is always unselected. In other words, the conduction of programmable element 14 The potential corresponding to the disconnected state is transmitted to the node 7 in advance, and since there are no elements on the word line 6 side that may cause a delay, the drive signal φ3 is set to 10.
8 transistors 4 through all immediately V power "MA '7
(/This is derived.

Fig. 3 shows a second embodiment using a non-explosion J, 1, and a driving M.
OS + - A discharge M0S) Larestar 18 is added between the source of the Runsistor 10 and the ground potential, and a precharge signal φ1. This is a Tekota circuit that inputs the power to form the entire discharge circuit of the node 17, and is designed to operate more cheaply.

FIG. 4 shows a third embodiment using a non-firing JvC, the circuit configuration is the same as the previous R12 second embodiment, and the precharge signal φ is input to each gate of the precharge MOS transistors 2 and 12. ]11. The operation is performed when φ1 and φ2 are applied as signals having different falling timings as shown in FIG. That is, it is not necessarily necessary to use the same signal φP as a signal for controlling all of the precharge MOS transistors 2 and 12, and other signals may be used as long as the pulse signals overlap in the precharge period.

Furthermore, in each of the first to third embodiments described above, the connection between the programmable element 14 and the i53 MOS transistor 13 can also be configured by connecting the programmable element 14 to the ground potential side.

<Effects> As mentioned above, the Tecoator circuit (misfire) can eliminate the negative effects caused by the presence of a programmable element in series on the word line and drive signal, and M 0 S
This is a major hindrance to speeding up memory.

[Brief explanation of the drawing]

Is Fig. 1 an embodiment of the present invention? 2 is a timing diagram of the circuit of FIG. 1, FIG. 3 is a circuit diagram of a second embodiment according to the present invention, and FIG. 4 is a circuit diagram of a third embodiment according to the present invention. Figure 5 is a timing diagram of the circuit in Figure 4.
Figure 6 is a circuit diagram of a conventional redundant configuration MOS decoder;
The figure is a timing diagram of the circuit of FIG. 6. 1: MOS transistor for word line selection, 2°3.4
,9,10. II, 12, 13.18: MO3+・Lancisister, 14: Programmable element, 6 wires,
C: Stray capacitance of word line, φ3: Word line 5 drive signal, φ7, Nidor transfer gate drive ff1lJ (Go number,
φP, φP1. φP2' Precious word number, φ1.
φ2: Redundant circuit control signal, Voo Telephone agent Patent attorney Yoshihiko Fukushi (and 2 others) 3rd
Figure φAO-4JAN

Claims (1)

[Scope of Claims] 1. The precharge state of the commonly connected output lines of the word line selection MOS transistors controls the conduction/non-conduction of the word line and drive 0J MO5) run transistor to output a signal to the word line. In the dynamic node coder circuit that controls the derivation of Connect the redundant circuit output connected to the programmable element which recorded the programmable element, and the redundant circuit holds the potential holding MO3+- transistor non-conductive while the programmable element is conductive, and the programmable element is held non-conductive. MOS transistor for holding potential in state? A decoder circuit for a redundant MOS memory, characterized in that the decoder circuit forms an output signal that causes conduction. 2. The redundant circuit includes a MOS transistor for precharging, a MOS transistor for precharging, and a programmable element inserted in series between the power supplies, and a MOS transistor for driving, the gate of which is given the output of the MOS transistor for precharging. The discharge M is based on the output of the driving MOS transistor.
A decoder circuit for a redundant Mt)S memory according to claim 1, characterized in that the entire operation of the OS transistors is controlled. 3. The decoder circuit for a redundant MOS memory according to claim 2, wherein the driving MOS transistor of the redundant circuit has a discharge MOS transistor connected between it and a ground potential.