JPS6129069B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for rapidly transferring data between successive memory locations of a semiconductor memory.

In computer equipment and the like, it is often desirable to quickly read data stored in several successive memory locations. In such a situation, individual row and column addresses are not required to access the data in each memory location. All that is needed is a first memory location and some means of automatically directing memory to subsequent memory locations. Rapid writing of data to subsequent memory locations can be done in the same general manner.

Some conventional memories have a feature called "page mode" operation for quickly reading data stored in successive memory locations. In this mode of operation, data stored in one row of memory is held in multiple sense amplifiers. Subsequent column addresses are then input to the memory to sequentially output the data stored in each sense amplifier. Since successive row addresses are not required to read data stored in successive memory locations within the row being accessed, data read time is reduced by a factor of two. However, the standard read-write cycle time to page mode cycle time ratio (typical value is 2) makes it normal to require more complexity in configuring devices to perform page mode operations. often not high enough to make a difference.

The object of the invention is to obtain a device for rapidly exchanging data to and from successive memory locations of a semiconductor memory.

According to the invention, N data latches are each associated with one said data latch for storing data associated with N consecutive memory locations defined by a plurality of bits of the address input; an address input having a given logic state and a corresponding N series-connected decoders configured to output the data stored in the associated data latch onto the data output bus. One decoder is initially activated in response to the bit being selected, and each decoder receives an address input such that the data stored in the data latch associated with that decoder is output onto the data output bus. The activated decoder receiving the selected bit is configured to thereafter disable itself and activate the next decoder, and the next decoder and the remaining decoders are activated. is configured such that the data latch disables itself and enables the next decoder after the address input is received, causing the data latch to output the next N successive bits of the decoder onto the data bus in response to one address input. A device is obtained for rapidly transferring data between successive memory locations of a semiconductor memory and a data output bus, characterized in that:

The present invention has the advantage that data can be transferred more quickly and with a simpler configuration than conventional page mode devices.

The present invention allows data stored in successive memory locations of a semiconductor memory to be rapidly read from the memory in response to a single address input. To do this, the apparatus of the present invention includes N data latches associated with N consecutive memory locations for storing data. Their memory locations are defined by multiple bits of the address input.

N decoders connected in series are included to sequentially select the buffers to output the data stored in the buffers. Each decoder is associated with one data latch. In response to an address input, one decoder is activated to output the data stored in its associated data latch. Thereafter, said one decoder disables itself and enables the next decoder so that the second data latch outputs the data stored therein. This operation continues in sequence, with each activated decoder disabling itself and activating the next decoder so that the data latch sequentially outputs the data stored therein.

In a preferred embodiment of the invention, the inclusion of N data buffers provides for rapid writing of data to memory. Those data/
The buffer is adapted to receive incoming data and output the received incoming data to N consecutive memory locations when the memory is in write mode. Each data buffer is controlled by one of the decoders which is activated as described above. An activated decoder causes its associated buffer to output its stored data to memory. In this manner, N data buffers are sequentially selected to cause incoming data to be written to N consecutive memory locations.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

Reference is first made to FIG. 1 in which an apparatus for rapidly reading data from and rapidly writing data to successive memory locations of a semiconductor memory is shown. In the apparatus shown in FIG. 1, a "nipple mode" of operation is provided in which four bits of data are read and written to four consecutive memory locations in response to a single address input.

This device has four data latches, shown as output sense amplifiers A ₀ , A ₁ , A ₂ , A ₃ , and four decoders D ₀ , D ₁ , D ₂ , D ₃ . include.
Each decoder is associated with one sense amplifier. The sense amplifier stores four bits of data received from four consecutive memory locations. One sense amplifier stores one bit. Their memory locations are defined by 6 bits of the 8 bit address input. Generally, each decoder is activated to output data stored in its associated sense amplifier to data bus 10 via output latch 12. To begin outputting data, one decoder, _e.g. Each decoder receives two bits of address input so as to output . The activated decoder then deactivates itself and the next decoder, e.g.
D ₁ is activated to cause the sense amplifier A ₁ associated with the decoder to output the stored data. This operation continues in sequence, with each activated decoder disabling itself and activating the next decoder so that the sense amplifiers are activated in sequence. In this way, 4 of the data
A bit responds to one address input by inputting data.
It can be output to the bus.

As will be explained later, in response to one address input, four bits of input data are transferred to data input buffers B ₀ -B ₃ associated with decoders D ₀ -D ₃ from four successive locations in the memory. In order to add locations sequentially, decoders D ₀ -D ₃ are also adapted to be activated sequentially. Thus, the illustrated device operates in "nipple mode" to rapidly write and read data to and from memory.

More specifically, the output sense amplifier AO is adapted to store data bits and their complement bits received from memory locations via data buses DB ₀ and ₀ . Similarly, the sense amplifier, A ₁ ,
A ₂ and A ₃ are also connected to the data bus from successive memory locations.
Data bits received via DB ₁ and ₁ , DB ₂ and ₂ , and DB ₃ and ₃ and their complement bits are stored. The data bits (and their complement bits) carried by buses DB ₀ to _{DB 3} are 6 of 8 bit address inputs to memory.
from four consecutive memory locations defined by the bit.

The output terminal of sense amplifier A ₀ is connected to the drains of MOS transistors 14 and 16. The sources of these transistors are coupled to the input terminals of output latch 12 via leads 18 and 20, respectively. Thus, when transistors 14 and 16 are turned on, the data stored in sense amplifier _A0 is provided to output bus 10 via output latch 12. Similarly, sense amplifier
The output terminals of A ₁ to _{A 3} are transistors 22 and 24,
are coupled to output latch 12 via 26 and 28, 30 and 32, respectively.

Decoder D ₀ receives two selected bits ₀ and ₁ from the input address via leads 34 and 36. . The remaining decoders D ₁ - _{D 3} also receive the same address bits, but their address bits
Since the combinations of logic states of the bits are different, initially only one decoder is selected or activated. . For example, decoders A ₁ , A ₂ ,
_A3 receives bits ₀ and _A1 , _A0 and ₁ , and _A0 and _A1, respectively. Therefore, when ₀ and ₁ are both low logic levels, decoder D ₀ is activated. And decoders _D1 to _D3 are all inactive.
However, when both ₀ and _A1 are at a low logic level, only decoder _D1 is activated. in this way,
Suffice it to say that the input bits of the decoders have a given logic state which activates any one of the decoders _D0 to _D3 . The operation of the remaining decoders will be explained later.

Decoders D ₀ -D ₃ also receive a clock signal R _POF . After the decoder is activated, the clock signal φ _POF clocks the operation of the decoder. This will be explained next.

Decoder by bits ₀ and ₁ which are low level
Assuming D ₀ is selected, decoder D ₀ generates output signal Y ₀ when clock signal φ _POF goes low at time t ₁ (FIG. 2). That signal Y ₀
is applied via lead 38 to the gates of transistors 14 and 16 to turn them on. Therefore, the data stored in the sense amplifier _A0 is transferred to the transistors 14 and 16.
is applied to output bus 10 via leads 18 and 20 and output latch 12. The high or low level data output thus provided to output bus 10 is represented by waveform D ₀ in FIG.

The decoder D ₀ then disables itself and turns off transistors 14 and 16;
The output signal Y ₀ is applied via lead 40 to the next decoder D ₁ . Decoder in response to this signal
Since D ₁ is selected, the clock signal φ _PO is activated at time t ₂ .
When _F goes low again (Figure 2), the decoder
D ₁ produces an output signal Y ₁ on lead 42 to turn off transistors 22 and 24. Therefore,
Output data D ₁ from sense amplifier A ₁ (Figure 2)
is applied to the output bus 10, after which the decoder
D ₁ becomes inactive by itself and transistor 2
2 and 24 and turn off the output signal.
Give Y ₁ to decoder D ₂ to select. This operation continues as decoders D ₂ and D ₃ are activated in sequence to output decoders D ₂ and D ₃ (FIG. 2) in synchronization with clock pulse φ _POF .

After the data is read from amplifier A ₃ , decoder D ₃ sends output Y ₃ to the decoder via lead 44.
Select decoder D ₀ by applying to D ₀ . In this way, each decoder can be selected for another quick data read. Alternatively, as shown in FIG. 2, the nipple read cycle described above can be followed by a normal read cycle.

It should be understood that when any decoder is first selected by a pair of low level input bits, a nipple mode cycle begins. Thereafter, other decoders are selected in sequence until the four sense amplifiers A ₀ -A ₃ output their stored data.

To perform nipple write mode operation,
Each data input buffer has a pair of transistors coupled to its associated data bus and controlled by a decoder for receiving input data. For example, buffer B ₀ receives input data bits D _io and _io via transistors 46 and 48, respectively. The output _of this buffer is applied to data bus DB _0,0 . Batsuhua B ₁ ~
_B3 are similarly connected to couple input data to their respective associated data buses.
When the memory is in write mode, decoder _D0 is activated as described above to turn off transistors 46 and 48 and transfer input data to the bus.
Join to DB ₀ , ₀ . Then, decoder D ₁ ~
D ₃ are activated sequentially as described above,
Read the remaining 3 bits of input data to the remaining bus. In this way, four bits of input data can be rapidly written to four consecutive memory locations in memory.

In FIG. 1, the output sense amplifiers A ₀ -A ₃ and the output latch 12 can be conventional ones. The decoders D ₀ to D ₃ are all the same, and preferably those shown in FIG. 3 are used. Buffers B ₀ to _{B 3} also have the same structure, one of which is shown in FIG. 6 is a timing waveform diagram of various input signals, output signals and clock signals in the circuit shown in FIGS. 3 and 4. FIG.

FIG. 5 is a table of indexes linking the signals generated in the circuit of FIG. 3 to various decoders. For example, if the circuit of Figure 3 represents a decoder D ₀ , then Y _i is the signal Y ₀ generated by decoder D ₀ and Y _i+3 is the signal generated by decoder D ₃ .
_Y3 . If the circuit of Figure 3 represents a decoder D ₁ , Y _i is the signal generated by the decoder D ₁ .
Y ₁ and Y _i+3 represent the signal Y ₀ represented by the decoder Y ₀ .

Refer now to FIG. The illustrated decoder has an address input A ₀ on the gates of transistors 50 and 52.
(or ₀ ) and receive A ₁ (or ₁ ). Output lead 54 outputs the output signal Y generated by the decoder.
tell _i . Its output is used to output data stored in a sense amplifier associated with this decoder, and is also applied to the gates of transistors 56 and 58. If the illustrated decoder is D ₀ , then the signal Y _i represents the signal Y ₀ shown in FIG.

A signal Y _i+3 is applied to the gate of transistor 60. If the illustrated decoder is D ₀ then the signal Y _i+
3 is the signal Y ₃ shown in FIG. 1 and corresponds to the Y _i output of the decoder D ₃ .

The illustrated decoder receives the precharge signal φ _D (FIG. 6). This signal is initially high and is applied to the gate of transistor 62, causing its source (node 64) to be high. Another clock signal φ _OD2 (Fig. 6) is also at high level, at circuit point 64.
to the gate of transistor 66, which is coupled to the gate of transistor 66. Since the gate of transistor 66 is coupled to circuit point 64, transistor 66
The drain of (circuit point 68) is also brought to a high level.

Signal φ _D is also applied to the gate of transistor 70 to preliminarily set circuit point 72 to a high level. Therefore, transistors 74, 76 are turned off and their drains (circuit point 7) are turned off.
8,80) to a low level.

The gate of another transistor 82 receives signal φ _D and raises the voltage at node 84, turning off transistors 86 and 88 and causing their drains (nodes 90 and 92) to go low. Thus, transistors 94, 96 whose gates are coupled to circuit points 90, 92, respectively
is turned off. The source of transistor 96 is coupled to transistor 100 via node 98. The gate of this transistor 100 receives a signal _φD . Therefore, the transistor 100
is turned on and lowers the voltage at circuit point 8. Accordingly, transistor 102 whose gate is connected to circuit point 98 is also turned off. The drain of transistor 102 is coupled to node 64, but since transistor 102 is now off, transistor 102 is coupled to node 64.
It does not disturb the high level at 4.

At this time, the signal φ _POF (see FIGS. 1 and 6) is at a high level and is applied to the transistor 104. The gate and source of transistor 104 are coupled to nodes 78 and 80, respectively. Since circuit point 78 is at a low level, transistor 104
is held off and node 80 is at a low level. Circuit point 80 is also coupled to the gate of transistor 106. At this time, this transistor 10
6 is also in the off state.

Signal φ _POF is also applied to transistor 94 . A circuit point 9 is connected to the gate of this transistor 94.
Since a low level of 0 is applied, transistor 94 remains on and the potential at its source (circuit point 92) is at a low level.

Assume now that the address inputs to transistors 50 and 52 are both low and the transistors are off. Circuit points 64 and 68 are then held high. Circuit point 68 is coupled to the gate of transistor 108;
The drain of this transistor 108 is the signal φY ₀
receive. Since this signal φY ₀ is at a high level (FIG. 6), transistor 108 outputs a high level output to lead 54.

This lead 54 is also coupled to the drain of transistor 109. The gate lead 111 of this transistor 109 is coupled to circuit point 80.
It will be recalled that during the precharge cycle, circuit point 80 was pulled low. Transistor 109 is therefore kept off, allowing signal Y _i on lead 54 to go high. In this way, the illustrated decoder has D ₀ (first
), Y _i represents the signal Y ₀ and transistors 14 and 16 are turned on. All other decoders are inactive because at least one address input of the other decoders is high. Accordingly, at least one transistor corresponding to transistors 50, 52 in the other decoders is turned on to connect circuit points 64, 68.
The voltage at the circuit point corresponding to is made low, thereby inhibiting φY ₀ from driving Y _i high in the other decoders.

As mentioned above, after the sense amplifier associated with each decoder outputs the stored data, each decoder becomes inactive. To this end, a signal Y _i on lead 54 is applied via lead 112 to the gate of transistor 110 and also to the gate of transistor 58 . Therefore, node 84 is pulled low and transistors 86 and 88 are turned off. Also, transistor 110 is turned off, raising the potential at node 90 and turning on transistor 94. When the signal φ _POF goes high again at time Ta (FIG. 6), the signal is applied to circuit point 92 via transistor 94. Therefore, transistor 96 turns on, causing node 98 to go high.
Transistor 102 is turned on and circuit point 6
4 is brought to a low level. Therefore, the signal φY ₀ will then go high and the decoder will be disabled so that the output Y _i will not be driven high.

Reference is now made to FIG. Signal φ _POF at time Ta
It can be seen that when the signal φY0 goes to a high level, the signal _φY0 goes to a low level. When signal φY ₀ goes low, output Y _i on lead 54 is also brought low.

Assuming that the operation described above concerns decoder D ₀ , decoder D ₀ enables decoder D ₁ such that decoder D ₁ is activated by the next high level pulse φ _POF . To explain this operation, assume that the circuit shown in FIG. 3 represents decoder _D1 (all decoders have the circuit configuration shown in FIG. 3). Then, the input Y _i+3 to decoder D ₁ is
Represents the Y _i output of D ₀ .

When the Y _i output of decoder D ₀ is at high level, the Y _{i +3} input transistor 6 to decoder D ₁
0 gate is driven to high level. Therefore, node 78 will be brought high and transistor 104 will be turned on. time
When signal φ _POF goes high at Ta, transistor 104 drives node 80 high, turning transistor 106 on. Since the source of transistor 106 is coupled to node 64, node 64 is driven high. signal φ
₀ D ₂ also reaches a high level at time Ta. Therefore, circuit point 68 is also set to a high level. However, since signal φY ₀ is at a low level at that time, transistor 108 keeps the Y _i output of decoder D ₁ at a low level. However, time t _b (Fig. 6)
When the signal φY ₀ goes high, the Y _i output on lead 54 is driven high.

The above operation continues for each nipple cycle, with the i-th decoder activating the i+1-th decoder when the signal φY ₀ goes high.

Each decoder also includes a holding circuit coupled to Y _i output lead 54. This circuit consists of transistor 11
2,114,116,118,120. These transistors are configured to actively keep the unselected decoder Y _i outputs low.

Gate signal φ _PO of transistors 114 and 120
Since they receive _F , their sources (points 122 and 124) are pulled high during precharge. Since the signal φY ₀ is applied to the gate of the transistor 118, when the signal goes high, the drain of the transistor 118 (124 in the circuit) goes low.

Assuming node 64 is low (indicating that the decoder is not selected), transistor 116 remains off and node 12
2 maintains a high level. Transistor 112 is therefore turned on, keeping lead 54 at ground potential.

When node 64 is high, transistor 116 is turned on, causing node 122 to go low, turning transistor 112 off and allowing lead 54 to be driven high.

Next, refer to FIG. This figure shows a circuit diagram of data input buffers B ₀ -B ₃ of FIG. 1. This buffer is connected to input leads 126 and 12 for receiving data input DIN, which is applied from the outside.
8 and output leads 130, 13 coupling the output DB _i , _i to the data bus (DB ₀ , ₀ ) of FIG.
Contains 2. The other input terminals are connected to circuit point 64 in Figure 3.
Leads 134 and 136 are coupled to circuit point 80 of FIG. 3, and lead 140 is coupled to circuit point 92 of FIG. 3. As will be explained in more detail below, an activated decoder activates its associated buffer to provide data input (DIN,
) is coupled to DB _i , _i output.

If the decoder associated with the illustrated buffer is not activated, the potential at node 64 of that decoder is at a low level. The low level potential is coupled through lead 134 to transistors 142 and 144. A signal φ ₀ D ₂ is applied to the gates of these transistors. Therefore, the sources of transistors 142 and 144 (points 146 and 148) are at a low level.

Circuit points 146 and 148 are transistors 150,
It is directly connected to the gate of 152. An input DIN is given to each of these gates. When circuit points 146 and 148 are low, those transistors remain off and the input DIN;
are disconnected from the output leads 130, 132.

When the decoder associated with the illustrated buffer is activated, the potential at node 64 of the decoder goes high. Therefore, buffer points 146 and 148 are both high and transistors 150 and 152 are turned on. input
When DIN is high and the input is low, the sources of transistors 150 and 152 (points 154 and 156) are driven high and low, respectively.

Node 154 is coupled to the gates of transistors 158 and 160, and node 156 is coupled to the gates of transistors 162 and 164. Therefore, transistors 158 and 160 are turned off and transistors 162 and 164 are turned on. To this end, leads 130 and 132 are driven high and low, respectively. The data coupled to leads 130, 132 is thereby written to the selected memory location via one of the pair of data buses of FIG.

It will be appreciated that writing data to memory is a relatively time consuming operation. Therefore,
The data output from the buffer shown is kept available for reading even after the next subsequent decoder and buffer is activated on the next nipple cycle. To that end, the output leads 130,1 during the next subsequent nipple cycle.
Transistors 166 and 168 are included to maintain the logic level at circuit points 154 and 156 so that the logic level on node 32 remains unchanged.

The gates of transistors 166 and 168 are coupled via lead 140 to node 92 in FIG. This circuit point 92 is driven high when signal φ _POF goes high at the beginning of the nipple cycle. Therefore, transistor 16
6,168 is turned on. Since the drains of transistors 166 and 168 are coupled to the gates of transistors 150 and 152, respectively, transistors 150 and 152 are turned off. Therefore, the high and low levels previously applied to circuit points 154 and 156, respectively, are retained there. For that purpose, transistor 1
58 and 160 are kept on and transistors 162 and 164 are kept off. lead 1
The high and low levels appearing at 30 and 132, respectively, are thus preserved. Therefore, since the write operation can be repeated in three consecutive cycles, the write cycle time can be shortened.

The illustrated buffer preferably also includes a pair of active hold circuits that prevent the buffer from sensing further data input when the associated decoder is inactive. The first holding circuit includes transistors 172, 174, 176,
178, 180, 182, 183, and other holding circuits include transistors 184, 186, 190,
192, 194, 196 included.

First, the first holding circuit will be explained. A signal φD is applied to the gates of transistors 174 and 180 to precharge nodes 198 and 200 to a high level. Since the DIN input is provided through lead 202 to the gate of transistor 182, when this DIN input is high, circuit point 20
0 is taken to low level.

The gate of transistor 176 is coupled via lead 136 to node 64 in FIG. 3, its source to node 200, and its drain to node 198. Therefore, assuming this buffer's decoder is activated, node 64 will be high, transistor 176 will be turned on, and node 198 will be low. Therefore, transistor 183 is turned off and its drain (circuit point 1
54) The voltage will be able to change in response to the DIN input on lead 126.

If the decoder associated with the illustrated buffer is disabled, node 64 of that decoder is low, transistor 176 is off, and node 198 is high. Therefore, transistor 183 is turned on and pulls circuit point 154 to ground potential.

Other holding circuits operate in the same manner as above. Therefore, when the decoder associated with the buffer is activated, transistor 196 remains off, only allowing the potential at node 156 to change in response to the input on lead 128. is sufficient. When the buffer decoder is not activated, transistor 19
6 is in the on state, and the circuit point 156 is kept at ground potential.

It is often desirable to write the full potential of _Vcc to a memory location. In this example, some
By driving DIN to 1.4 times _Vcc ,
The other part includes a capacitor 204 coupled to circuit points 154 and 156, respectively, and receiving the signal φ _POF .
206, circuit points 154, 156
It does this by increasing the voltage above _Vcc . With this configuration, when the level of the signal φ _POF rises, the potentials at the circuit points 154 and 156 are driven higher.

Another feature that increases the operating speed of this device is the use of the signal φ _0D2 . As shown in Figure 6, the signal φ _0D2 tracks the signal φ _POF as a whole, but the signal φ _0D2 varies between 7V and 4V, whereas the signal φ _POF varies between 5V and 0V. do. signal φ
Using _0D2 significantly shortens the precharge portion of the nipple cycle, as explained below.

Signal Y _i (lead 54) to V _cc (e.g. 5V)
You will find that it is desirable to drive up to To this end, the voltage on lead 68 is driven above _Vcc , preferably up to 7V, as described below. Referring to FIG. 6, it can be seen that the signal φ _0D2 drops from 7V to 4V just before the signal φ _YC goes high at time t _b . Just before that occurred, signal φ _POF had gone high, pulling node 64 through transistors 104 and 106 to about 4 volts. Therefore, the potentials of the gate and source of transistor 66 are 4V and about 4V, respectively. In this state, transistor 66 is cut off, so circuit point 68
is disconnected from circuit point 64. Therefore, when signal φ _YO goes high and increases the drain voltage of transistor 108, transistor 10
The gate-to-drain capacitance of 8 causes node 68 to rise to approximately 7V, and signal Y _i is driven high. If transistor 66 was not cut off by signal φ _0D2 , circuit point 6
8 has never been disconnected from circuit point 64, and the voltage level at circuit point 88 has not increased, so that signal Y
_i don't think it will be driven to the desired high level.

It will be appreciated that by precharging node 64 to a higher level, transistor 66 can be cut off. However, due to the extra time required to cause such precharging,
The time required to activate the decoder increases. In the illustrated circuit, the activation time of the decoder is shortened, yet increases the level at circuit point 68;
The ability to drive the signal Y _i up to V _cc can also be maintained.

A circuit utilizing signal φ _0D2 in a similar manner is shown in FIG. In this circuit, buffer points 146 and 148 are quickly disconnected from point 64 when signal φ _0D2 drops to 4V, allowing efficient bootstrap operation at points 146 and 148. can.

The device of the invention can be used in a pair of memories each operating in nipple mode. Previously, each such memory was controlled by a clock signal to define precharge cycles and active (read or write) cycles. While the second memory is in precharge mode, the first memory can have a signal that goes low to initiate a nipple read cycle. The clock signal in the first memory can then be driven high to precharge the first memory, and the clock signal in the second memory can be driven low to initiate a nipple read cycle. . Clock signals in two memories,
By shifting in this manner, data bits can be read out for an undetermined amount of time each nipple cycle.

One of the advantages of the decoder and buffer described above is that very little DC power is consumed and that reliable operation can be achieved with a low precharge voltage. Of course, very high speed operation can be achieved by each decoder stopping its operation and activating the next decoder. Also, the fact that each buffer maintains its data output through four nipple cycles allows input data to be read easily and quickly.

[Brief explanation of the drawing]

1 is a block diagram of an apparatus of the present invention for rapidly transferring data between successive memory locations and a data output bus; FIG. 2 is a waveform diagram useful in explaining the apparatus of FIG. 1; and FIG. 1 is a circuit diagram showing an example of the configuration of each decoder in FIG. 1, FIG. 4 is a circuit diagram showing an example of the configuration of each data input buffer in FIG.
3 is an index table relating the signals generated by the circuit of FIG. 3 to the various decoders of FIG. 1, and FIG. 6 is a timing waveform diagram of the various signals in the circuit of FIGS. 3 and 4. 12...Output latch, _A0 to _A3 ...Data latch (sense amplifier), _B0 to _B3 ...Data input buffer, _D0 to _D3 ...Decoder.

Claims (1)

[Claims] 1. In an apparatus for rapidly transferring data between a plurality of successive memory locations of a semiconductor memory and a data output bus, a plurality of decoders D ₀ , D receive an address input and identify the addressed memory location. ₁ , D ₂ , D ₃ and
N amplifiers A ₀ , A ₁ , A ₂ , A ₃ , each associated with each of N successive memory locations in the memory, and a data output bus 1 selectively coupled to said amplifiers.
0, each of said amplifiers A ₀ , A ₁ , A ₂ , A ₃ acting as a latch for storing data associated with N consecutive memory locations defined by a plurality of bits of the address input; The decoder includes the amplifiers A ₀ , A ₁ , and
It consists of N serially connected decoders _{D 0 ,} D ₁ , D ₂ , D ₃ associated with each of A ₂ , A 3 , each of said decoders adapted to receive a selected bit of the address input. each of said decoders D ₀ , D ₁ , D ₂ , D ₃ has an input for receiving a clock signal φP ₀ F;
One of _D0 is responsive to the generation of a clock signal such that when a given set of logic states in the address input bits is decoded, the corresponding amplifier _A0 outputs its stored data onto output data bus 10; Each enabled decoder D ₀ provides a signal to the subsequent next decoder D ₁ such that on the occurrence of the next clock signal, said next decoder D ₁ enables its corresponding amplifier A ₁ to read the data stored therein. Transferring to the data output bus 10, each enabled decoder _D0 is arranged to disable itself such that an N-bit column of data is transferred to the data input bus 10 in response to a single address input. Apparatus for rapidly transferring data between a plurality of successive memory locations of a semiconductor memory and a data output bus, characterized in that: 2. Apparatus according to claim 1, wherein a plurality of input buffers B ₀ , B ₁ , B ₂ , B ₃ are provided for writing input data to a memory location, and each decoder D ₀ , D ₁ , D ₂ , D ₃ are associated with input buffers, and the decoder is responsive to one address input to sequentially select the buffers for writing input data to successive memory locations. A device that does this. 3. The device according to claim 2, wherein each buffer B ₀ -B ₃ has an input terminal 126, 128 for receiving data and an output terminal 130, 132 for coupling the data to the memory. , means 16 for holding data at the output terminals 130, 132 while successive buffers are selected so that writing of data at the output terminals of the buffers can continue while successive buffers are selected.
6,168. 4. A device according to claim 2 or 3, in which each buffer B ₀ -B ₃ is configured such that the buffer is A device characterized in that it includes a suppression circuit 172-183:184-196 for preventing buffering from being felt in data received at an input terminal. 5. The device according to any one of claims 1 to 4, wherein each decoder D ₀ to D ₃ receives a selected address bit and decodes the address bit in a given logic state. Address input circuits 50, 5 that generate output signals Y _i in response to
2, 108, 109, and means 40 for combining the output signal Y _i and outputting the data stored in the data latch.
and a clock signal coupled to receive an output signal and a clock signal generated by the address input circuit, and inhibit the address input circuit from generating further output signals in response to the control signal and the clock signal; A disabling circuit 58, 86, 88, 94, 96, 110 for causing each data to become disabled by itself after being enabled by. 6. The device according to claim 5, wherein each decoder is coupled to the address input circuit, receives the output signal of the previous decoder and the clock signal, and receives the output signal of the previous decoder and the clock signal. an activatable circuit 6 for enabling its address input circuit to generate an output signal in response to the generation of a signal such that each decoder is activated by a previously activated decoder;
0,104,106. 7. The device according to claim 5 or 6, in which the address input circuits 50, 5
2,108,109 are the first circuit points 6, which are precharged to a positive voltage level;
4; transistor means 5 for receiving address input bits and for inhibiting discharge of said circuit point in response to said address bit being in said given logic state;
0,52, and a source coupled to the first circuit point 64;
a gate receiving a second clock signal φ _OD2 and a drain output terminal 6 coupled to a second circuit point 68;
8, a gate coupled to a second circuit point 68, and a third
a second transistor 108 having a drain for receiving a clock signal φ _YO and a source output terminal 54 for generating a control signal, wherein the second clock signal φ _OD2 is at a high level and the first Transistor 66 is turned on, pre-charging said second circuit point 68, and then goes low to substantially cut off said first transistor 6, connecting said first circuit point 64 to said second circuit point. the second clock signal φ _OD2 is selected to be isolated from point 68, and the second clock signal φ OD2 goes high while the first transistor 66 is substantially cut off,
08 to bootstrap said second circuit point 68 to a higher voltage and drive output terminal 54 to a relatively high positive voltage. device to do. 8. A device according to any one of claims 1 to 7 for a semiconductor memory having a read mode and a write mode, in which the data latch is connected to an activated decoder D ₀ , D ₁ , 4 data latches configured to output stored data when selected by D ₂ and D ₃
A ₀ , A ₁ , A ₂ , A ₃ , the device includes four data input buffers B ₀ , B ₁ , B ₂ , B ₃ , each data input buffer having one input terminal for receiving incoming data.
26, 128 and output terminals 130, 132 for coupling data to the memory, and each data input buffer is configured to output the decoder to the memory location when selected by the activated decoder. and the decoder consists of 4 connected in series.
each decoder is associated with one of _the data latches and one of _the input buffers, and each decoder is responsive to its address input to place the memory in _{a read} mode. An apparatus characterized in that it selects a data latch associated with it at a time and an input buffer associated with it when the memory is in a write mode.