JPS60128494A - Smoothing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION This invention relates to smoothing circuits for graphic display devices.

[Prior art]

In a Rask scan type graphic display device, when a diagonal straight line is displayed, it looks like a step, so various methods have been proposed for displaying the straight line smoothly. For example, in the method shown in FIG. 1(1), end dots indicated by white circles are displayed with lower brightness than other dots. In the method shown in Fig. 1 (2), two electron beams are output simultaneously, two dots are arranged above and below in a multi-step luminance distribution according to the slope of the straight line, and each of the two dots is Keep the total brightness constant. A third method is to increase the resolution of the CRT display device itself.

[Problems with conventional technology]

However, the first method has problems in that straight lines appear thick and a memory for changing brightness is required. Furthermore, the second and third methods have the problem of complicating the overall structure and increasing costs.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a smoothing circuit that can smoothly display straight lines with a simple configuration.

[Key points of the invention]

The display data is delayed, and the brightness of half dots at the end of the display figure is controlled based on the delayed display data and the original display data, so that straight lines are displayed smoothly.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 2 to 6. FIG. 2 is a block diagram of the graphic display device. In the figure, 1 is an input device, and input data 2 from this input device 1 is input to an 0PU (central processing unit) 2. A main storage device 3 is connected to this 0PU2, and data (2) is exchanged with it, and a machine clock (2) generated by a clock generator 4 is supplied. Also UP
The display data (2) processed and output by U2 is written into a video memory 5 consisting of a RAM (random access memory). This video memory 5 consists of memories 5A, 5B, and 50 for each color of red, green, and blue, and each memory 5
The display data (■) output in parallel from A to 5C is given to the corresponding shift register 6 provided in three series.The data (■) output from this shift register 6 is
is input to the smoothing circuit 7 provided with 3 series and undergoes smoothing processing, and the 3 series D-
A converter 8 is provided. The])-A converter 8 controls the brightness of the input signal (2) and outputs it as a video signal to the OR'l' display device 9 of the Rusk scan type, thereby displaying a figure.

On the other hand, the click signal ■ outputted by the clock generator 4 is transmitted to the display address control circuit 10 and the synchronization signal generation circuit 1.
1 is input. The display address control circuit 10 outputs an address control signal (2) to the video memory 5 and reads data from the video memory 5. Further, the synchronization signal generation circuit 11 outputs horizontal and vertical synchronization signals to the ORT display device 9. Furthermore, the clock signal (2) outputted from the clock generator 4 is a load clock and a dot clock that are supplied to the shift register 6 and the smoothing circuit 7. Note that the dot clock will hereinafter be referred to as a signal [phase].

FIG. 3 shows the configuration of the three series smoothing circuit 7 described above. A signal (2) in which the display data (2) from the memory 5A (same as 5B and 50) of the video memory 5 is outputted via the shift register 6 is input to the input terminals of the D-type flip-flops 12 and 13.

These flip-flops 12 and 13 respectively pass the dot clock 2 through the inverter 14 or directly to each input terminal 0.
k and is driven. and flip flop 1
2 set output ■ is the oven collector's OR gate 15
In addition, the reset outputs are input to the anime/games 16 and 17, respectively. Further, the set output (2) of the ARITUB flop 13 is input to the AND gate 18, and the reset output is input to the AND gate 19.

The signal {circle around (2)} is input to the AND gate 18 via the inverter 20 which is input to the AND gate 19 . The output of AND gate 18 is OR gate 15, AND gate 17
The output of the AND gate 19 is input to the OR gate 15.

Then, the output (■) of the OR gate 15 is sent to the D-A converter 8 as a signal delayed by half a dot from the signal (1), and the outputs of the (1) and (16) and (16) and (17) gates are both input to the OR gate 21 as a brightness control signal (D). -A converter 8. In other words, the signal (2) and the signal (2) constitute the signal (2).

FIG. 4 shows the configuration of three systems of DA converters 8.

The above signal ■ is connected to the NPN transistor Tr via the resistor RB.
The signal (2) is also connected to the OR gate 23 of the oven collector via the inverter 22. On the other hand, a voltage Vac is applied via a resistor RD to a switch SW whose one end is grounded. This switch SW is used to adjust brightness for smoothing, and the other end is connected to the OR gate 23, and is also commonly connected to a video amplifier (path shown) for all three systems. Also, or gate 23
The output of is connected to the base of the transistor Tr via resistors R and o. A resistor RA is connected between the base and the cap of the transistor Tr, and a resistor R1 is connected to the emitter of the transistor Tr.
is grounded through. And the collector has a voltage V c
c is supplied. The emitter output of transistor Tr is sent via capacitor C to OR'I' display device 9. Therefore, the resistance value of the resistors RB and RQ is RB (
It is Ra.

Next, the operation of the above embodiment will be explained with reference to FIGS. 5 and 6. Assuming that a straight line is to be drawn on the screen of the CRT display device 9, the coordinate data of the starting and ending points of the straight line to be drawn is input from the input device 1.

0PU2 calculates straight line data to be drawn based on the coordinate data, and writes it into each of the red, green, and blue memories 5A, 5B, and 50 of the video memory 5. For example, if you want to display a straight line in red, write straight line data to the red memory 5A, if you want to display it in green, write it to the edge memory 5B, and if you want to display it in white, write straight line data to all memories 5A, 5B, and 5C. It's crowded. The display data from the video memory 5 is output word by word to the shift register 6 in accordance with the dot clock, and is sent out from the shift register 6 to the smoothing circuit 7 bit by bit in accordance with the dot clock. Therefore, as shown in FIG. 5, 9 bits of display data
As an example, if this "00
The display data ``0111000'' is connected to the flip-flop 13 that reads data at the rising edge of the dot clock ``■'' and the inverter 14, so the display data ``is a dot clock ``.
Since it is input to the flip-flop 12 which reads data at the falling edge of A signal [phase] delayed by 0 times and a signal ■ delayed by 117 times are obtained. Therefore, the AND gate 19 that inputs the data ■ and the mutual output (declaration) of the 7-lip 70 tube 13 outputs a signal ■ as shown in FIG. 5, and the AND gate 18 that inputs the data and the signal ■ Signals (■) shown in are output respectively. Therefore, the OR gate 15 outputs a waveform (2) obtained by extending the data (2) by one clock, and the OR gate 21 outputs a pulse (2) for half a clock after the leading and trailing ends of the data (2). These signals ■,
(2) is input to the DA converter 8. This DA converter 8
, the output terminal of the OR gate 23 is connected to ■, and the transistor 4 is
Assuming that the base of the Tr is ■, the potentials of points ■ and @ with respect to signals ■ and [F] and the output signal ■ are as shown in the following table.

Therefore, for the display data originally displayed as shown in Fig. 6(a), half-brightness display is obtained with half dots at the front and rear ends of each display data as shown in Fig. 6(b). The diagonal straight lines are displayed smoothly without becoming step-like. Furthermore, when the switch sw is turned off, the half-dot display is displayed at full brightness.

Note that this smoothing process may or may not be necessary, but it may be changed by a switch or by a program, or if the dots are lined up diagonally as shown in Figure 6(a). It may also be possible to control the smoothing process to be performed automatically when the smoothing process is performed.

Further, in the above embodiment, the case where a straight line is displayed has been explained as an example, but the present invention is not limited to this and can be applied to the case where a curved line or a circle is displayed.

〔Effect of the invention〕

As described in detail above, according to the present invention, smoothing can be achieved with a simple circuit without providing a special memory for smoothing. Moreover, this has the effect that straight lines do not appear thick.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional linear display, FIG. 2 is a system diagram of a graphic display device according to an embodiment of the present invention, and FIG.
The figure is a detailed circuit diagram of the smoothing circuit 7, and Figure 4 is D-A.
FIG. 5 is a detailed circuit diagram of the converter 8, FIG. 5 is a waveform diagram explaining the operation, and FIG. 6 is a diagram showing an example of a linear display according to the present invention. 1...Manual power device, 2...OPU, 4.
... Clock generator, 5 ... Video memory, 6 ... Shift register, 7 ...
...Smoothing circuit, 8...D-A converter,
9...OR'['Display device 110...°°. Display address control circuit, 12.13...D-type flip 70 tube, Tr...transistor, RA
%RBN几0...Resistance, SW...Switch. Patent applicant Casio Computer Co., Ltd. Figure 1 Figure 3 Figure 4 Figure 5 ((b)

Claims (1)

[Claims] a delay circuit that delays display data supplied in synchronization with the dot click; a pulse creation circuit that creates a pulse with a cow dot clock width based on the delayed display data output from the delay circuit and the display data; A smoothing circuit comprising: a brightness control circuit that controls brightness during a half-dot period based on a pulse output from the pulse generating circuit, and is configured to control brightness of an end half-dot of display data.