JPS6012749A - Manufacture of carrier tape - Google Patents

Manufacture of carrier tape

Info

Publication number
JPS6012749A
JPS6012749A JP58120534A JP12053483A JPS6012749A JP S6012749 A JPS6012749 A JP S6012749A JP 58120534 A JP58120534 A JP 58120534A JP 12053483 A JP12053483 A JP 12053483A JP S6012749 A JPS6012749 A JP S6012749A
Authority
JP
Japan
Prior art keywords
substrate
lead
electrode
carrier tape
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58120534A
Other languages
Japanese (ja)
Inventor
Isamu Kitahiro
北広　勇
Kenzo Hatada
畑田　賢造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58120534A priority Critical patent/JPS6012749A/en
Publication of JPS6012749A publication Critical patent/JPS6012749A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Abstract

PURPOSE:To obtain the projected electrode of a lead easily and with good yield by a method wherein, when the projected electrode is formed on the Sn plated Cu lead supported by the titled tape, an Au projected lead is previously provided on another substrate, and then the Au electrode is transcribed to the lead by heat treatment after the lead is made to abut against the another substrate. CONSTITUTION:A conductive layer 22 is adhered on the substrate 21 made of metal, etc. and covered with a resin layer 23 absorbing laser beams, and apertures 26 and 26' are bored by the irradiation of the layer 23 with laser beams 25 from a guide 24 by corresponding to the projected electrodes 27' desired for transcription. Next, the Au projected electrodes 27 are formed in these apertures 26 and 26', and the Cu leads 29 Sn plated supported by the carrier tape 28 are positioned above them. Thereafter, the electrode 27 is positioned to a fixed position of the lead 29 and then transcribed to the lead 29 by heating after they are made to abut againt each other, and accordingly the desired projected electrodes 27' are obtained.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は近年高密度実装のために実用化が図られている
フィルムキャリヤ方式による半導体デバイスの組立等に
用いるキャリヤテープに関連し、突起電極付キャリヤテ
ープの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a carrier tape used in the assembly of semiconductor devices using a film carrier method, which has been put into practical use for high-density packaging in recent years, and relates to a carrier tape with protruding electrodes. The present invention relates to a method for manufacturing a tape.

従来例の構成とその問題点 従来、半導体デバイス組立の主流は２６μｍφの金属細
線を用いたワイヤボンディング法であったが、近年ＬＳ
Ｉの発展とともに電極数が増大、さらには高密度実装が
強く要求される中にあって一部ギヤングボンディングの
できるフィルムキャリヤ方式が有望視されている。現在
実用化されているフィルムキャリヤ方式は、ＬＳＩ上の
ポンディングパッド上に予かしめ、高さ２０μｍ程度の
全突起電極が形成されたものに錫メッキした銅す−ドを
一致させて加熱、加圧し接合するものである。Conventional structure and its problems Conventionally, the mainstream method for assembling semiconductor devices has been the wire bonding method using thin metal wires of 26 μmφ, but in recent years LS
With the development of I, the number of electrodes has increased, and there is a strong demand for high-density packaging, so a film carrier system that can partially perform gigantic bonding is viewed as promising. The film carrier method that is currently in practical use is to heat and heat a tin-plated copper board that is pre-swaged onto a bonding pad on an LSI, on which all protruding electrodes with a height of about 20 μm are formed. It is a type of pressure bonding.

この方式では、予かしめＬＳＩのポンディングパッド上
に全突起電極を必要とするため、ユーザーにとってＬＳ
Ｉ選択が制限される不都合があった。この点を解決する
ために第１図に示すような、突起、電極付キャリヤテー
プが提案された。以下、第１図により従来の突起電極付
キャリヤテープを説明する。第１図において１は樹脂フ
ィルム、２はデバイスを収納するだめの貫通孔、３は銅
箔、４．５，６はホトレジストで銅箔エツチング時のマ
スク、６は突起電極形成のだめのマスク、７は片面から
銅箔厚さあ半分までエツチングする領域、８は領域７に
対応しエツチングされた領域、９は突起として残った部
分、１０はＬＳＩ等のデバイス、１１はポンディングパ
ッドである。This method requires all protruding electrodes on the bonding pads of the pre-swaged LSI, so it is difficult for the user to
There was an inconvenience that I selection was limited. To solve this problem, a carrier tape with protrusions and electrodes as shown in FIG. 1 was proposed. Hereinafter, a conventional carrier tape with protruding electrodes will be explained with reference to FIG. In Fig. 1, 1 is a resin film, 2 is a through hole for storing a device, 3 is a copper foil, 4, 5 and 6 are photoresist masks for etching the copper foil, 6 is a mask for forming protruding electrodes, and 7 A region is etched from one side to half the thickness of the copper foil, 8 is an etched region corresponding to region 7, 9 is a portion remaining as a protrusion, 10 is a device such as an LSI, and 11 is a bonding pad.

まず、ポリイミド等の耐熱性樹脂フィルムのテープ１を
準備し、前記テープの所定位置にデバイスを収納するだ
めの貫通孔２を形成する（第１図Ａ）０次に前記テープ
１上に銅箔３を接着する（第１図Ｂ）。ついで、第１図
Ｃの如く、テープ１上の銅箔３で残すべき領域にホトレ
ジストパターン４，５．６を形成する。First, a tape 1 made of a heat-resistant resin film such as polyimide is prepared, and a through hole 2 for storing a device is formed in a predetermined position of the tape (Fig. 1A).Next, a copper foil is placed on the tape 1. 3 (Figure 1B). Then, as shown in FIG. 1C, photoresist patterns 4, 5, and 6 are formed on the tape 1 in areas to be left with the copper foil 3.

このとき、４，５は銅リード形成のだめのレジストパタ
ーン、６は突起部形成のためのレジストパターンである
。この状態で銅箔３をエツチングすると、リードが形成
されるとともに、８に示す凹部がリード上に形成される
（第１図Ｄ）。９は突起部でＬＳＩのポンディングパッ
ドと接続するために金メッキされる。第１図ＥはＬＳ１
１０’（ｚボンディングした状態である。ポンディング
パッド１１は通常のワイヤボンディングではアルミで良
いが、第１図に示す方式では、ポンディングパッド上に
薄い金の蒸着層を必要とする。突起電極９と金蒸着膜を
形成したポンディングパッド１１との接合は（金−金）
熱圧着による。At this time, 4 and 5 are resist patterns for forming copper leads, and 6 is a resist pattern for forming protrusions. When the copper foil 3 is etched in this state, a lead is formed and a recess shown at 8 is formed on the lead (FIG. 1D). Numeral 9 is a protrusion and is plated with gold for connection to a bonding pad of the LSI. Figure 1 E is LS1
10' (Z-bonded state. The bonding pad 11 may be made of aluminum in normal wire bonding, but the method shown in FIG. 1 requires a thin vapor deposited layer of gold on the bonding pad. Protruding electrode 9 and the bonding pad 11 on which a gold vapor-deposited film is formed (gold-gold).
By thermocompression bonding.

この方法ではボンディング条件を厳密に制御し、アルミ
パッド上を清浄にすることができれば、通常のワイヤボ
ンディング用ＬＳＩチップが使用できるためチップ選択
の範囲が広くなる。゛しかじながら、第１図Ａ−Ｄに示
した如く、突起電極形成のために複雑な工程、特にＣの
フォト工程及びエツチング工程を必要とする上、エツチ
ング速度を厳密に制御しなければ凹部８の制御ができず
キャリヤテープの歩留りは極めて低い。In this method, if the bonding conditions can be strictly controlled and the top of the aluminum pad can be kept clean, ordinary LSI chips for wire bonding can be used, which widens the range of chip selection. However, as shown in FIGS. 1A to 1D, the formation of protruding electrodes requires complicated processes, especially the photolithography process and etching process shown in C, and if the etching rate is not strictly controlled, the recesses will form. 8 cannot be controlled and the yield of carrier tape is extremely low.

発明の目的 本発明の目的はこのような従来の問題に鑑み、容易かつ
歩留り良く突起電極を先端部に有するキャリヤテープの
製造方法’ｆｒｏｍ供することにある。OBJECTS OF THE INVENTION In view of these conventional problems, it is an object of the present invention to provide a method for manufacturing a carrier tape having a protruding electrode at its tip easily and with high yield.

発明の構成 本発明は予かしめ別基板に金等の突起電極を形成してお
き、通常のフィルムキャリヤ方式でツメル使用するテー
プキャリヤのリード先端に前記突起電極を転写する方式
において、主として突起電極を形成する方法に関するも
のである。即ち、本発明は基板上に絶縁膜を形成しレー
ザビーム等で前記絶縁膜に転写用突起電極形成用のメッ
キ窓を開孔するものである。さらに、本発明は単位領域
内は前記レーザビームを移動させ、単位領域間は基板載
置台を移動させることによシ大面積の基板全域にわたり
効率よくかつ精度よく開孔加工する方法を含むキャリヤ
テープの製造法である。Structure of the Invention The present invention mainly involves forming protruding electrodes made of gold or the like on a separate substrate in advance and transferring the protruding electrodes to the lead tips of tape carriers that are used in a normal film carrier method. It relates to a method of forming. That is, in the present invention, an insulating film is formed on a substrate, and a plating window for forming a projection electrode for transfer is formed in the insulating film using a laser beam or the like. Furthermore, the present invention provides a carrier tape including a method for efficiently and accurately forming holes over the entire area of a large-area substrate by moving the laser beam within a unit area and moving the substrate mounting table between unit areas. This is the manufacturing method.

実施例の説明 第２図は本発明の一実施例に関る製造法を部分的に拡大
した断面図で示したものである。第２図において、２１
は基板、２２は導電層（但し、基板として金属板を用い
ても良い。）、２３は絶縁層、２４はレーザ光を導くガ
イド、２６はレーザ光、２６は絶縁層に形成された開孔
、２７はメッキにより形成された金の突起電極、２８は
キャリヤテープ、２９はキャリヤテープのリードで錫メ
ッキされた銅リードである。DESCRIPTION OF EMBODIMENTS FIG. 2 is a partially enlarged sectional view showing a manufacturing method according to an embodiment of the present invention. In Figure 2, 21
22 is a substrate, 22 is a conductive layer (however, a metal plate may be used as the substrate), 23 is an insulating layer, 24 is a guide for guiding laser light, 26 is a laser beam, and 26 is an opening formed in the insulating layer. , 27 is a gold protrusion electrode formed by plating, 28 is a carrier tape, and 29 is a tin-plated copper lead of the carrier tape.

第２図Ａは表面が導電層２２である基板２１を示してい
る。前記基板２１上にレーザ光を吸収する樹脂膜２３を
塗布する（第２図Ｂ）。次にレーザ光２６で前記基板２
１上の所定部分の樹脂２３を焼き取ると開孔２６が形成
される。２６から２６′への移動はレーザ光を導くガイ
ドとシャッター（図示せず）を同期させて行なえば良い
（第２図Ｃ）。FIG. 2A shows a substrate 21 having a conductive layer 22 on its surface. A resin film 23 that absorbs laser light is applied onto the substrate 21 (FIG. 2B). Next, the substrate 2 is
When a predetermined portion of resin 23 on 1 is burned off, an opening 26 is formed. The movement from 26 to 26' can be carried out by synchronizing a guide for guiding the laser beam and a shutter (not shown) (FIG. 2C).

次に第２図りに示す如く、導電層２２を一方の電極とし
て金メッキすれば、金の突起電極２７が容易に形成され
る。金の突起電極２７とテープキャリヤ２８のり一部２
９を位置合ぜし、加熱すれば、リード先端に金の突起電
極２７′が転写される（第２図Ｅ）。本発明によれば、
開孔２６の形成のだめのマスク、露光装置、現像装置、
エツチング装置が全く不要となる。Next, as shown in the second diagram, by gold plating the conductive layer 22 as one electrode, a protruding gold electrode 27 can be easily formed. Gold protruding electrode 27 and tape carrier 28 glue part 2
9 is aligned and heated, a protruding gold electrode 27' is transferred to the tip of the lead (FIG. 2E). According to the invention,
A mask for forming the openings 26, an exposure device, a developing device,
No etching device is required at all.

一般に第２図の基板２１上の開孔２６は、工程Ｅで作ら
れた突起電極付テープキャリヤがボンディングすべき半
導体デバイス例えばＬＳＩのポンディングパッドと精確
に１対ＩＫ対応していなければならない。即ち、第２図
の基板２１は大面積の中には１個のＬＳＩのポンディン
グパッドに相当する開孔を単位とし、その単位が多数個
整列した状態が実現される。In general, the openings 26 on the substrate 21 in FIG. 2 must have an exact one-to-one IK correspondence with the bonding pads of a semiconductor device, such as an LSI, to which the tape carrier with protruding electrodes made in step E is to be bonded. That is, in the large area of the substrate 21 in FIG. 2, a state in which a large number of holes corresponding to one LSI bonding pad are arranged is realized.

第３図に開孔を有する基板の一部を平面図で示しだ。第
３図において２１は基板、３２は単位区画、３３は開孔
である。図より明らかな如（ＩＣのウェル−に例えれば
３２は１チツプであり、３３はポンディングパッドであ
る。図では１チツプ１２パツドの例を示したが、パッド
の数は特に制限されるものではない。このような基板上
に金の突起電極を形成し、テープキャリヤのリードに転
写する場合、単位区画３２内の開孔に関しては相対位置
関係は精度を必要とする。一方、単位区画間に関しては
それ程ピッチ精度を必要としない。いずれにせよ、リー
ドと突起電極の接合時には位置合せを必要とする。本発
明では開孔部をレーザのような商エネルギービームで行
うことが特徴であるが、第３図の如き平面配置の基板を
作る加工法としては第４図に示す方法が望ましい０第４
図において、４１は載置台２１は基板、２３は絶縁層、
４４．４４’はレーザビームの位置、４６は開孔、４６
は単位区画、４７はレーザビームの移動量、４８は単位
区画が複数個形成される場合のピッチである。図かられ
かる如く、単位区画内の開孔加工は４７に示すレーザー
ビームの移動により行ない、１単位区画内の加工が終了
すれば、ピッチ４８で載置台４１を移動させた抜法の単
位区画内の加工を行なえば良い。FIG. 3 shows a plan view of a part of the substrate having an opening. In FIG. 3, 21 is a substrate, 32 is a unit section, and 33 is an opening. As is clear from the figure (if compared to an IC well, 32 is one chip and 33 is a bonding pad. The figure shows an example of 1 chip and 12 pads, but the number of pads is particularly limited. When forming gold protruding electrodes on such a substrate and transferring them to leads of a tape carrier, the relative positional relationship of the openings within the unit sections 32 requires precision. However, pitch accuracy is not required as much as that.In any case, alignment is required when joining the lead and the protruding electrode.The feature of the present invention is that the hole is formed using a quotient energy beam such as a laser. , the method shown in Fig. 4 is preferable as a processing method for producing a substrate with a planar arrangement as shown in Fig. 3.
In the figure, 41 is the mounting table 21 as a substrate, 23 is an insulating layer,
44.44' is the position of the laser beam, 46 is the opening, 46
is a unit section, 47 is the amount of movement of the laser beam, and 48 is a pitch when a plurality of unit sections are formed. As can be seen from the figure, hole machining within a unit section is performed by moving the laser beam shown at 47, and once the machining within one unit section is completed, the unit section of the drawing method is moved by moving the mounting table 41 at a pitch of 48. All you have to do is process the inside.

発明の効果 本発明の製造方法によれば、高価な設備・治具例えば、
マスク、マスク合せ装置、現像装置エツチング装置が不
要であり、それに伴い複雑な工程も不要となる。さらに
は、開孔の加工法において１単位区画内の移動と単位区
画間の移動を各々加工ヘッド（実施例ではレーザービー
ム）と載置台に分割したため、高速化が可能で、かつ高
精度が期待できる。Effects of the Invention According to the manufacturing method of the present invention, expensive equipment and jigs, for example,
A mask, a mask alignment device, a developing device and an etching device are not required, and accordingly, complicated steps are also not required. Furthermore, in the hole machining method, movement within one unit section and movement between unit sections are divided into the processing head (laser beam in the example) and the mounting table, making it possible to increase speed and expect high accuracy. can.

【図面の簡単な説明】 第１図Ａ〜Ｅは従来の突起電極付テープキャリヤを説明
する工程図、第２図Ａ−Ｅは本発明の製造工程の一実施
例の工程図、第３図は本発明により製造される基板の概
略図、第４図は本発明の製造工程における基板加工法を
示す図である０２１・・・・・・基板、２２・・・・・
・導電層、２３・・・・・・絶縁層、２６・・・・・・
レーザ光、２６・・・・・・開孔、２７・・印・全突起
電極、２８・・・・・キャリヤテープ、３２・・・・・
・単位区画、３３・・・・・・開孔、４１・・・・・・
載置台、４４゜４４＜・・・・・レーザ位置、４８・・
・・・・ピッチ。 第１図 １ 第２図 ？２ １ ３ 第３図 ？ｌ[Brief Description of the Drawings] Figures 1A to 1E are process diagrams explaining a conventional tape carrier with protruding electrodes, Figures 2A to 2E are process diagrams of an embodiment of the manufacturing process of the present invention, and Figure 3 is a schematic diagram of a substrate manufactured according to the present invention, and FIG. 4 is a diagram showing a substrate processing method in the manufacturing process of the present invention.021...Substrate, 22...
・Conductive layer, 23... Insulating layer, 26...
Laser light, 26... Opening, 27... Mark/all protruding electrodes, 28... Carrier tape, 32...
・Unit section, 33... Opening, 41...
Mounting table, 44°44<...Laser position, 48...
····pitch. Figure 1 Figure 2? 2 1 3 Figure 3? l

Claims (1)

【特許請求の範囲】[Claims] （１）少なくとも表面が導電層である基板上に絶縁層を
形成する工程、前記基板の所定位置に高エネルギのビー
ムを照射して前記絶縁層の一部を除去し開孔を設ける工
程、前記基板上の導電層を一方の電極として前記開孔部
より突出した突起電極をメッキで形成する工程、金属リ
ードの先端を前記突起電極に一致させて圧接し、前記突
起電極を前記金属リードに転写する工程を有することを
特命　、とするキャリヤテープ製造方法。 （掲　レーザ・ビームを用いて絶縁層の一部を除去し、
開孔を設けることを特徴とする特許請求の範囲第１項記
載のキャリヤテープ製造方法。 （碕　複数個の開孔を設けるべき箇所を含む単位領域が
複数個集合してなる基板に開孔を形成するに際し、前記
単位区画内の開孔加工は高エネルギビームの移動により
行ない、前記単−位区画間の移動は前記基板を塔載した
載置台により行なうことを特徴とする特許請求の範囲第
１項記載のキャリヤテープ製造方法。(1) A step of forming an insulating layer on a substrate whose surface is at least a conductive layer, a step of irradiating a high-energy beam to a predetermined position of the substrate to remove a part of the insulating layer and forming an opening; A step of forming a protruding electrode protruding from the opening with the conductive layer on the substrate as one electrode by plating, aligning the tip of a metal lead with the protruding electrode and pressing it into contact with the protruding electrode, and transferring the protruding electrode to the metal lead. A carrier tape manufacturing method specially designed to include a process of. (Remove part of the insulating layer using a laser beam,
2. A method for manufacturing a carrier tape according to claim 1, characterized in that apertures are provided. (Saki) When forming holes in a substrate made up of a plurality of unit regions including locations where a plurality of holes should be formed, the hole processing in the unit section is performed by moving a high-energy beam, and 2. The carrier tape manufacturing method according to claim 1, wherein the movement between the two position sections is carried out using a mounting table on which the substrate is mounted.
JP58120534A 1983-07-01 1983-07-01 Manufacture of carrier tape Pending JPS6012749A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58120534A JPS6012749A (en) 1983-07-01 1983-07-01 Manufacture of carrier tape

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58120534A JPS6012749A (en) 1983-07-01 1983-07-01 Manufacture of carrier tape

Publications (1)

Publication Number Publication Date
JPS6012749A true JPS6012749A (en) 1985-01-23

Family

ID=14788660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58120534A Pending JPS6012749A (en) 1983-07-01 1983-07-01 Manufacture of carrier tape

Country Status (1)

Country Link
JP (1) JPS6012749A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5786239A (en) * 1995-09-20 1998-07-28 Sony Corporation Method of manufacturing a semiconductor package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5786239A (en) * 1995-09-20 1998-07-28 Sony Corporation Method of manufacturing a semiconductor package
US5982033A (en) * 1995-09-20 1999-11-09 Sony Corporation Semiconductor chip package

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