JPS60127485A - Time signal clock - Google Patents

Time signal clock

Info

Publication number
JPS60127485A
JPS60127485A JP23573083A JP23573083A JPS60127485A JP S60127485 A JPS60127485 A JP S60127485A JP 23573083 A JP23573083 A JP 23573083A JP 23573083 A JP23573083 A JP 23573083A JP S60127485 A JPS60127485 A JP S60127485A
Authority
JP
Japan
Prior art keywords
output
circuit
time signal
contact piece
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23573083A
Other languages
Japanese (ja)
Other versions
JPS6260670B2 (en
Inventor
Yoshihito Owa
大輪 義仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seikosha KK
Original Assignee
Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seikosha KK filed Critical Seikosha KK
Priority to JP23573083A priority Critical patent/JPS60127485A/en
Publication of JPS60127485A publication Critical patent/JPS60127485A/en
Publication of JPS6260670B2 publication Critical patent/JPS6260670B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G04HOROLOGY
    • G04CELECTROMECHANICAL CLOCKS OR WATCHES
    • G04C21/00Producing acoustic time signals by electrical means
    • G04C21/04Indicating the time of the day
    • G04C21/12Indicating the time of the day by electro-acoustic means

Landscapes

  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • General Physics & Mathematics (AREA)
  • Electromechanical Clocks (AREA)

Abstract

PURPOSE:To enable accurate time signal by dispensing with a contact point of an accurate time to simplify constitution and to enhance reliability, by detecting the output from a contact point for detecting a time signal number, when said output is changed over, to start time signal. CONSTITUTION:A contact piece A is elastically contacted with two lines of plural electrodes ES1-ES4 and EC1-EC3 formed on a base plate to bring said electrodes to a continuity state while a moving apparatus connects the contact piece A to the rotation of a clock to rotate the same and is slid so that the electrode brought to a continuity state is changed over at a just hour. A pulse generating circuit PG1 supplies pulses P1-P3 shifted in a phase to the electrodes EC1-EC3 and an output circuit EN1 receives outputs from the electrodes ES1- ES4 to output a signal for showing the display position of the clock. A time signal apparatus N starts the just hour indication in the time signal number by a comparison circuit CM generating a time signal starting signal when the electrode brought to a continuity state by the contact piece A is changed over and the output of the circuit EN1.

Description

【発明の詳細な説明】 本発明は報時時計に関するものでるる。[Detailed description of the invention] The present invention relates to a time signal clock.

例えば、機械的なアナログ表示式の報時時計において、
時針に連動して回転する円板に1〜12時の@コードを
表わす4ビツトのパターン電極を形成しこのパターン電
極上を4木の接片を摺動させて表示時刻を検出するもの
かめる。これvcよると、接片のチャタリングを考鳳し
て、正時より少し前にこの正時のコード出力が得られる
ようにパターン電極を形成してりる。そして分針に連動
して毎正時に閉じる接点を設け、この接点1g号を報時
スタート信号として用いている。
For example, in a mechanical analog display time signal clock,
A 4-bit pattern electrode representing the @ code from 1 to 12 o'clock is formed on a disc rotating in conjunction with the hour hand, and a 4-bit contact piece is slid on this pattern electrode to detect the displayed time. According to this VC, the pattern electrode is formed so that the code output at the hour can be obtained a little before the hour, taking into account the chattering of the contact piece. A contact is provided which closes every hour on the hour in conjunction with the minute hand, and this contact No. 1g is used as a time signal.

このように報時数構出用の接点と正時接点とを必輩とし
、接点数が多くなるとともに機構が複雑で組立性が悪い
などの欠点があった。
In this way, the contact for setting the time signal and the contact for the hour are required, which increases the number of contacts and has disadvantages such as a complicated mechanism and poor assembly.

そこで本発明は報時数構出用の接点のチャタリングによ
る影響を受けず、そのために上記接点からの出力がI;
I]シ換わったときにこれを検出して報時をスタートさ
せること1r(、l:す、正時の接点を不要としたもの
でめる。
Therefore, the present invention is not affected by the chattering of the contact for setting the time signal, and therefore the output from the contact is I;
I] Detecting this when the hour change occurs and starting the time signal.

以下本発明の一実H1y+、1を図面に基づいて説明す
る。第1図において、円板Dvcに同心円状[2列に’
1ili数の1囁E S+ 〜Ti El 4 、 E
 Ot 〜E O3を形成してろる。八は時針(図示せ
ず。)VC連動して回転する接片で、時針軸BK開固着
て娶る。接片Aの接、壱a1は外側の電極上を摺動し、
接点a2に内側の′電極上を摺動すゐ。この摺動vcよ
って、外側の4種類のN 橙E S t〜KEY、と内
側の6種類のt極E’O+ 〜EO3との導油がとられ
、その組合ぎは1〜12時の位置においてそれぞれ貨な
ジ、この組合ぜを識別するごとにより時針の表示位置を
検出することができるのである。各電極は、接片Aの接
膚が正時丁度において電極の端部に接触する工うに形成
して必る。
Hereinafter, one embodiment of the present invention H1y+, 1 will be explained based on the drawings. In Fig. 1, a concentric circle [in two rows']
1ili number 1 whisper E S+ ~Ti El 4, E
Ot~E O3 is formed. 8 is a contact piece that rotates in conjunction with the hour hand (not shown) VC, and is fixed to the hour hand shaft BK. The contact piece A1 slides on the outer electrode,
Slide on the inner electrode of contact a2. By this sliding vc, oil is introduced between the four types of N orange E S t~KEY on the outside and the six types of t poles E'O+ ~EO3 on the inside, and the combination is at the 1~12 o'clock position. By identifying this combination, the display position of the hour hand can be detected. Each electrode must be formed such that the skin of contact piece A contacts the end of the electrode at exactly the hour.

Cの接触の検出を行なって報時を行なう回路構成を示し
たのが第2図で、同図r(おいてQは発揚お工び分周回
路、PG、fiパルス発生回路で、その出力端子P1〜
P3からは順次位相のずれた3系統のパルスが生じ、そ
れぞれバッファF、〜Fa 11介してリード端子c、
−03K供給されている。リード端子01〜C3はそれ
ぞれ第1図の電、極EC1〜EOsK接続したものでめ
る。
Figure 2 shows the circuit configuration for detecting the contact of C and reporting the time. Terminal P1~
Three systems of pulses with phase shifts are generated from P3, and are sent to lead terminals c and 11 via buffers F and ~Fa11, respectively.
-03K is supplied. The lead terminals 01 to C3 are connected to the terminals EC1 to EOsK shown in FIG. 1, respectively.

また、リード端子81〜s4は、それぞれ電極ES@−
ES4から引き出しLもので、これらからの出力はバッ
ファF4〜F7を介して出力回路ENIK供給される。
In addition, the lead terminals 81 to s4 each have an electrode ES@-
The outputs from these are supplied to the output circuit ENIK via buffers F4 to F7.

出力回路KN、はエンコーダ等からなシ、パルス発生回
路PG、からのパルスおよびバッファF4〜F7からの
パルスに工って4ビツトの2進コード出力を生じるもの
でりる。
The output circuit KN generates a 4-bit binary code output by processing the pulses from the pulse generating circuit PG and the pulses from the buffers F4 to F7, not from an encoder or the like.

この具体的構成についてに後述する。Ll、L。This specific configuration will be described later. Ll, L.

はラッチ回路、CMは比較回路で、ラッチ回路LLIL
2の内容が不一致のとき出力が7′1″′になる。Mは
O検出回路で、ラッチ回路Llの出力がUのとき出力が
0”になる。Nは報時回路で、ラッチ回路L2の内容に
応じた回数だけ報時音を発生する。dは遅延回路で、ゲ
ート回路G、の出力を僅かに遅延するものである。
is a latch circuit, CM is a comparison circuit, and latch circuit LLIL
When the contents of 2 do not match, the output becomes 7'1"'. M is an O detection circuit, and when the output of the latch circuit Ll is U, the output becomes 0". N is a time signal circuit that generates a time signal a number of times according to the contents of the latch circuit L2. d is a delay circuit that slightly delays the output of the gate circuit G.

第5図に、第2図の出力口1烙EN、の一例を示したも
ので、02〜G 17 uゲート回路で、ゲート回路0
14〜G 17の出力から4ビツトのコード出刃が生じ
る。
FIG. 5 shows an example of the output port 1 EN in FIG.
A 4-bit code edge is generated from the outputs of G14 to G17.

つぎに動作について説明する。Next, the operation will be explained.

第1図の接片Aが図示の状態力・ら時針に連動して回転
しでいき、2時丁度になると接点al+a2がそれぞれ
電極ES2.EOIの端部Vc接触する。そのため第2
図の端子S2+C1間が接片AvL−工って導通さ九る
。そこでパルス発生回路PGIの端子P1からパルスが
発生すると、これがバッファFt、Fse介して出力回
路ENIK供給され、このときのバッファF4〜F7の
出力はそれぞれ(1011)となる。捷1c端子P2 
The contact piece A in FIG. 1 begins to rotate in conjunction with the illustrated state force/ra hour hand, and at exactly 2 o'clock, the contact points al+a2 are connected to the electrodes ES2, ES2, and ES2, respectively. The end Vc of the EOI contacts. Therefore, the second
The terminals S2+C1 in the figure are electrically connected by the contact AvL-. Therefore, when a pulse is generated from the terminal P1 of the pulse generating circuit PGI, it is supplied to the output circuit ENIK via the buffers Ft and Fse, and the outputs of the buffers F4 to F7 at this time are each (1011). Sword 1c terminal P2
.

P3刀・らパルスが発生しても、(−Jl、らはバッフ
ァF4〜F7VCは伝達されず、各出力fi Ll 1
1+に保持される。端子P、からの上記パルスvCLつ
て出力回路KN、からは以下のような出力が生じる。
Even if the P3 pulse is generated, (-Jl, is not transmitted to the buffers F4 to F7VC, and each output fi Ll 1
It is held at 1+. The pulse vCL from the terminal P generates the following output from the output circuit KN.

端子P1刀)らのパルスは、第6図のゲート回路G+o
−G+3vc供給されるとともにバッファF5を介して
ゲート回路G3 、G7 、Gllに供給される。
The pulses from the terminal P1) are sent to the gate circuit G+o in FIG.
-G+3vc and is also supplied to gate circuits G3, G7, and Gll via buffer F5.

そのためケート回路G11の出力が”1″vcな9、他
のゲート回路の出力はIt 01+に保持される。した
がってゲート回路014〜G 17からは2時のコード
出力(0100)が生じる。tfc端子p2 。
Therefore, while the output of the gate circuit G11 is "1"vc9, the outputs of the other gate circuits are held at It01+. Therefore, the 2 o'clock code output (0100) is generated from the gate circuits 014 to G17. tfc terminal p2.

P3からのパルスの発生時Kfi、バッファF4〜F7
の出力が総て“1”に保時されているためゲート回路0
2〜G+3の出力が総て0#、したがってゲート回路0
14〜G1フの出力も総て′0”に保持される。
Kfi when pulse is generated from P3, buffers F4 to F7
Since all the outputs of are kept at “1”, the gate circuit is 0.
All outputs from 2 to G+3 are 0#, therefore gate circuit 0
All outputs from 14 to G1 are also held at '0'.

こうして端子” + P2 、P3からのパルスの発生
ごとに出力回路EN、からはそれぞれ(01oo)、(
oooo)、(oooo)が発生し、ラッチ回路り、に
供給される。このラッチ回路L1 lff−は、パルス
発生回路PG1の端子P4から、端子p、、P2 、P
3からのパルスの発生中において狭幅のパルスが供給さ
れている。したがって端子P1 + P2 、P37)
’らのパルスの発生ごとにおける出力回路Emtの出力
がラッチ回路LtKラッチされる。ラッチ回路り、[2
時のコード出力(0100)がラッチされると、比較回
路CAMVCよってラッチ回路L2の出力(今、前回の
正時でりる1時のコード出力が記憶されている。)(1
000)と比較され、両者が不一致のため出力が′1”
Kなる。−ま7ζ0り全出回路Mの出力も1”になりゲ
ート回路01が1;iり。ゲート回路G、にはパルス発
生回路P0の端子P5から、端子P4からのパルスと位
相のず;h7tパルスを供給してめ9、これがゲート回
路o1を通過−rる。このパルスによってラッチ回路L
1の2時のコード出力がラッチ回路L2 Kラッチされ
るとと%)K僅かに遅れて報時回路Nが動作し、正時の
報時が行なわれる。
In this way, each time a pulse is generated from the terminals ``+P2 and P3, the output circuit EN outputs (01oo) and (01oo), respectively.
oooo) and (oooo) are generated and supplied to the latch circuit. This latch circuit L1 lff- connects terminals P4 of pulse generating circuit PG1 to terminals p, , P2, P
During the generation of pulses from 3, narrow pulses are supplied. Therefore terminals P1 + P2, P37)
The output of the output circuit Emt is latched by the latch circuit LtK every time a pulse from ' is generated. Latch circuit, [2
When the o'clock code output (0100) is latched, the comparator circuit CAMVC outputs the latch circuit L2 (the code output of 1 o'clock from the previous hour is currently stored) (1
000), and since the two do not match, the output is '1'
K becomes. - When the output of the full output circuit M becomes 1'', the gate circuit 01 becomes 1; A pulse is supplied, which passes through the gate circuit o1.This pulse causes the latch circuit L to
When the 2 o'clock code output of 1 is latched by the latch circuit L2K, the time signal circuit N operates with a slight delay of %)K, and the hour is announced.

なお端子P2.P3からのパルスの発生時にラッチ回路
T=+に、(0000)が→ノチされた・場合VCは0
v、出回路(Aの出力がパ0”になりゲート回路G1が
閉じる友め、ラッチ回路L2にはラッチされない。
Note that terminal P2. When the pulse from P3 is generated, (0000) is notched in the latch circuit T=+. If (0000) is notched, VC is 0.
v, the output of the output circuit (A becomes 0'' and the gate circuit G1 closes, so it is not latched by the latch circuit L2.

また一旦、ラッチ回路L2VC2時のコード出力がラッ
チされlヒ後は、ラッチ回路LlK21寺のコード出力
がラッチされ足とき両者が一致するため比較回路CMの
出力が′″u ” l/(:なり、ゲート回路Gl か
らパルスは発生しない、すなわち、ラッチ回路L2に一
旦、2時のコード出力がラッチされた後はつき′の5時
のコード出力がランチ回路Llにラッチされるまで変化
しない。
Also, once the code output from the latch circuit L2VC2 is latched, the code output from the latch circuit LlK21 is latched, and since they match, the output from the comparison circuit CM becomes ``u'' l/(: , no pulse is generated from the gate circuit Gl. That is, once the 2 o'clock code output is latched by the latch circuit L2, it does not change until the 5 o'clock code output is latched by the launch circuit Ll.

なふ゛第1ν10ρ片AとTλ極開にチャタリングが生
じるが、これvCよる悪影昔(・″LゼJら生じないの
でりる。例えば接点aI 、a2が電極RS ’2 +
EC,に徐々に接していくときのチャタリングでは、第
2図の端子Sz、C1間が導通したり非導通になったり
する。導通状態においてパルス発生回路PG1の端子P
4刀工らパルスが発生すれば、2時のコ−1゛がランチ
回路り、にラッチさtして問題は生じない。捷た非導通
状態では(0000>がラッチ回路り、にラッチされる
ため、この場合にも誤動作は生じない。
Chattering occurs between the first ν10ρ piece A and the Tλ polar opening, but this is due to the bad influence caused by vC.
When chattering occurs when the terminal gradually comes into contact with EC, the terminals Sz and C1 in FIG. 2 become conductive or non-conductive. In the conductive state, the terminal P of the pulse generation circuit PG1
If a pulse is generated from the fourth pulse, the 2 o'clock code 1 becomes the launch circuit and is latched, causing no problem. In the broken non-conducting state, (0000> is latched by the latch circuit, so no malfunction occurs in this case as well.

以上のようにして1.接片Aの回転に従って外側の1J
L* K S t −E S 4 と内側1の電極Ec
l〜BC3との導通がとられ、第2図示のマトリクスの
接点が順次閉成していく。これによって出力回路EN、
からは各時のコード出力が順次発生し、これに基づいて
報時回路Nによって表示時刻に対応した回数だけ報時が
行なわれる。
As mentioned above, 1. According to the rotation of contact piece A, the outer 1J
L*K S t -E S 4 and inner 1 electrode Ec
1 to BC3 is established, and the contacts of the matrix shown in the second diagram are sequentially closed. As a result, the output circuit EN,
The code output for each hour is sequentially generated from the code output, and based on this, the time signal circuit N performs the time signal a number of times corresponding to the displayed time.

第4図は、外側に6種類の電極ES5〜E S 10を
形成し、内側に2種類の電極EC4、EO6を形成した
もので、上記と同様に1〜12時の位置においてそれぞ
れ異なった組合せの電極間が導通され、各時が検出され
るものである。し〃・も正時丁度にふ・いて、接点a1
が電極BS5〜gs、oの端部に接触するように形成し
てりる。
In Figure 4, six types of electrodes ES5 to ES10 are formed on the outside, and two types of electrodes EC4 and EO6 are formed on the inside, and similar to the above, different combinations are formed at the 1 to 12 o'clock positions. Conductivity is established between the electrodes, and each time is detected. The switch also turned on exactly on the hour, and contact a1
are formed so as to contact the ends of the electrodes BS5 to gs and o.

この場合には第5図の工つに、パルス発生回路PG2か
ら2系統の位相のずれたパルスを発生し、バッファFR
,F、を介してリード端子C4。
In this case, two systems of phase-shifted pulses are generated from the pulse generation circuit PG2, and the buffer FR
, F, to the lead terminal C4.

OsK供給するリード端子04 、 Os IQそれぞ
れ電極E Ca + E ’:’ 5に接続したもので
める。また電極ES5〜ES、Oはそれぞれリード端子
85〜810を接続してあり、この各端子85 + S
 loはそれぞれバッファF+o−I”tsの入力1則
に接続してめる。バッファFI0=F15の出力に出力
回路EN2に供給してりシ、他の構成は上81と同様で
りる。
Lead terminal 04 for supplying OsK and Os IQ are connected to electrode E Ca + E':' 5, respectively. Further, the electrodes ES5 to ES, O are connected to lead terminals 85 to 810, respectively, and each terminal 85 + S
lo is connected to the input 1 of the buffer F+o-I''ts, respectively.The output of the buffer FI0=F15 is supplied to the output circuit EN2, and the other configurations are the same as in 81 above.

動作は上記の例と同様で、各電極からなるマトリクスの
交点が接片Aによって順次閉成され、バッフ7F+o−
Ftsからのパルス訃工びパルス発生回路PG2がらの
パルスによって出力回路E N 2からは各時を表わす
コード出力が発生し、これに基づいて報時が行なわれる
The operation is similar to the above example, and the intersection points of the matrix made up of each electrode are sequentially closed by the contact piece A, and the buffer 7F+o-
A code output representing each hour is generated from the output circuit E N 2 by the pulse from the pulse generation circuit PG2 from the Fts, and the time is reported based on this.

なお上記の実用例では、電′rf1.全固定して(き接
片を回転させたが、逆に接片を固定しておいて電極側を
回転させるようにしてもよい。
Note that in the above practical example, the electric current 'rf1. Although the contact piece is completely fixed (the contact piece is rotated, it is also possible to fix the contact piece and rotate the electrode side).

以上のように本発明によれば、2列の複数の電極上を時
開の回転に連動して接片を相対的に摺動させて正時丁度
に接片を′gL極に接触させ、一方の列の各市、極に供
給した位相のずれたパルスが、他方の列のどの電極から
生じる〃為に工って時を検出して報時を行なうLつにし
たので、正時を検出する接点で不及となり、2接ですみ
構成的に簡単になるとともに、信頼性が向上し、正確な
報時を行なうことができる。
As described above, according to the present invention, the contact piece is caused to relatively slide on the plurality of electrodes in two rows in conjunction with the rotation of the time opening, and the contact piece is brought into contact with the 'gL pole just on the hour; Since the phase-shifted pulses supplied to each city and pole of one column are generated from which electrode of the other column, the time is detected and signaled by L pulses, so that the hour can be detected. It is possible to use only two contacts, which simplifies the configuration, improves reliability, and allows accurate time reporting.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実画り[1を示した正面図、第2図
は回路構成の一例を示した論理回路図、第3図は第2図
の一部を詳細に示した論理回路図、第4図eユ池の実施
例を示した正面図、a9,5図は第4図の例に訃ける回
路溝底の−yllを示した論理回路図でりる。 )GSI −ES4 、EOI−WCs・・・電極A・
・・接ハ B・・・移動装置 PGI ・・・パルス発生回路 )ち1111 ・・・出力回路 LL 、L2・・ラッチ回路 CM・・・比較回路 ]く・・・機部回路 KS6 ′−EE1o 、EC4+ Bs ・・−’を
極PG2・・パルス発生回路 1菅; N 、・・・出力回路 以上 出願人 株式会社 精 工 舎 代理人 弁理士 最 上 務 第2図 第3図 第4図 10 第5図
Fig. 1 is a front view showing an actual drawing of the present invention [1], Fig. 2 is a logic circuit diagram showing an example of the circuit configuration, and Fig. 3 is a logic circuit diagram showing a part of Fig. 2 in detail. Circuit diagram, FIG. 4 is a front view showing an embodiment of the e-pond, and FIG. ) GSI-ES4, EOI-WCs...electrode A.
...Connection B...Movement device PGI...Pulse generation circuit) 1111...Output circuit LL, L2...Latch circuit CM...Comparison circuit]...Machine section circuit KS6'-EE1o , EC4+ Bs...-' to the pole PG2...Pulse generation circuit 1 tube; N,...Output circuit or above Applicant Seikosha Co., Ltd. Agent Patent Attorney Mogami Figure 2 Figure 3 Figure 4 Figure 10 Figure 5

Claims (1)

【特許請求の範囲】[Claims] 基板上に形成した2列の複数の電極と、各列の電iK連
接しこの弾接した電極間を導通させる接片と、この接片
おLび上記基板のいずれ力・一方を時針の回転に連結し
て回転させ上記接片によって導通される電極が正時VC
おいて切り換わるよりに摺動させる移動装置と、−万の
列の各′電極に順次位相のずれたパルスを供給するパル
ス発生回路と、他方の列の各電極からの出力および上記
パルスを受けて上記時針の表示位置を表わす出力を生じ
る第1の出力回路と、上記接片に裏って導通される電極
が切り横わったとき報時スタート信号を生じる第2の小
力回路と、第1の出力回路力・らの出力VCよって報時
数を指定され上記報時スタート信号に工って正時の報時
を開始する報時装置と71)らなる報時時計。
A plurality of electrodes in two rows formed on a substrate, a contact piece that connects the electrodes in each row and conducts between the elastically contacted electrodes, and any force between this contact piece L and the above substrate, and one of them is used to rotate the hour hand. The electrode connected to and rotated by the contact piece conducts on the hour VC.
a pulse generating circuit that sequentially supplies phase-shifted pulses to each electrode in the -10,000 column, and receives the output from each electrode in the other column and the above-mentioned pulses; a first output circuit that generates an output representing the display position of the hour hand; a second small power circuit that generates an alarm time start signal when the electrode conductive behind the contact piece crosses; 71) A time-reporting clock comprising: a time-reporting device which starts time-reporting on the hour by inputting the number of times to be reported by an output circuit power of 1 and an output VC of .
JP23573083A 1983-12-14 1983-12-14 Time signal clock Granted JPS60127485A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23573083A JPS60127485A (en) 1983-12-14 1983-12-14 Time signal clock

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23573083A JPS60127485A (en) 1983-12-14 1983-12-14 Time signal clock

Publications (2)

Publication Number Publication Date
JPS60127485A true JPS60127485A (en) 1985-07-08
JPS6260670B2 JPS6260670B2 (en) 1987-12-17

Family

ID=16990377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23573083A Granted JPS60127485A (en) 1983-12-14 1983-12-14 Time signal clock

Country Status (1)

Country Link
JP (1) JPS60127485A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62145184U (en) * 1986-03-06 1987-09-12

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62145184U (en) * 1986-03-06 1987-09-12

Also Published As

Publication number Publication date
JPS6260670B2 (en) 1987-12-17

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