JP2516237Y2 - Auxiliary circuit of time signal clock - Google Patents

Description

[Detailed description of the device]

[0001]

This invention has a time code board,
The present invention relates to a timekeeping circuit of a timepiece that emits a timekeeping sound at every hour based on a time code signal from the time code board.

[0002]

2. Description of the Related Art Today, in a timepiece body which emits a percussion sound every hourly time, the time is measured using a time code board, and the number of times is calculated every hour on the hour. A sound generator (for example, Japanese Unexamined Patent Publication No. 52-75365) or a sound generator that produces a beating sound or a melody based on a time code signal from a time code board (for example, The actual number is 62-7096).

In the circuit of these timepieces, as shown in FIG. 7, normally, four detection contacts 11, 12, 13, and 14 in contact with the time code board 10 are connected via a detection resistor 17. Is connected to an H level power supply, and the code contacts arranged concentrically on the time code board 10 are used as the on-potential power supply.
Based on the pattern of the code contacts formed on the time code plate 10 which is connected to a common ground of the level, the time code plate 10 is attached to the hour hand shaft, etc., and rotates once in 12 hours. The time from 1 o'clock to 12 o'clock is represented by a 4-bit signal, and when each detection contact 11, 12, 13, 14 comes into contact with the code contact formed on the time code board 10, L When the detection contact is not in contact with the code contact, the H level off-potential signal is output as the level on-potential signal.
I am trying to input to.

This 4-bit time code signal is generally contacted by the code contacts formed on the time code plate 10 with the respective detection contacts 11, 12, 13, 14 from a few minutes before the hour. The hour signal is input to the time signal circuit 15 as a signal indicating a specific time immediately before the hour, and the hour signal or half-hour signal from the time signal contact 16 is input to the time signal circuit 15. When
In many cases, the time signal circuit 15 is activated by using the hour signal or the half-hour signal as a trigger to cause the speaker 19 to generate a required number of time signal sounds based on the time code signal.

By the way, the time code signal is continuously input to the time signal circuit 15, but when the code contact is missing or dust is attached, the time code signal is output from the time signal contact 16. There is a case where an accurate time code signal is not input when the hour signal is input to the time signal circuit 15, and the time signal circuit 15 may malfunction. Therefore, in order to prevent such malfunction of the time signal circuit 15,
There is also a circuit in which a latch circuit and a comparison circuit are incorporated, the time code signal is read a plurality of times, and the time signal circuit 15 is operated when the read time code signals match (for example, Japanese Patent Laid-Open No. Sho. 56-49976).

[0006]

[Problems to be Solved by the Invention] As described above, the time
Although the time signal circuit using a cable can obtain the time code signal with a small size and a relatively simple structure, as described above, temporary contact failure due to dust, chipping, or bouncing. Occurs, which causes a malfunction in the time signal circuit, and the improvement and modification of the time signal circuit so as not to cause the malfunction has a drawback that the design and manufacture of the time signal circuit becomes difficult.

[0007]

SUMMARY OF THE INVENTION The present invention has a detection terminal connected to each detection contact and one polar terminal connected to a common ground which is an on-potential power source of a time code board. Each of the detection terminals is connected to the polarity terminal through a switch element, and a time clock input to each detection terminal is input.
An auxiliary circuit having an input / output latch circuit for outputting an ON signal for conducting the switch element when the input signal is at the ON potential, and having a timer circuit for setting the input / output latch circuit to the initial state every required time. It will be attached to the time circuit.

[0008]

[Working] The present invention has an input / output latch circuit for outputting an ON signal when the time code signal is at the L level ON potential, and the detection terminal is made conductive by the ON signal. Since it is an auxiliary circuit having a switch element connected to the terminal, when each detection contact comes into contact with the code contact of the time code board and the detection terminal is turned on, the switch element is made conductive. The detection contact can be connected to the polarity terminal, that is, the common ground, and the detection contact can be reliably maintained at the ON potential even when a temporary contact failure occurs between the detection contact and the code contact. .

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, an embodiment of an auxiliary circuit according to the present invention is one in which four detecting contacts 11, 12, 13, 14 which are brought into contact with a time code board 10 are respectively connected. In the auxiliary circuit 20 of the timepiece clock having the detection terminals 21, 22, 23 and 24, and having one polar terminal 25 connected to the common ground used as the ON potential power source of the time code board 10. Yes, the auxiliary circuit 20 includes the four detection terminals 21 and 21.
2, 23 and 24 are respectively connected to the polar terminals 25 via the analog switch elements 31, 32, 33 and 34 of the switch circuit 30.
, And each detection terminal 21, 22, 23, 24
Are connected to the input / output latch circuit 40, respectively.

As shown in FIG. 2, the input / output latch circuit 40 has the same number of RSs as the detection terminals 21, 22, 23 and 24.
The flip-flops 41, 42, 43, 44 and the gate sections 45, 46, 47, 48, and one control circuit section 70, and the four detection terminals 21, 22, 2
3, 24 are connected to the set input terminals of the RS-flip-flops 41, 42, 43, 44 via the gate sections 45, 46, 47, 48, respectively, and the RS-flip-flops 4 are connected.
The Q output terminals of 1, 42, 43, and 44 are connected to the RS-
Detection terminals 21, 22, 2 for inputting code signals to the set input terminals of the flip-flops 41, 42, 43, 44
It is connected to the control input terminals of the respective analog switch elements 31, 32, 33, 34 inserted between 3, 24 and the polar terminal 25.

Further, four RS-flip-flops 4
The reset input terminals of 1, 42, 43, 44 are connected to the K signal output terminals of the control circuit section 70 for outputting the cancel signal, and the detection terminals 21, 22, 23, 24 are also connected.
And the RS-flip-flops 41, 42, 43, 44 are respectively provided with gate sections 45, 46, 47, 48 each having one exclusive-OR circuit 51, 52, 5 respectively.
3, 54 and one AND circuit 56, 57, 58, 59, respectively
Are connected in series, and each of the detection terminals 21, 2 is connected.
2, 23, 24 are connected to the exclusive-OR circuits 51, 52, 53, 54 of the gate sections 45, 46, 47, 48, respectively, and all the exclusive-OR circuits 51, 5 are connected.
The other input terminals of 2, 53, 54 are connected to the polarity terminal 25, and all the other input terminals of the AND circuits 56, 57, 58, 59 are read signal output terminals (hereinafter referred to as M signal) in the control circuit unit 70 described later. Terminal).

The time signal input terminal 26 is connected to the time contact 16 which outputs an hour signal and a half-hour signal every 30 minutes, and the pulse generating circuit 90 is as shown in the time chart of FIG. When an L-level hourly signal or a half-hour signal is input to the A signal, an hourly pulse signal having a predetermined pulse width is output to the B signal based on the hourly signal, etc. Then, a shift pulse circuit is formed so as to output a timing pulse signal having a predetermined pulse width to a C signal, and subsequently to output a set pulse signal having a predetermined width to a D signal and a trigger-pulse signal to an E signal. The hour pulse signal output terminal (hereinafter referred to as B signal terminal) of the pulse generation circuit 90 is provided to the control circuit unit 70, the timing pulse signal output terminal (hereinafter referred to as C signal terminal) and the set pulse signal output terminal (hereinafter D). Signal end The) that timer - connected to the circuit 60, the trigger - the pulse output terminal (hereinafter referred E signal terminal) gate - via preparative circuit 80 trigger - connected to the signal terminals 29.

As shown in FIG. 3, the timer circuit 60 is composed of one timer, an OR circuit, an AND circuit, an inverter, and an RS-flip-flop.
The φ input terminal of 63 is connected to the clock input terminal 27 of the auxiliary circuit 20, and the clock input terminal 27 is connected to the reference signal generating circuit of the clock circuit to input a signal of, for example, 0.5 Hertz. The reset input terminal of -63 is connected to the C signal terminal which is the timing pulse signal output terminal in the pulse generation circuit 90, and the timer-63 counts the clock signal after the reset is released, and after 25 minutes, carries H from signal output terminal to F signal
A pulse timer signal is output, and this carry signal output terminal is connected to the input terminal of the first OR circuit 65 and the control circuit section 70 of the input / output latch circuit 60.

The other input terminal of the first OR circuit 65 is a timing pulse signal output terminal of the pulse generating circuit 90 together with the reset input terminal of the timer-63.
The output terminal of the first OR circuit 65 is connected to the reset terminal of the fifth RS-flip-flop 68 and the input terminal of the fifth AND circuit 67 via the fifth inverter 66. The other input terminal of the AND circuit 67 is connected to the D signal terminal which is the set pulse signal output terminal in the pulse generation circuit 90, and the output terminal of the fifth AND circuit 67 is connected to the set input terminal of the fifth RS-flip-flop 68. However, the Q output terminal of the fifth RS-flip-flop 68 is the control circuit unit 70 in the input / output latch circuit 60.
To connect to.

Therefore, in this timer circuit 60, the timer 63 is reset by the timing pulse signal output from the pulse generating circuit 90 to the C signal, and the fifth R
After the S-flip-flop 68 is once reset, the fifth RS-flip-flop 68 is set by the set pulse signal output to the D signal,
The output is set to the H level and the operation signal is output to the G signal. When the timer-63 of the timer circuit 60 measures 25 minutes and outputs the carry signal as the timer signal to the F signal, the fifth RS-flip-flop 68 is returned to the reset state and the operation signal is output. This operation signal is a timer-63 that counts a predetermined time from the time when the hourly signal or the half-hour signal is input to the auxiliary circuit 10 and the pulse generation circuit 90 outputs the timing pulse signal. The output will be continued while it is being performed.

The control circuit section 70 is composed of two D-flip-flops, an AND circuit and an inverter, and one three-input OR circuit and two-input OR circuit.
The D input terminal of the flip-flop 71 is connected to the Q output terminal of the fifth RS-flip-flop 68 in the timer circuit 60 together with the one input terminal of the second OR circuit 73 in the control circuit section 70, and the first D-flip-flop is connected. The Q output terminal of 71 is connected to the D of the second D-flip-flop 72.
It is connected to an input terminal and one input terminal of a second OR circuit 73 of a three-input type, and the remaining one input terminal of the second OR circuit 73 is connected to the Q output terminal of the second D-flip-flop 72. The output terminal of the second OR circuit 73 is connected to the seventh AND circuit 79 via the sixth inverter 74,
The φ input terminals of the D-flip-flop 71 and the second D-flip-flop 72 are connected to the clock input terminal 27 of the auxiliary circuit 20, and the input terminal of the sixth AND circuit 77 is the positive pulse signal in the pulse generation circuit 90. The B signal terminal which is an output terminal and the Q output terminal of the fifth RS-flip-flop 68 in the timer circuit 60 are respectively connected, and the output terminal of the sixth AND circuit 77 is connected to the third OR circuit 7.
6, the other input terminal of the third OR circuit 76 is connected to the carry signal output terminal of the timer-63 in the timer circuit 60, and the output terminal of the third OR circuit 76 is used as the K signal terminal. 4 in the input / output latch circuit 40
Connected to the reset input terminals of the RS-flip-flops 41, 42, 43, 44, and the seventh inverter 7
8 is connected to the input terminal of the seventh AND circuit 79 in the control circuit section 70, and the output terminal of the seventh AND circuit 79 is used as an M signal terminal for the gate sections 45, 46, 47 and 48.
The first AND circuit 56 to the fourth AND circuit 59
It is connected to each input terminal of each AND circuit.

Therefore, when the hour signal or the half-hour signal is input to the auxiliary circuit 20 and the timer 63 of the timer circuit 60 starts counting the reference signal input from the clock circuit, the control circuit section 70 An operation signal output as a G signal from the timer circuit 60 is input, and the operation signal is passed through the second OR circuit 73 and then made into an L level signal by the sixth inverter 74, and then the seventh AND circuit. The output of 79 is M
The signal is set to the L level to stop the output of the read signal output from the control circuit unit 70 as the M signal, and the gate units 45, 46, 47, 48 in the input / output latch circuit 40 are stopped.
AND circuits 56, 57, 58, 59 of
Inputting the ON potential or OFF potential of the code signal to the set input terminals of the RS-flip-flops 41, 42, 43, 44 and inputting the hourly signal or half-hour signal to the auxiliary circuit 20. The states of the RS-flip-flops 41, 42, 43, 44 at the time of being held are held.

Further, 25 minutes have elapsed after the hour signal or the half-hour signal was input to the auxiliary circuit 20, the timer circuit 6
When the timer signal is output from 0 to F signal, the timer signal passes through the third OR circuit 76, and the timer signal is output to the K signal as a cancel signal. Four RS-flip-flops 41, 42, 4 in the input / output latch circuit 40
When the output of the operation signal output from the timer circuit 60 to the G signal is stopped due to the lapse of 25 minutes, the output signals of the sixth inverter 74 and the seventh inverter 78 are reset. When the output becomes H level, the M signal output from the seventh AND circuit 79 is set at H level to output a read signal, and the read signal causes the four AND circuits of the first and fourth AND circuits 56 to 59 to be output. Open the 1st R
The S-flip-flop 41 to the fourth RS-flip-flop 44 are connected to the detection terminals 21, 22, 23 and 24, that is, the detection contacts 11, 12 and 1 which are brought into contact with the time code board 10.
The voltage of 3 and 14 can be read.

Then, the first RS-flip-flop 41
Through the fourth RS-flip-flop 44 are connected to the respective detection terminals 2
When the set state is brought about by the ON potentials of the code signals input to 1, 22, 23 and 24, the R set state is set.
The S-flip-flop outputs the ON signal with its Q output at the H level, and the switch element connected to the detection terminal to which the ON-potential signal is input is brought into conduction by the ON signal so that the detection terminal and the polarity terminal are connected. Therefore, in the auxiliary circuit 20, a timer signal is output from the timer-circuit 60 in the auxiliary circuit 20. And the RS-flip-flops 41, 42, 43, 4 in the input / output latch circuit 40 by the timer signal.
4 is reset, the input / output latch circuit 40 is set to the initial state, and the output of the ON signal from each RS-flip-flop 41, 42, 43, 44 constituting the input / output latch circuit 40 is stopped, and each analog switch element 31 is , 32, 3
3 and 34 are made non-conductive.

The code formed on the time code board 10
The contact point and each of the detection contacts 11, 12, 13, and 14 are in contact with each other, and any one of the detection contacts 11, 12, 13, and 14 becomes the L level, which is an appropriate H level and L level. When a 4-bit time code signal, which is a combination of on-potential and off-potential, is input to the time signal circuit 15, this time code signal is applied to the auxiliary circuit 20 as well as the detection terminal 21,
Input from 22, 23, 24, and detection terminals 21, 2
Among the detection terminals 2, 23, 24, the detection terminals to which the L level signal which is the ON potential is input are the detection terminals 21, 22, 2
Of the RS-flip-flops 41, 42, 43, 44 in the input / output latch circuit 40 connected from 3, 24 via the gate sections 45, 46, 47, 48, the L level signal is input. The RS flip-flop connected to the detection terminal is switched to the set state.

Therefore, of the RS-flip-flops 41, 42, 43, 44 which constitute the input / output latch circuit 40,
The RS flip-flop connected to the detection terminal to which the time code signal of L level which is the ON potential is input, outputs the ON signal with its Q output as H level, and the ON signal outputs the L level of the L level. The analog switch element inserted between the detection terminal to which the on-potential is input and the polarity terminal 25 is brought into a conductive state, and the detection terminal to which the on-potential is input and thus the detection contacts 11, 12, 13, and 14 L
The leveled detection contact is connected to the common ground not only through the code contact but also through the analog switch element of the auxiliary circuit 20.

As described above, the auxiliary circuit 20 according to the present embodiment.
Are the detection terminals 21, 22, 2 of the auxiliary circuit 20.
3 and 24 are connected to the respective detection contacts 11, 12, 13 and 14, and the polarity terminal 25 is connected to the common ground, and when the detection contacts come into contact with the cord contacts and are connected to the common ground, Since the detection contacts that have changed to the L level among the detection contacts 11, 12, 13, 14 are connected to the common ground through the analog switch element in the auxiliary circuit 20, the detection contacts 11, 12, 13, 14 are temporarily When the detection contacts 11, 12, 13, 14 are changed to the L level by coming into contact with the code contacts, the analog switch elements 31, 32, 3
L of detection contacts 11, 12, 13, 14 via 3, 34
It is possible to maintain the level, and if there is a temporary contact failure between the detection contacts 11, 12, 13, 14 and the code contacts, such as missing code contacts, the detection contacts 11, 12, 1
It is possible to reliably maintain the L levels of 3 and 14, and to always input the time code signal which is a precise 4-bit signal of the H level or the L level to the timing circuit 15.

Further, when the pointer is corrected by manual operation or the like, that is, when the time code board 10 is rotated at a high speed together with the pointer, the hour signal or the half-hour signal continues to the auxiliary circuit 20 in a short time. The pulse generator circuit 90 outputs the set pulse signal to the D signal subsequent to the timing pulse signal output to the C signal.
The RS-flip-flop 68 keeps the set state continuous, and as shown in the time chart of FIG. 6, the G signal is intermittently set to the L level and maintained at the H level.

Therefore, the sixth AND circuit 77 of the control circuit section 70 is opened and the sixth AND circuit 77 is operated by the pulse generation circuit 9
Pass the hourly pulse signal output from 0 to the B signal,
Since this hourly pulse signal is output to the K signal as a cancel signal via the third OR circuit 76, the four RS-flip-flops 41,
42, 43, 44 are reset and the timer circuit 6
Since the G signal from 0 is at the H level, the first D-flip-flop 71 and the second D-flip-flop 72 in the control circuit unit 70 set the Q output to the H level and the G signal is intermittently set to the L level. , This L level signal is the first D
-There is a time delay in transmitting to the Q output of the flip-flop 71 and the second D-flip-flop 72, and the output of the second OR circuit 73 is always at the H level and the sixth inverter
The I signal which is the output of the gate 74 is maintained at the L level, and the M signal which is the output of the seventh AND circuit 79 is always at the L level. Therefore, the first AND of the gate units 45, 46, 47 and 48 is The circuits 56 to the fourth AND circuit 59 are all closed, and the signals from the detection terminals 21, 22, 23 and 24 are blocked from being transmitted to the input / output latch circuit 40.

In the above embodiment, the code contacts of the time code board 10 are connected to the L level power source, and the detection contacts 11 and 1 are connected.
2, 13, 14 are connected to the H level power source through the detection resistor 17 to make the ON potentials of the detection contacts 11, 12, 13, 14 into L level signals. An exclu-sive OR circuit is used in the unit 30,
A time signal circuit 1 which operates by a time code signal in which the code contact is connected to an H level power source and the ON potential is an H level signal.
5 is an auxiliary circuit 20 which can also be connected to 5.

Further, a gate inserted between the E signal terminal for outputting the trigger pulse signal from the pulse generating circuit 90 of the auxiliary circuit 20 in this embodiment and the trigger signal terminal 29.
5, the input terminal of the Schmitt circuit 81 is connected to the illuminance detection terminal 28, the output terminal of the Schmitt circuit 81 is connected to the input terminal of the eighth AND circuit 83, and the output terminal of the eighth AND circuit 83 is connected. The other input terminal is the pulse generator 90
Of the eighth AND circuit 83 is connected to the trigger signal terminal 29 via the inverter 85, and the illuminance detection terminal 28 is connected to the detection resistor 87. If it is connected to the H level power source and the L level power source via the photocell 88, a trigger pulse signal is sent through the gate circuit 80 when the periphery of the watch body is bright. When the surroundings of the timepiece are dark, the gate circuit 80 shuts off the trigger pulse signal. Therefore, the trigger input terminal of the time signal circuit 15 is not connected to the time signal contact 16, By connecting to the trigger signal terminal 29 in place of the time contact 16, it is possible to prevent the time signal sound from being emitted in the dark. Instead of the H level power source of the detection resistor 87, the pulse generation circuit 90 E signal Directly withdrawn from the auxiliary circuit 20, in which can also be sounded broadcast time sound only when similarly bright ambient light when applying the E signal to the detection resistor 87.

[0027]

The auxiliary circuit of the timepiece timepiece according to the present invention is attached to the timepiece timepiece having the timepiece circuit using the time code plate, and the required number of detection terminals are connected to the respective detection contacts. , The polarity terminal can be connected to the common ground which is the on-potential power supply of the time code board to remove the noise of the time code signal and input the accurate time code signal to the time signal circuit. It is an auxiliary circuit that can perform an accurate time signal operation by simply incorporating it into a conventional circuit without modifying and changing the time signal circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing a state in which an auxiliary circuit according to an embodiment of the present invention is connected to a time signal circuit.

FIG. 2 is a diagram showing a circuit configuration of an auxiliary circuit according to the present invention.

FIG. 3 is a diagram showing circuit details of a timer circuit and a control circuit unit in an auxiliary circuit according to the present invention.

FIG. 4 is a time chart showing each signal in the second embodiment of the auxiliary circuit according to the present invention.

FIG. 5 is a diagram showing a modified use example of the auxiliary circuit according to the present invention.

FIG. 6 is a time chart showing each signal when the pointer of the auxiliary circuit according to the present invention is modified.

FIG. 7 is a diagram showing a circuit example of a conventional timepiece clock using a time code board.

[Explanation of symbols]

10 time code plate 11, 12, 13, 14 detection contact 15 time circuit 16 time contact 20 auxiliary circuit 21, 22, 23, 24 detection contact 25 polarity terminal 26 time signal input terminal 27 clock terminal 30 switch Circuit 31, 32, 33, 34 Analog switch element 40 Input / output latch circuit 60 Timer-circuit 65 Delay inversion circuit 70 Control circuit unit 90 Pulse generation circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Toru Tanabe Inventor Toru Tanabe 496 Oaza, Showa-machi, Kita-Katsushika-gun, Saitama Rhythm Watch Industry Co., Ltd. Showa Plant (56) References JP-A-56-49976 (JP, A) JP-A-60-66180 (JP, A) JP-A-62-3690 (JP, A)

Claims (1)

(57) [Scope of utility model registration request] 1. A time signal of a time signal clock which reads a code signal from a time code board by a time signal output at every predetermined time and reports the time based on the code signal. A time signal input terminal connected to the time signal to be input to the time circuit and a required number of detection terminals and time code plates to input the code signal from the time code board. And a polarity terminal connected to the on-potential power supply, which starts a counting operation in response to a time signal input to the time signal input terminal, outputs an operating signal during the counting operation, and
A timer circuit that outputs a timer signal after a certain period of time to end the counting operation, and an on-potential or off-potential code that is input to each of the detection terminals when an operation signal is not input from the timer circuit. The signal is set to the latchable state and the ON potential in the latch data is output to the switch circuit as the ON signal. When the operation signal from the timer circuit is input, the latch data based on the code signal input to each detection terminal is input. -Maintains the data, outputs the latched ON-potential of the latched data to the switch circuit as an ON signal, and
An input / output latch circuit that resets latch data when the time signal or the timer signal is input, and each of the detection terminals are connected to the polarity terminal through a switch element, and an on-potential code signal is connected. And a switch circuit for electrically connecting a switch element connected to the detection terminal to which is input by the ON signal.