JPS60126750A - Cache memory device - Google Patents

Abstract

PURPOSE:To select the write system corresponding to the system environment by providing a selection means for selecting any of a simultaneous write circuit and a sequential write circuit depending on the command of a high-order device. CONSTITUTION:When a CPU1 is a system to process of a batch system, the CPU1 outputs a 0 level signal as a control signal 5. A write data from the CPU1 is transferred to an external storage device 4 as the result that a write data from the CPU1 and a signal of level 1 inverted by a NOT circuit 6 are inputted to an AND circuit 8. Moreover, the write data is transferred to a cache memory section 3 at the same time. When the CPU1 is the time sharing system, the signal 5 goes to level 1. A 0 level signal is inputted from the circuit 6 to the circuit 6 to the circuit 8, resulting that the write data from the CPU1 is transferred only to a memory section 3. After the write data transfer to the device 4 is stored once in the memory section 3, the write data is transferred by an AND circuit 7 when cache memory devices 2 and 5 are both free.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a cache memory device in an external storage system, and more particularly to control of write operations.

[Background of the invention]

In recent years, in computer systems, external storage devices such as magnetic disk devices and magnetic tape devices have been designed to have higher recording densities and larger storage capacities, and the storage capacity per device has increased significantly.

However, in terms of data access time, the main memory in a central processing unit is on the order of several hundred nanoseconds, whereas the seek time and rotational waiting time in magnetic disk devices, for example, are on the order of tens of milliseconds. The difference in access camp between the processing unit and the external storage device is about JO5, which has been an obstacle to improving the performance of the entire system. In order to improve performance, it has been proposed to provide a cache memory device made of semiconductor between the central processing bag and the external storage device to reduce the access gap.

A cache memory device is a data storage device in an external storage device.

- Store data that is frequently used in the evening, and when reading data stored in a cache memory device, shorten access time by reading directly from the cache memory device without accessing an external storage device. The aim is to

In a cache memory device, there are two types of methods for writing (@changing) data into a cache memory section.

In the first method, as shown in FIG. 1, data from the central processing unit [1 is transmitted via the data bus DB.

This is a simultaneous write method in which data is written to the cache memory unit 3 in the cache memory device 2 and also written to the external storage device [4] at the same time. The simultaneous write method requires access to the external storage device 2 every time a write is made, so the access time becomes longer, but the use of the cache memory section 3 is possible because writing is done to both the cache memory section 3 and the external storage device 4 at the same time. The rate can be small.

On the other hand, in the second method, as shown in FIG. 2, the data from the central processing unit 1 is temporarily written to the cache memory section 3 via the path C of the data bus DB, and then the data is written to the external storage device 4. Cache memory device 2 and external storage device 4
At the point when both become free, the data bus DB
This is a sequential writing method in which data is written from the cache memory unit 3 to the external storage device 4 via the following path. In the sequential write method, the write operation of the central processing unit 1 is completed by simply writing to the cache memory unit 3, so the operation time is much shorter than in the first method.
It is necessary to perform two operations: receiving write data from the central processing unit 1 and writing to the external storage device 4.
The usage rate of the cache memory unit 3 ends up being high. Generally, the simultaneous write method is suitable when processing a large amount of data at once, such as in batch processing, and the sequential write method is suitable for a time sharing system (TSS) having a large number of users.

However, with the increase in capacity, it has become common for a plurality of central processing units 1 to jointly use the external storage device 4. Therefore, batch processing and time sharing systems (
Although it is desirable to use both methods of TS'S), conventional methods only use either the simultaneous writing method or the sequential writing method, making it difficult to optimize the processing method. Ta.

[Purpose of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a cache memory device that eliminates the drawbacks of the prior art as described above and allows a writing method to be selected in accordance with the system environment.

[Summary of the invention]

In order to achieve the above object, the present invention has a cache memory section that stores frequently used data in an external storage device, and when accessing the data from a host device, the external storage device is accessed. In a cache memory device that transfers the data from the cache memory unit without any process, when there is a data write command to the cache memory unit, the data is simultaneously written to both the cache memory unit and the external storage device. a write circuit, a sequential write circuit that once writes data to the cache memory section and then writes to the external storage device using the data written to the cache memory section, and instructions for the host device. By providing selection means for selecting either the simultaneous write path or the sequential write circuit, an appropriate write processing method can be selected according to the system environment, and surface performance can be improved according to the system environment. It is characterized by the realization of an electronic computer system.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 3 is a block diagram of a computer system including a cache memory device according to an embodiment of the present invention.

2 is a central processing unit, 2 is a cache memory device, and 4 is an external storage device such as a magnetic disk device or a magnetic tape device. The cache memory device 2 has a cache memory section 3, in which frequently used data among the data in the external storage device 4 is stored.

In response to a read command from the central processing unit 1, if the requested data exists in the cache memory unit 3, it is read from the cache memory unit 3, and if it exists only in the external storage device 4, it is read from the external storage device 4. Transfer the corresponding data from.

The control signal 5 from the central processing unit 1 is outputted to the cache memory device 2, outputted to the AND circuit 7 as is, and outputted to the AND circuit 8 after being inverted by the NOT circuit 6. When the control signal 5 is 1', the AND circuit 7 ORs the write data written in the cache memory unit 3 from the path E of the data bus DB via the path F of the data bus DB. Output to 89. The A N,D circuit 8 operates when the output of the NOT circuit 6 is l', that is, the control signal 5 is 0'.
At this time, the write data from the central processing unit 1 is output directly to the OR circuit 9 via the path G of the data bus, but at this time, the write data is also transferred to the cache memory section 3 at the same time. The OR circuit 9 performs the logical sum of the outputs of the A N D-D paths 7.8 and outputs the result to the external storage device 4 via the path (2) of the data bus DB.

Now, assume that the central processing unit 1 is a system that performs batch processing. In this case, the central processing unit 1 outputs a signal of '0 leher' as the control signal 5 when performing the write process. A
As a result of inputting the write data from the central processing unit 1 and the signal of 1 level inverted by the NOT circuit 6 to the ND circuit 8, the write data from the central processing unit 1 is transferred to the external storage device 4. On the other hand, the write data is transferred to the cache memory section 3 unconditionally, so in the case of batch processing, the write data is transferred to the cache memory section 3 and the external storage device 4 at the same time. Therefore, the usage rate of the cache memory unit 3 is low, and this write processing method is suitable for batch processing in which a large amount of data is processed at once. Incidentally, at this time, the AND circuit 7 receives the level "0".

The output of the AND circuit 7 is prohibited.

The central processing unit 1 is a time sharing system (TSS).
) system, the control signal 5 issued from it will be '1 level. At this time, as a result of the input of the zero level signal inverted by the NOT circuit 6 to the AND circuit 8, no write data is directly output from the central processing unit 1 to the external storage device 4. Therefore, the write data is transferred only to the cache memory section 3. Transfer of the write data to the external storage device 4 is performed by the AND circuit 7 when both the cache memory device 2 and the external storage device 4 are free with respect to the central processing unit 1, after the data is once stored in the cache memory section 3.
This is done by The function of detecting this free time is generally known and is controlled by a microprogram, for example, so a description thereof will be omitted here. This method is suitable for a time sharing system (TSS) having a large number of users because the write operation of the central processing unit 1 itself is completed by simply writing to the cache memory section 38 and takes a short time.

As described above, it is possible to selectively set two write processing methods in one cache memory device. Although the cache memory device 2 is connected to a plurality of central processing units 1, only one is shown in FIG. 3, and the others are omitted.

Furthermore, the control (No. 8 5) may be set by, for example, a jumper wire in the cache memory device @2, and in this case, the number of settings must be provided corresponding to the number of central processing units gt to be connected.

〔Effect of the invention〕

As described above, according to the present invention, the write processing method for the cache memory section can be selected according to the system environment, and a high-performance computer system can be constructed according to the system environment.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the first method of writing to the cache memory section, FIG. 2 is a diagram for explaining the second method of writing to the cache memory section, and FIG. 3 is a diagram for explaining the second method of writing to the cache memory section. FIG. 1 is a diagram for explaining one embodiment of the present invention. 3: Cash memory section, 5: Control signal, 6: NOT circuit, 7.8: AND circuit, 9: O]? ! circuit. Figure 1 Figure 2

Claims (1)

[Claims] (1) It has a cache memory section that stores frequently used data in an external storage device, and when a host device such as a host device accesses the data, the data is stored in the cache memory without accessing the external storage device. In the cache memory device that transfers the data from the cache memory unit, when there is a data write command to the cache memory unit,
a simultaneous write circuit that simultaneously writes to both the cache memory section and the external storage device; and a simultaneous write circuit that once writes data to the cache memory section and then uses the data written to the cache memory section to write data to the external storage device. 1. A cache memory device comprising: a sequential write circuit for writing data to the memory; and a selection means for selecting either the simultaneous write circuit or the sequential write circuit according to an instruction from the host device.