JPS60125184A - Rotation controlling method of motor - Google Patents

Abstract

PURPOSE:To accurately maintain always the synchronizing rotation according to a reference pulse by delaying a comparison pulse to out of the set time when the comparison pulse is presented within the set time from the presence of a reference pulse. CONSTITUTION:An up-down counter 6 inputs a reference pulse P1 to a count-up terminal, a comparison pulse P2 from a rotation speed sensor 16 to a count- down terminal, and the counted value through a comparator 12 to a drive unit 14. The pulse P1 is delayed by the prescribed time by the first delay circuit 8, and inputted to the counter 6. The second delay circuit 10 delays a comparison pulse P2 to out of the set time and outputs to the counter 6 when the pulse P2 is presented within the set time from the presence of the pulse P1.

Description

[Detailed description of the invention] The present invention relates to a method for controlling five rotations of a motor.

For example, in order to comply with IMO standards, motors used in acoustic sounders must have a wide rotational speed range of 1:10 or more, and must also have accurate followability and responsiveness when changing speed. You are required to have one. Therefore, the inventors of the present invention input both a reference pulse that regulates the rotational speed of the motor and a comparison pulse that corresponds to the actual rotational speed of the motor into a circuit that drives and controls the motor, and calculates the frequency of both pulses. An up/down counter is provided that performs a run I operation in response to the difference, and the rotational speed of the motor is controlled by the count output from this up/down counter when the frequencies of both pulses match. (Refer to Utility Application No. 5'7-438220). It was confirmed that this allows the motor to be varied over a wide rotational speed range that satisfies the engineering MO standards, and also to have good followability and responsiveness even when the speed is changed. After considering the circuit, I found that
When the reference pulse and the comparison pulse are continuously input to the down counter, and the phase difference between the two pulses is small and the reference pulse and the comparison pulse enter the up/down counter at almost the same time, the up/down counter It has been found that there are cases where it is difficult to distinguish between the reference pulse and the comparison pulse, resulting in a counting error and, as a result, a problem in which the rotational speed of the motor temporarily fluctuates.

It is an object of the present invention to solve the above-mentioned problems and to enable the motor to accurately maintain synchronous rotation in accordance with the reference pulse at all times.

In order to achieve such an object, the present invention sets a certain time t1 based on the appearance of the reference pulse, and causes the up/down counter to perform a counting operation based on the reference pulse within this set time t1. When a comparison pulse appears within a set time, the comparison pulse is delayed until outside the set time and is applied to the up/down counter.

Hereinafter, the present invention will be explained in detail based on an embodiment shown in the drawings. FIG. 1 is a block diagram showing a motor rotation control device to which the present invention is applied. In the figure, 1 is a control circuit, and 2 is a reference pulse P1 that sets the rotation speed of the motor M.
4 is a reference pulse train circuit that shapes the waveform of the comparison pulse P2 corresponding to the actual rotational speed of the motor M. Also, 6 is the above-mentioned both pulses P,
This is an up/down counter that performs a counting operation in response to the difference in frequency of F2. A first delay circuit 8 is provided between the reference pulse train circuit 2 and the up/down/counter 6, which delays the reference pulse P1 that has passed through the reference pulse train circuit 2 by a predetermined time and supplies it to the up/down/counter 6 at the next stage. It is being Further, between the comparison pulse train circuit 4 and the up/down counter 6, a comparison pulse P2 passing through the comparison pulse train circuit 4 is compared with a reference pulse P1 from the first delay circuit 8, and the comparison pulse P2 is the reference pulse. A second delay circuit 10 is provided which supplies the comparison pulse P2 to the up/down counter 6 at the next stage with a further delay than the delayed reference pulse when the comparison pulse P2 is within a fixed phase difference from P1.

12 is a converter that converts the count value output from the up/down counter 6 into a control signal for the motor M; 14;
16 is a drive unit that drives the motor M with a drive output based on the converted output of the converter 12, and 16 is a comparison pulse P2 that detects the rotational speed of the motor M and corresponds to the rotational speed of the motor M.
A rotation speed sensor 18 outputs the rotation speed sensor 16 or an amplifier that amplifies the rano comparison pulse P2.

FIG. 2 is a circuit diagram showing details of the first delay circuit 8 and the second delay circuit 10. The first delay circuits 8 each have capacitors c, , c2 . c3. c4 and resistance R1゜R,
, R3, and R4, the first to fourth differentiating circuits D
F,, D F2. D F3. D F4, first and second inverter N1. Engineering N2, 1st NAND circuit N
A, and a first diode D. Further, the second delay circuit 10 includes capacitors C5 and C6, respectively.
, C7 and resistors "5. R, , R7, the fifth to seventh differentiating circuits D F5. D F6. D F,,
3rd inverter I N3, 2nd and 3rd two NAND
Circuit NA2. NA3 and a second diode D2. In addition, each of the first to seventh differentiating circuits D
The capacitor capacitance and resistance value of F, to D F7 are respectively set so as to exhibit a predetermined time constant.

Next, regarding the control operation of the motor M by the control circuit 1, first, the drive control of the entire circuit will be explained, and then,
Delay operations by the first and second delay circuits 8 and 10 will be explained.

A reference pulse P1 having a reference frequency for setting the rotational speed of the motor M is generated by the reference pulse train circuit 2 into a waveform +! After that, the signal is inputted to the -f up/down/counter via the first delay circuit 2 at the next stage. Up/Down/Counter 6
outputs a count value in response to the input reference pulse Pl, and this color/1 value is input to the drive section 14 via the converter 12.

Converter 12 converts the count value of up/down counter 6 into a control signal for controlling the rotation speed of motor M. When using a DC motor as the motor M, the converter 12
A D'/A converter is used, and the DC voltage output changes in accordance with the count value of the up/down counter 6. The rotation of the motor M is controlled by this voltage output. For example, when the count value increases, the DC voltage output also increases, and the drive unit 14 increases the rotation speed of the motor M based on this voltage output. Conversely, when the count value decreases, the DC voltage output also decreases, and the drive unit 14 decreases the rotation speed of the motor M based on this voltage output. Further, when an AC motor is used as the motor M, the converter 12 changes the AC voltage output in accordance with the count value of the up/down counter 6. To control the AC voltage, for example, the count value of the up/down counter 6 may be converted to a DC voltage by a D/A converter, and the amplitude of the AC signal may be modulated using the converted DC voltage. The drive unit 14 then rotates the AC motor according to the converted AC voltage.

Alternatively, the converter 12 may be an A/A converter as described above, but other converters may also be used. For example, the rotation of the motor M may be controlled by controlling the flow time of the supplied DC or AC current. In this case, the converter 12 may convert the count value of the up/down counter 6 into a control signal for controlling the flow time of the drive current supplied from the drive unit 14 to the septa M. for example,
The converter 12 sends out a pulse wave whose repetition frequency or pulse width changes to i in accordance with the count value of the up/down counter 6, and uses this pulse wave to intermittently interrupt the flow time of the drive current. Therefore, it is possible to change the cutoff interval or cutoff time depending on the count value. Further, when an AC motor is used as the motor M, the frequency of the drive current may be controlled by one. In this case, the controller 12 may convert the up/turn counter 60 count value into a frequency change of the alternating current signal. For example, in the converter 12, the frequency of the reference frequency signal is divided to generate an AC signal, and by changing the frequency division ratio according to the count value of the up/down counter 6, the frequency of the AC signal is changed to the count value. It can be changed according to.

A drive output corresponding to the count value is generated from the drive unit 14, and the motor M is rotated by this drive output.

The rotational speed of the motor M is detected by a rotational speed sensor 16. The rotation speed sensor 16 generates a comparison pulse P2 corresponding to the rotation speed. This comparison pulse P2 is input to the comparison pulse train circuit 4 after being amplified by the next-stage amplifier 18. Comparison) The pulse train circuit 4 shapes the waveform of the comparison pulse P2. Comparison, comparison pulse P2 from S pulse train circuit 4
is the up/down counter 6 via the second delay circuit 10.
is man-powered.

The up/down counter 6 has a count up terminal UP.
An addition count is performed each time a pulse wave is applied to the countdown terminal DOWN, and a subtraction count is performed each time a pulse wave is applied to the countdown terminal DOWN. Therefore, when the frequency of the reference pulse P1 is higher than that of the comparison pulse P2, and when the actual rotational speed of the DC motor M is lower than the normal rotational speed, the up/down counter 6 is based on the reference pulse P. A count up operation is performed to increase the initial count value. The count value resulting from this count-up operation is outputted from the up/down counter 6 and is provided to the drive section 14 via the converter 12.

Since the drive unit 14 provides the motor M with a drive output responsive to this count value, the rotational speed of the motor M is increased.

The rotational speed of the motor M thus increased is detected by the rotational speed sensor 16, and the comparison pulse ζ pulse P2 output from the rotational velocity sensor 16 is transferred to the amplifier 18 and the comparison pulse train circuit 4.
, the up/down counter 6 via the second rounding circuit 10
feedback will be given again. In this way, the comparison pulse P2 and the reference pulse P1 and the two pulses p, . , conversely, when the number of clock responses of the reference pulse P, is smaller than that of the comparison pulse P2, the up/down counter 6 performs a countdown operation in accordance with the frequency difference between the pulses p, , p2 in the same way as above. As a result, the rotation speed of the motor M is controlled in accordance with the frequency of the reference pulse P1, and the motor M is rotated synchronously.

Next, the delay operations of the first delay circuit 8 and the second delay circuit 10 will be explained. FIG. 3 is a waveform diagram showing changes in the waveform of the reference pulse passing through the first delay circuit 8. As shown in FIG. The reference pulse P1 inputted to the first delay circuit 8 via the reference pulse train circuit 2 is waveform-shaped into a predetermined pulse width t1 by the first differentiating circuit DF of the circuit 8, and then passed through the first inverter IN, The polarity is reversed (FIG. 3(A)).

The polarity of this inverter N1 output is inverted by the first NAND circuit NA through the second differentiating circuit DF2 ((B) in the same figure). Then, the output of the first NAND circuit NA has a pulse width approximately halved by the third differentiating circuit DF3, and the polarity of this pulse is inverted by the second inverter IN2 ((C) in the same figure).

This second inverter N2 output is sent to the fourth differentiating circuit D F4
and the first diode D1, the signal is converted into a pulse responsive to the rise timing of the signal ((D) in the same figure). Therefore, as shown in FIG. 5, the reference pulse P (after passing through the first delay circuit 8) is delayed by a predetermined time (ty2) from the reference pulse P1 input to the circuit 8. Pf is provided to an up/down counter 10.

FIG. 4 is a waveform diagram showing waveform changes according to the phase difference between the comparison pulse passing through the second delay circuit 10 and the reference pulse, and five examples of phase differences are shown in each case. The comparison pulse P2 input to the second delay circuit 10 via the comparison pulse train circuit 4 is applied to the first inverter N1 output (the fourth
The waveform is shaped into a pulse width t2 that is longer than that shown in Figure (A).
Same figure (E)). This fifth differentiating circuit output and the first delay circuit 8
The output of the first input/verter N1 is also input to the second NAND circuit NA. As a result, the second NAND circuit N
The A2 output has the waveform shown in the same figure (2) obtained by NANDing the same figure (A) and (2). This second NAND circuit N2 output is one input of the third NAND circuit N3 in the next stage. When there is no feedback from the third inverter Ns, a high level is applied to the other input terminal of the third NAND circuit IN8.
The output of the inverter N is the inverted polarity of the 12NAND circuit NA2 output ((()I) in the same figure). This third NAND circuit NA3 output is the sixth differentiator circuit D11+'6
In response to the rising timing, the waveform becomes a waveform having a pulse width t3 larger than the output of the fifth differentiating circuit DF, and the polarity is reversed by the third inverter N3 in the next stage (the same figure (average)). This third inverter IN3 output is
It is fed back to the NAND circuit NA3. 3rd N
The A N D circuit NA connects this fed-back third inverter I N3 output (see the same diagram)) and the second NAND
Input the circuit NA and output ((F) in the same figure) and check the NA of both.
Take ND. Therefore, the output of the third NAND circuit NA has a waveform that is inverted in polarity from the output of the third inverter N3, as shown in FIG. 2 (G2). The output of the third NAND circuit NA3 is converted into a pulse responsive to the rising timing by the seventh differentiating circuit DF and the second diode D2 ((I) in the same figure). Therefore, as shown in FIG. 5, the comparison pulse P5 after passing through the second delay circuit 10 is delayed according to the phase difference with the reference pulse P1 input to the first delay circuit 8. That is, when the comparison pulse P2 is within the constant phase difference t1 of the reference pulse P1, it is delayed to outside this constant phase difference t1. Comparison pulse P! thus delayed! is given to the up/down counter 6. As a result, the reference pulse pi that has passed through the first delay circuit 8 and the comparison pulse 2 that has passed through the second delay circuit 10
The stage will always maintain at least the required phase difference.

In the above embodiment, as shown in FIG. A long time t1 is set, and within this set time t1, the up/down counter 6 is caused to perform a counting operation using the delayed reference pulse P1, and within this set time t1, the comparison pulse P is
2 appears, this appearing comparison pulse is delayed by the second delay circuit outside the set time. Therefore, the comparison pulse P2 with respect to the reference pulse P1
Since the phase difference between the two is always maintained above the required value, it is possible to prevent the occurrence of counting errors in the up/down counter, resulting in the excellent effect of being able to maintain the motor's rotational speed accurately at all times. .

In the above, if the reference pulse P1 has a wide pulse width, for example, the pulse width is shorter than the set time t1, for example, that pulse wave (Fig. 4 pry) is used as the reference pulse P1, 1 delay circuit need not be used. That is, a pulse wave shown in P7 in FIG. If the up/down counter 6 performs the counting operation at the time of falling, there is no need to delay the reference pulse P1 like pi, as shown in FIG.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention, and FIG. 1 is a block diagram in which the present invention is applied to a motor control device, FIG. 2 is a circuit diagram of a first delay circuit and a second delay circuit, and FIG. is the first
FIG. 4 is a waveform diagram showing waveform changes of the reference pulse passing through the delay circuit. FIG. 1- is a time chart showing a reference pulse before and after passing through the delay circuit, and a comparison pulse before and after passing through the second delay circuit. 1. Drive circuit, 6. Up/down/counter, 8.
1st delay circuit, 10...2nd delay circuit, G...motor. Applicant: Furuno Electric Co., Ltd. Agent: Kazuhide Okada, patent attorney

Claims (1)

[Claims] (1) An up/down counter that inputs a reference pulse that sets the motor rotation speed and a comparison pulse that corresponds to the actual rotation speed of the motor, and performs a 1/J count operation in response to the frequency difference between the two pulses. Use this to upload/
In the motor control method, the rotational speed of the motor is controlled based on a control signal output from a down counter, in which a certain period of time is set based on the appearance of the reference pulse, and the reference pulse is detected within the set time. While causing the up/down counter to perform a counting operation based on the pulse, when the comparison pulse appears within the set time, the appearing comparison pulse is delayed until outside the set time and the up/down counter A method for controlling rotation of a motor, characterized in that: