JP2543541B2 - Drive device for PWM inverter - Google Patents

Description

The present invention relates to a drive device for a PWM inverter, and more particularly to a drive device for a PWM inverter suitable for controlling the speed of an AC motor or the like.

[Conventional technology]

As a method of controlling the speed of an AC motor, a method of giving a PWM pulse signal to a switching element of an inverter is known. When generating this PWM pulse signal, the magnitude relationship between the voltage command signal of variable voltage and variable frequency and the carrier wave of a constant frequency triangular wave or sawtooth wave is compared,
A method of generating a PWM pulse signal whose duty ratio changes according to the magnitude of both signals is adopted. Examples of this system include those described in JP-A-61-109467 and JP-A-61-199472. Conventionally, the methods for generating these PWM pulse signals are the asynchronous method that changes the voltage command signal (modulation wave) of variable voltage and variable frequency while keeping the carrier wave constant, and the synchronous method that synchronizes the modulation wave and the carrier wave. ing.

[Problems to be Solved by the Invention]

Unlike the synchronous system, the asynchronous system in the above conventional technology does not require a PLL (phase locked loop) circuit or a pulse number switching circuit, so the circuit configuration can be simplified. Since the method of sequentially comparing the modulated waves is used, it is necessary to configure the carrier wave generation circuit and the successive comparison circuit with a hard circuit to perform high speed comparison. When the carrier generation circuit and the comparison circuit are made to be software, the comparison calculation pitch becomes slower due to the restriction of the processing time of the microcomputer, and a beat is generated between the voltage command which is the modulated wave and the output voltage. In particular, the higher the frequency of the modulated wave, the greater the influence thereof, and when the speed of the electric motor is controlled by the inverter, there is a problem that current beat or noise is generated due to the beat.

That is, as shown in FIGS. 2 and 3, the carrier wave 11 and the modulated wave 12 are compared, and when the level of the carrier wave 11 is lower than the level of the modulated wave 12, the PWM pulse signal 1
I am trying to output 3. However, when the frequency of the modulation wave 12 that is the command value for controlling the speed of the electric motor becomes high, when the voltage of the modulation wave 12 decreases, the phase of the PWM pulse signal 13 is an ideal PWM pulse signal (shown by a broken line). Waveform), and conversely, when the voltage of the modulated wave 12 increases, the phase of the PWM pulse signal 13 leads the ideal PWM pulse signal (waveform indicated by the broken line).

Considering this as the average voltage of the modulation wave 12 in one cycle Tc of the carrier wave 11, when the average voltage in one cycle Tc of the modulation wave 12 is 0V, the intersection point of the 0V line and the carrier wave 11 is PWM.
This is the point at which the level of the pulse signal 13 is inverted. For this reason, the PWM pulse signal 13
As shown in FIG. 4, as the frequency of the modulated wave 12 increases, a phase shift occurs between the ideal PWM pulse signal 13 and the actual PWM pulse signal 13 as described above. Although the signal indicated by the broken line in FIG. 4 should be applied to the AC motor, in reality, the destructive signal indicated by the solid line in FIG. 4 is applied to the AC motor. Since the signal indicated by the broken line in FIG. 4 is out of phase with the voltage command signal, this causes a beat.

An object of the present invention is to suppress the phase shift between the voltage command signal and the inverter output signal in the asynchronous system.
It is to provide a drive device of a PWM inverter device.

[Means for solving the problem]

The present invention provides a voltage command means for outputting a voltage command signal for adjusting an inverter output, and a timing pulse for sequentially outputting timing pulses at a timing corresponding to one cycle of a virtual carrier wave having a frequency higher than that of the voltage command signal. The generation means, the advance phase voltage command signal generation means for generating a phase advance voltage command signal by advancing the phase angle of the voltage command signal by a predetermined value in accordance with the voltage command signal output from the voltage command means, and the advance phase voltage command signal generation means. A leading phase intermediate value calculating means for calculating a leading phase intermediate value corresponding to the voltage value of the voltage command signal at the intermediate point of the one cycle of the virtual carrier wave from the generated leading phase voltage command signal, and calculation of the leading phase intermediate value calculating means Value and the on-timing time corresponding to the intersection point of the virtual carrier and the virtual line parallel to the time axis of the virtual carrier that passes through the intermediate phase value based on the amplitude value of the virtual carrier. An on-off timing time calculating means for calculating the off-timing time with reference to the timing pulse generation timing; and an on-pulse signal for turning on the switching element of the inverter according to the on-timing time and the off-timing time calculated by the on-off timing time calculating means. A PWM inverter drive device comprising PWM pulse generation means for sequentially outputting to the inverter an off-pulse signal for turning off a switching element of the inverter.

[Action]

When the voltage command signal for adjusting the inverter output is output, timing pulses are sequentially output at timings corresponding to one cycle of a virtual carrier wave whose frequency is higher than that of the voltage command signal, and the phase angle of the voltage command signal is set to a predetermined value. The advanced phase advance voltage command signal is generated, and the phase advance intermediate value corresponding to the voltage value of the voltage command signal at the midpoint of one cycle of the virtual carrier wave is calculated from the advanced phase voltage instruction signal. Then, based on the phase advance intermediate value and the amplitude value of the virtual carrier, the on-timing time and the off-timing time corresponding to the intersection point of the virtual carrier passing through the phase advanced intermediate value and parallel to the time axis are the timing pulse generation timing. The on-pulse signal is calculated based on the reference, and the on-pulse signal is output to the switching element of the inverter according to the calculated on-timing time, and the off-pulse signal is output to the switching element of the inverter according to the calculated off-timing time. As a result, the inverter outputs the AC voltage in which the phase shift from the voltage command signal is suppressed.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, an inverter 20 converts a DC voltage P, N into a three-phase AC voltage and drives an AC motor 22 as a drive target. The inverter 20 has various switching elements, and each switching element has a driving device.
The pulse signal from 24 is supplied.

The driving device 24 is a microprocessor 26, a ROM 28, an interrupt signal generating circuit 30, counters 32, 34, 36, 38, 40, 42, pulse generating circuits 44, 46, 48, logic inverting circuits 50, 52, 54, driver circuits.
It consists of 56.

The microprocessor 26 has a CPU, a RAM, a ROM, an I / O, etc., and is supplied with a speed command and a speed signal according to the rotation speed of the AC electric motor 22. The microprocessor 26 is adapted to generate a command value for adjusting the speed of the AC motor 22 as a voltage command signal based on the speed command and the speed signal from the AC motor 22.

Further, as shown in FIG. 5E, an interrupt pulse as a timing pulse is supplied to the microprocessor 26 from the interrupt signal generating circuit 30 as the timing pulse generating means. I'm running.
As shown in FIG. 5 (A), the timing pulse is sequentially output at a timing corresponding to a carrier wave having a frequency higher than that of the voltage command signal 60, for example, one cycle Tc of a 1.2 kHz triangular wave. ing. Then, the microprocessor 26 calculates the on / off timing time of the PWM pulse based on the interrupt pulse so that the average output voltage of one cycle of the carrier wave matches the average voltage command value of one cycle of the carrier wave. The calculation is as follows.

For example, as shown in FIG. 5, at time t0 (interrupt pulse generation timing i + 1), timing (i
When obtaining the on / off timing time of the PWM pulse between +1) to (i + 2), the average output voltage of the inverter 20 during one cycle of the virtual carrier 62 is a linear change of the voltage command signal 60 during one cycle of the virtual carrier 62. Considering the change, the voltage value Va at the time ta, which is the midpoint of one cycle of the virtual carrier wave 62, shows an average value (see FIGS. 5B and 5C). Therefore, in order to obtain the voltage command value (voltage command signal) at time ta at time t0, the phase of the voltage command signal 60 shown by the dotted line is advanced by the phase angle θ as shown in FIG. 5 (D). The advanced voltage command signal 60 'is sought.

Next, a voltage (advanced phase intermediate value) Va ′ corresponding to the voltage Va at the midpoint of the voltage command signal 60 is obtained from the advanced phase voltage command signal 60 ′, passes through the voltage Va ′ and is parallel to the time axis of the virtual carrier wave 62. The intersections C1 and C2 of the virtual line 64 and the virtual carrier wave 62 are obtained. Then, the times T1 and T2 from the time t0 to each of the intersections C1 and C2 are obtained as the PWM pulse generation time, and T1 is the on-timing time and T2 is the off-timing time. Then, these times T1 and T2 are obtained by the following equations (1) and (2).

T2 = Tc-T1 (2) Here, Vp represents the maximum value of the virtual carrier wave 62.

Further, the time T1 is obtained as the time corresponding to the off timing of the PWM pulse, and the time T2 is obtained as the time corresponding to the on timing of the PWM pulse.

As described above, the microprocessor 26 includes the voltage command means for generating the voltage command signal 60 from the speed command and the speed signal, and the advanced voltage command signal 60 obtained by advancing the phase angle of the voltage command signal 60 by a predetermined value according to the voltage command signal 60. A phase-advancing voltage command signal generating means for generating ', and a voltage corresponding to the voltage Va of the voltage command signal 60 at the midpoint between the cycles of the virtual carrier 62 based on the phase-advancing voltage command signal 60' (advancing phase intermediate value). Based on the phase advance intermediate value calculation means for calculating Va ′ and the calculated value of the phase advance intermediate value calculation means and the amplitude value of the virtual carrier wave 62, the voltage (lead phase intermediate value) Va ′ is passed to the time axis of the virtual carrier wave 62. Parallel virtual line 64 and virtual carrier
An on-off timing time calculating means for calculating an on-timing time and an off-timing time corresponding to the intersection with the 62 on the basis of the generation timing of the interrupt pulse, and each calculated value of the on-off timing time calculating means It is designed to be output to the counters 32 to 42.

Further, when calculating the voltage Va at the intermediate point corresponding to 1/2 cycle of the virtual carrier wave 62 of the voltage command signal 60 at time t0, the phase of the voltage command signal 60 is advanced by a predetermined value, for example, the phase angle θ. However, this phase angle θ is obtained as follows, for example.

Time t0, which is the generation time of the interrupt pulse, and the virtual carrier
Let Δt be the time difference from time ta corresponding to 1/2 cycle of 62,
If the frequency of the voltage command signal 60 is fo, θ is given by the following (3)
It is represented by a formula.

θ = 2π · fo · Δt (3) The counters 32 and 34 are used as counters for driving U-phase switching elements, the counters 36 and 38 are used as V-phase counters, and the counters 40 and 42 are It is used as a W-phase counter. Since each phase has the same function, only the U-phase counter will be described below. The counter 32 is set with the off-timing value, and the counter 34 is set with the on-timing value. Each of the counters 32 and 34 counts the clock pulse from the microprocessor 26 in synchronization with the timing pulse, and outputs the off pulse to the pulse generation circuit 44 when the count value reaches the count value corresponding to the off timing. Further, the counter 34 counts the clock pulse from the microprocessor 26 in synchronization with the timing pulse, and outputs the ON pulse to the pulse generation circuit 44 when the count value reaches the count value corresponding to the ON timing. There is. The pulse generation circuit 44 outputs a PWM pulse signal for driving the switching element on the P side by the output pulse of the counter 32, and outputs an N pulse by the output pulse from the counter 34.
The PWM pulse signal for driving the switching element on the side is output. The former PWM pulse signal is directly supplied to the driver circuit 56, and the latter PWM pulse signal is supplied to the driver 56 via the logic inverting circuit 50. Then, each pulse signal is amplified by the driver circuit 56 and supplied to the switching element of the inverter 20. When the PWM pulse signal is supplied to the switching element of each inverter 20, the inverter 20 outputs the PWM pulse signal as shown in FIGS. 5B and 5C. The average value of the PWM pulse signal output from the inverter 20 is a signal having substantially the same phase as the voltage command signal 60. Therefore, it is possible to suppress the occurrence of beats due to the phase difference between the voltage command signal 60 and the output signal of the inverter 20.

In the above embodiment, the counters 32 to 42 are used. However, when the microprocessor 26 has a built-in hard timer or scheduling memory, these counters are used instead of the counters. It can be used, and in this case, the hardware configuration can be further simplified.

Further, in the above embodiment, the PWM pulse generating means is constituted by the counters 32 to 42 and the pulse generating circuits 44 to 48,
Although it has been described that the output signals of the logic inversion circuits 50, 52, 54 are used to drive the N-side switching element of each phase, when the switching element is turned off, there is a delay from the signal of the drive pulse, If a delay circuit is inserted at the output side of the generating circuit 44 and a non-lap time is provided between when the P-side switching element is turned off and when the N-side switching element is turned on, the P-side switching element is provided. It is possible to prevent the switching elements on the and N sides from being turned on at the same time.

〔The invention's effect〕

As described above, according to the present invention, since the phase shift between the voltage command signal and the inverter output signal is suppressed, the current is generated by the occurrence of the beat due to the phase difference between the voltage command signal and the inverter output signal. It is possible to suppress the generation of vibration and noise, and it is possible to contribute to the improvement of the performance of the inverter.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are waveform charts for explaining the operation of a conventional example,
FIG. 4 is a waveform diagram for explaining the characteristics of the conventional example, and FIG. 5 is a waveform diagram for explaining the operation of the device according to the present invention. 20 …… Inverter, 22 …… AC motor, 26 …… Microprocessor, 30 …… Interrupt signal generation circuit, 32,34,36,3
8,40,42 …… Counter, 44,46,48 …… Pulse generator, 5
0,52,54 …… Logic inversion circuit, 56 …… Driver circuit.

Claims (1)

(57) [Claims] 1. A voltage command means for outputting a voltage command signal for adjusting an inverter output, and a timing for sequentially outputting a timing pulse at a timing corresponding to one cycle of a virtual carrier wave having a frequency higher than that of the voltage command signal. A pulse generating means, a phase advancing voltage command signal generating means for generating a phase advancing voltage command signal by advancing a phase angle of the voltage command signal by a predetermined value according to the voltage command signal output from the voltage commanding means, and a phase advancing voltage command signal generating means. Of the phase advance intermediate value calculating means for calculating a phase advance intermediate value corresponding to the voltage value of the voltage instruction signal at the intermediate point of the one cycle of the virtual carrier wave by the generation of the phase advanced voltage instruction signal. At the on-timing corresponding to the intersection of the virtual carrier and the virtual line parallel to the time axis of the virtual carrier passing through the phase transition intermediate value based on the calculated value and the amplitude value of the virtual carrier. And an on-off timing time calculating means for calculating the off-timing time with reference to the timing pulse generation timing, and an on-pulse signal for turning on the switching element of the inverter according to the on-timing time and the off-timing time calculated by the on-off timing time calculating means A drive device for a PWM inverter, comprising: and a PWM pulse generating means for sequentially outputting an off-pulse signal for turning off a switching element of the inverter to the inverter.