JPS60121793A - Method of producing thick film hybrid integrated circuit board - Google Patents

Method of producing thick film hybrid integrated circuit board

Info

Publication number
JPS60121793A
JPS60121793A JP23096383A JP23096383A JPS60121793A JP S60121793 A JPS60121793 A JP S60121793A JP 23096383 A JP23096383 A JP 23096383A JP 23096383 A JP23096383 A JP 23096383A JP S60121793 A JPS60121793 A JP S60121793A
Authority
JP
Japan
Prior art keywords
thick film
conductor
hybrid integrated
integrated circuit
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23096383A
Other languages
Japanese (ja)
Inventor
均 戸田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP23096383A priority Critical patent/JPS60121793A/en
Publication of JPS60121793A publication Critical patent/JPS60121793A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の技術0分野〕 この発明は、厚膜基板に認識マークを設け、回路部品の
搭載位置が補正されるようにする、厚膜混成集積回路基
板の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a thick film hybrid integrated circuit board in which a recognition mark is provided on a thick film board so that the mounting position of circuit components is corrected. .

〔従来技術〕[Prior art]

厚膜混成集積回路の組立工程は、ダイポンド。 The assembly process for thick film hybrid integrated circuits is diepond.

ワイヤボンドなどのボンディング工程と、コンデンサ、
抵抗、ミニ七−ルド半導体素子などのチップ部品等の電
子部品装着工程、及びディスクIJ −ト部品、外部リ
ード等のはんだ付は工程の3工程からなっている0これ
らの工程のうち、特に、前工程のトランジスタ・ダイオ
ード・IC等の半導なっている。
Bonding processes such as wire bonding, capacitors,
The process of mounting electronic components such as resistors and chip components such as mini-7-wire semiconductor devices, and the soldering process of disk IJ-toad components and external leads are comprised of three processes. Among these processes, in particular, Semiconductors such as transistors, diodes, and ICs are used in the front-end process.

従来の厚膜混成集積回路基板の製造方法は、第1図に認
識マークを設けた厚膜基板の概要平面図で示すようにし
ていた0(l)は厚膜基板で、上面にパターンの認識マ
ーク(2)がA、B位置に2箇所形成されている。この
認識マークは黒色系のルテニウム系の抵抗体、又は同色
の誘電体からなり、本米の厚膜回路の導電体回路パター
ン(図示は略す)形成後、抵抗体パターン又は誘電体パ
ターン形成時に同時に付加形成される。このように、厚
膜基板(1)上に形成された厚膜回路パターン上には部
品搭際部を除き保護の誘電体ガラス(図示は略す′)で
被伎する。
The conventional method for manufacturing thick film hybrid integrated circuit boards is as shown in Figure 1, which is a schematic plan view of a thick film board with recognition marks. Two marks (2) are formed at positions A and B. This recognition mark is made of a black ruthenium-based resistor or a dielectric of the same color, and is used simultaneously after the conductor circuit pattern (not shown) of the thick film circuit is formed and when the resistor pattern or dielectric pattern is formed. Additionally formed. In this way, the thick film circuit pattern formed on the thick film substrate (1) is covered with a protective dielectric glass (not shown) except for the component mounting area.

従来は上記認識マーク(2)を利用し、次のように行っ
ていた。厚膜基板+11には認識マーク(2)にょシバ
ターン認識機能を付加されており、基板+1+ごとに認
識マーク(2)で部品の搭載点を認識することにより、
基板(1)の位置ずれを電子計算機により算出し搭載点
のX線;Y軸及び傾き角Vとの補正を行い、搭載動作を
開始する。
Conventionally, the above recognition mark (2) was used and the process was carried out as follows. The thick film board +11 is equipped with a recognition mark (2) and a pattern recognition function, and by recognizing the mounting point of the component with the recognition mark (2) for each board +1+,
The positional deviation of the board (1) is calculated by an electronic computer and corrected with the X-ray, Y-axis and inclination angle V of the mounting point, and the mounting operation is started.

上記従来の認識マーク(2)による方法は、白地の厚膜
基板(1)面と黒色の認識マーク(2)とのコントラス
トにより白黒画体化し、電子割算様による2値化信号レ
ベルで、厚膜基板[11位置のずれを検出し補正するよ
うにしている。この場合、2値化レベルの安定性を確保
するために、黒色系の抵抗体又は誘電体を便宜上、認識
マーク(2)として採用している。しかし、本来部品搭
載点は、抵抗体又は誘電体上ではなく、基板i11面に
施されている回路パターンの銀−パラジウム系の導電体
上に置くものである。したがって、前に施されである導
電体とこの後に施された認識マーク(2)とは、厚膜印
刷の重ね合わせ精度上の許容差内のずれがある。
The method using the conventional recognition mark (2) described above converts the image into a black and white image by contrast between the white thick film substrate (1) surface and the black recognition mark (2), and converts it into a binary signal level using electronic division. The positional shift of the thick film substrate [11] is detected and corrected. In this case, in order to ensure the stability of the binarization level, a blackish resistor or dielectric material is used as the recognition mark (2) for convenience. However, the component mounting point is originally not placed on the resistor or dielectric, but on the silver-palladium based conductor of the circuit pattern formed on the surface of the substrate i11. Therefore, there is a deviation between the previously applied conductor and the subsequently applied recognition mark (2) within the tolerance for overlay accuracy of thick film printing.

上記従来の認識マーク(2)による製造方法では、コン
デンサ、抵抗、ミニモールド素子等のチップ部品の搭載
に要求される、位置精度上200μ以内は満足できる。
The manufacturing method using the conventional recognition mark (2) described above can satisfy the positional accuracy of 200 μ or less required for mounting chip components such as capacitors, resistors, and mini-molded elements.

しかし、より以上の高度な位置精度上50μ以内を必要
とするようなグイボンド、ワイヤボンドのボンディング
工程の場合は、認識マーク(2)では不良品が生じる欠
点があった。
However, in the case of bonding processes such as Gui-bond and wire-bond, which require higher positional accuracy within 50 μm, the recognition mark (2) has the drawback of producing defective products.

また、基板(1)上に施されるパターンの銀−パラジウ
ム系の導電体と同時に、同材料の導電体で認識マークを
形成することも考えられるが、位置精度は高精度になる
のに反し、釦−パラジウム系ハ色彩が灰白系であり、基
板+1i面の白地とのコントラストがとれず、2値化レ
ベルが不安定となり認識マークとして不都合であった。
It is also possible to form a recognition mark with a conductor made of the same material at the same time as the silver-palladium conductor in the pattern applied on the substrate (1), but this would result in high positional accuracy. The button-palladium type C color was grayish-white, and there was no contrast with the white background of the +1i surface of the substrate, and the binarization level was unstable, which was inconvenient as a recognition mark.

〔発明の概要〕[Summary of the invention]

この発明は、上記従来の方法の欠点を除くためになされ
たもので、厚膜基板に施こす導電体の回路パターンの形
成と共に、同材料の導電体で認識マークを形成し、この
上を半透明色の誘電体ガラスで被覆するように重ね合わ
せて厚膜印刷することによシ、厚膜基板の地色と認識マ
ークの色のコントラストを高め、位置精度が高精度にな
シ、検出レベルが安定され、正確な搭載点及びボンディ
ング位置精度の高い、位置補正ができる、厚膜混成集積
回路基板の製造方法を提供することを目的としている。
This invention was made in order to eliminate the drawbacks of the above-mentioned conventional methods.In addition to forming a circuit pattern of a conductor on a thick film substrate, a recognition mark is formed using a conductor made of the same material, and a half-layer is formed on the conductor. By overlapping and printing thick films covered with transparent dielectric glass, the contrast between the ground color of the thick film board and the color of the recognition mark is increased, and the positioning accuracy is high and the detection level is high. It is an object of the present invention to provide a method for manufacturing a thick film hybrid integrated circuit board in which the mounting point is stable, the bonding position is accurate, the bonding position is high, and the position can be corrected.

〔発明の実施例〕[Embodiments of the invention]

第2図はこの発明の一実施例による厚膜混成集積回路基
板の製造方法を示す厚膜基板の平面図である。厚膜基板
(1)の上面には、銀−パラジウム系の導電体による厚
膜回路パターン(図示は略す)が印刷・焼成されている
。この厚膜回路パターンの形成と同時に、同材料の導電
体による認識マーク(5)がA及びB位置に2か所印刷
・焼成されて形成されている。(6)は上記厚膜回路パ
ターンをなす導電体や抵抗体などを被覆保護した誘電体
ガラス(図示は略す)と同時に、同材料で認識パターン
(5)を被覆したガラス被覆層である。厚膜基板Hに施
した認識マーク部を、第3図に拡大断面図で示す。
FIG. 2 is a plan view of a thick film substrate showing a method of manufacturing a thick film hybrid integrated circuit board according to an embodiment of the present invention. A thick film circuit pattern (not shown) made of a silver-palladium based conductor is printed and fired on the upper surface of the thick film substrate (1). Simultaneously with the formation of this thick film circuit pattern, two recognition marks (5) made of a conductor made of the same material are printed and fired at positions A and B. (6) is a dielectric glass (not shown) that covers and protects the conductor, resistor, etc. forming the thick film circuit pattern, and at the same time is a glass coating layer that covers the recognition pattern (5) with the same material. The recognition mark portion formed on the thick film substrate H is shown in an enlarged cross-sectional view in FIG.

ガラス被覆層(6)をなす誘電体ガラスは、薄縁色や薄
茶色系統で半透明にされている。これにより、このガラ
ス被覆層(6)を通して、厚膜基板(+)の白地部分は
誘電体カラスの色となり、認識パターン(5)部は導電
体の灰色が誘電体ガラスの色に重なり黒色に近い色で濃
くなり、光学的に厚膜基板+11と認識パターン(6)
とのコントラストが鮮明に撮像され、パターン認識時の
2値化レベルが安定化される。
The dielectric glass constituting the glass coating layer (6) is semitransparent with a light edge color or light brown color. As a result, through this glass coating layer (6), the white part of the thick film substrate (+) becomes the color of the dielectric glass, and the recognition pattern (5) part becomes black as the gray of the conductor overlaps with the color of the dielectric glass. The closer the color, the darker it becomes, and the pattern recognized as optically thick film substrate +11 (6)
The contrast between the two images is clearly captured, and the binarization level during pattern recognition is stabilized.

こうして、認識マーク(5)と部品搭載点及びダイボン
ド点、ワイヤボンド点等が同一工程でパターン形成され
た同一の厚膜導電体が基準になって、各位置座標データ
設定が可能となるので、ボンディング工程で必要とする
±50μの高精度の位置補正をすることができる。
In this way, the recognition mark (5), component mounting point, die bonding point, wire bonding point, etc. can be set using the same thick film conductor patterned in the same process as a reference, and each position coordinate data can be set. It is possible to perform highly accurate position correction of ±50μ required in the bonding process.

なお、上記実施例では、導電体として銀−パラジウム系
導電体の場合を示したが、厚膜基板(1)の色とコント
ラストの弱い色の他の材質の導電体の場合にも適用でき
るものである。
In the above embodiment, a silver-palladium-based conductor is used as the conductor, but the present invention can also be applied to conductors made of other materials with a color that has a weak contrast with the color of the thick film substrate (1). It is.

また、上記実施例では認識マーク(5)として正方形の
場合を示したが、厚膜基板(1)の位置が検出できる形
状であれば、他の形状であってもよい。
Further, in the above embodiment, the recognition mark (5) is square, but it may be of any other shape as long as the position of the thick film substrate (1) can be detected.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれは、厚膜基板面に導電体
により、厚膜回路パターンと同時に認識パターンを形成
し、導電体ガラスにより上記回路パターンの所要部と認
識パターンを被佼し、このガラス被覆層は、厚膜基板の
地色と認識パターンの色とのコントラストがつく薄色の
半透明にし、この認識パターンを検出し厚膜基板の位置
補正をするようにしたので、検出レベルが安定され、高
精製に位置補正ができ、部品の搭載位置及びボンディン
グ位置の精度が読められ、品質が向上される0
As described above, according to the present invention, a recognition pattern is formed on the surface of a thick film substrate using a conductor at the same time as a thick film circuit pattern, and a necessary part of the circuit pattern and the recognition pattern are covered with a conductive glass, This glass coating layer is made of a light-colored, semi-transparent layer that provides a contrast between the background color of the thick film substrate and the color of the recognition pattern.This recognition pattern is detected and the position of the thick film substrate is corrected, so that the detection level is is stabilized, highly refined position correction is possible, the accuracy of component mounting position and bonding position can be read, and quality is improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の厚膜混成集積回路基板の製造方法を示す
認識マークを施した押、膜基板の概要平面図、第2図は
この発明の一実施例による厚膜混成集積回路基板の製造
方法を示す認識マークを施した厚膜基板の概要平面図、
第3図は第2図の基板の認識マーク部の拡大断面図であ
る。 1・・・厚膜基・’、LE、5・・・認識パターン、6
・・・ガラス被覆層。 なお、図中同一符号は同−又は相当部分を示す。 代理人 大 岩 冷 雄
FIG. 1 is a schematic plan view of a stamped film substrate with recognition marks showing a conventional method of manufacturing a thick film hybrid integrated circuit board, and FIG. 2 is a schematic plan view of a thick film hybrid integrated circuit board according to an embodiment of the present invention. Schematic plan view of a thick film substrate with identification marks indicating the method;
FIG. 3 is an enlarged sectional view of the recognition mark portion of the substrate shown in FIG. 2. 1... Thick film base・', LE, 5... Recognition pattern, 6
...Glass coating layer. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Hiro Oiwa

Claims (1)

【特許請求の範囲】 +11 厚膜基板面に導電体による厚膜回路パターンを
形成し、電子部品が搭載されるようにし、この厚膜回路
パターン形成と同時に同一導電体によるgmマークを形
成し、上記厚膜回路パターン上の所要部及び上gRマー
ク上に誘電体ガラスで被覆保護し、このガラス被覆層は
上記厚膜基板の地色と上記認識マークの導電体の色との
コントラストを強める薄色の半透明にしておシ、この認
識マークの検出によシ上記厚膜回路パターン上の部品搭
載点及びボンディング点の位置補正がされるようにする
厚膜混成集積回路基板の製造方法。 (2)導電体は錯−パラジウム系金属からなることを特
徴とする特許請求の範囲第1項記載の厚膜混成集積回路
基板の製造方法。
[Claims] +11 Forming a thick film circuit pattern using a conductor on the surface of a thick film substrate so that electronic components can be mounted thereon, forming a GM mark using the same conductor at the same time as forming the thick film circuit pattern, The required parts on the thick film circuit pattern and the upper gR mark are coated and protected with dielectric glass, and this glass coating layer is a thin film that enhances the contrast between the ground color of the thick film substrate and the color of the conductor of the recognition mark. A method for manufacturing a thick film hybrid integrated circuit board in which the color is translucent and the positions of component mounting points and bonding points on the thick film circuit pattern are corrected by detecting the recognition mark. (2) The method for manufacturing a thick film hybrid integrated circuit board according to claim 1, wherein the conductor is made of a complex-palladium metal.
JP23096383A 1983-12-05 1983-12-05 Method of producing thick film hybrid integrated circuit board Pending JPS60121793A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23096383A JPS60121793A (en) 1983-12-05 1983-12-05 Method of producing thick film hybrid integrated circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23096383A JPS60121793A (en) 1983-12-05 1983-12-05 Method of producing thick film hybrid integrated circuit board

Publications (1)

Publication Number Publication Date
JPS60121793A true JPS60121793A (en) 1985-06-29

Family

ID=16916058

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23096383A Pending JPS60121793A (en) 1983-12-05 1983-12-05 Method of producing thick film hybrid integrated circuit board

Country Status (1)

Country Link
JP (1) JPS60121793A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6374530A (en) * 1986-09-17 1988-04-05 Sony Corp Automatic mounting method for component

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6374530A (en) * 1986-09-17 1988-04-05 Sony Corp Automatic mounting method for component

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