JPH07263488A - Semiconductor chip, tab tape, inner lead bonder and manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve an aligning accuracy in an inner lead bonding step in the case of manufacturing TABLSI as compared with aligning using conventional pattern recognition technique. CONSTITUTION:Dummy bumps 21 for alignment are provided on sides of a chip 20. A bonding stage 4 which places the chip 20 is horizontally moved rightward to a TAB tape, the bumps of right side are brought into contact with inner leads of a leftmost end, and a position of the stage 4 at that time is stored. Then, the chip 20 is horizontally moved leftward, the bumps of right side is brought into contact with inner leads of a rightmost end, and a position of the stage 4 at that time is stored. Data of intermediate position is calculated from data of the two positions, and the stage 4 is moved to its intermediate position. A series of operations are conducted for a Y-axis direction. Contact of the bumps with the inner leads is electrically detected.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor chip, TAB
The present invention relates to a tape, an inner lead bonder, and a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a TAB semiconductor device, and a semiconductor chip, a TAB tape, and an inner lead bonder used for implementing the manufacturing method.

[0002]

2. Description of the Related Art The TAB method, which is one of the connection technologies for taking out leads from an LSI chip, not only enables thin and compact high-density mounting, but also, for example, a multi-pin batch bonder of about 100 pins or more. It has several major features, such as suitability for improving productivity, because it is possible to sing. By the way, as described above, the TAB connection technology is intended to be applied to a large number of pins, small-sized, and high-density mounting LSIs.
In the inner lead bonding step (the step of collectively bonding all the bumps on the LSI chip and the inner leads of the TAB tape), it is required that the bumps and the inner leads be accurately aligned. The present invention has been made in view of the above requirements, and relates to a technique for improving alignment accuracy at the time of inner lead bonding in a manufacturing process of a TAB method LSI (hereinafter, referred to as TABLSI).

It is no exaggeration to say that an LSI is completed by integrating various alignments, and there are many steps in its manufacturing process that require alignment. Therefore, various alignment techniques for LSI manufacturing have been researched and developed, but high precision alignment of micron order or higher is required, for example, alignment of a mask and a wafer in a lithography process. In such cases, pattern recognition technology using light is often used. The pattern recognition technology using light has been conventionally applied to the alignment by inner lead bonding when manufacturing a TABLSI. That is, the alignment is performed by the pattern matching method. Hereinafter, a conventional alignment method using pattern matching will be described.

FIG. 7A is a schematic plan view of a chip of a TABLSI manufactured using a conventional alignment method. Referring to the figure, a large number of bumps 1 are formed along the four sides of a square chip 10. These bumps 1 are for exchanging power and signals necessary for signal processing in this LSI with the outside through inner leads (described later) of a TAB tape bonded to them. Alignment marks 11 having a characteristic shape for alignment (in this case, a cross-shaped cross pattern) are formed at two corners of the chip 10 which are diagonally located. The alignment mark 11 is usually formed by etching a metal layer formed on the chip, and is formed at the same time as other aluminum wirings in the aluminum wiring forming step in the wafer process, for example. To be done. Of course, the number of alignment marks 11 may be two or more. Also, the shape of the chip may be rectangular rather than square.

Next, referring to FIG. 7B showing a schematic plan view of the TAB tape, alignment marks 13 having a characteristic shape for alignment are provided at four corners of the device hole 2 of the TAB tape 12. Has been. This alignment mark 13 is
For example, it is formed at the same time when the copper foil of the TAB tape 12 is etched to form the inner leads 3. Figure 7
In the example shown in (b), the planar shape of each alignment mark 13 is a shape in which two beams protruding into the device hole from each of two orthogonal sides of the device hole 2 cross at their tips. There is. Incidentally, FIG. 7B also shows the chip 10 arranged in the device hole 2 together with the TAB tape 12.

Here, the device hole 2 is shown in FIG.
Although only one is drawn, in a normal TAB tape, a large number of device holes 2 as shown in the figure are arranged at predetermined intervals in the longitudinal direction (paper surface, left-right direction) of the long tape. Such a TAB tape is wound on a reel (not shown). At the time of actual inner lead bonding, reel to reel (Reel to
Reel) transports the TAB tape 12 in the longitudinal direction by one device hole and fixes it to the tape clamper (not shown) of the inner lead bonder.
The chip 10 is separately supplied onto a bonding stage (not shown) located below the device hole 2, the bump 1 on the chip 10 and the inner lead 3 around the device hole 2 are aligned, and then both are bonded. This operation is repeated for each device hole.

Chip 10 and TAB tape 1 as described above
Positioning in the conventional inner lead bonding process is performed as follows by using No. 2 and. First, the inner lead bonder is made to remember (teaching) the reference for comparison when performing pattern matching. In this teaching, the alignment mark 13 on the TAB tape
And the reference image of the alignment mark 11 of the chip, the reference position when detecting the position of the TAB tape to be inner lead bonded on the tape clamper, and the chip to be bonded,
When the bump 1 and the inner lead 3 are completely aligned with the reference position for detecting the position on the bonding stage, the alignment mark 11 of the chip is formed.
It is necessary to store in the bonder four types of data relating to the relative positions of the TAB tape and the alignment mark 13 of the TAB tape. Normally, teaching is performed as follows.

First, the first device hole of the TAB tape 12 is sent to the tape clamper and fixed. The bonder takes the alignment mark 13 formed in the first device hole as binary image data into the bonder and uses it as a reference image, and at the same time, reads the position data of the alignment mark 13 on the tape clamper, The position is set as the reference position of the TAB tape on the tape clamper. The binary data of the alignment mark 13 is obtained by irradiating the alignment mark 13 and its peripheral portion with light by a bonder recognition camera (not shown) and binarizing the intensity of the received reflected light at a predetermined slice level. Done by Usually, the part of the alignment mark is bright and the other parts are dark.

Next, the first chip is supplied to the bonding stage for the above-mentioned first device hole. As with the TAB tape, the bonder takes in the alignment mark 11 provided on the first chip as binarized image data and uses it as a reference image, and at the same time the position data of the alignment mark 11 on the bonding stage. Is read, and the position is set as the reference position of the chip on the bonding stage.

After the above operation, using the first device hole and the first chip, the bumps 1 and TA of the chip are formed.
Align the inner lead 3 of the B tape. At this time, the operator directly positions the bumps 1 and the inner leads 3 while looking at the monitor screen (not shown) of the bonder. After the alignment by the operator is completed, the bonder is the alignment data of the first alignment mark of the device hole (in other words, reference image) 1 and the alignment mark of the first chip aligned with this (the same reference mark). The relative position of the two alignment marks when the alignment is completed is calculated from the position data of the image 3) and stored.

Next, the second and subsequent device holes are aligned with the chip automatically based on the reference image and position data taught as described above. That is, with respect to the TAB tape 12 that has been transferred to the bonding position and fixed to the tape clamper, the recognition camera binarizes two or more of the alignment marks 13 located at the corners of the device hole 2 at least diagonally. Capture as image data. Then, the tape clamper and the camera are moved relative to each other so that the binarized alignment mark 13 just captured matches the binarized alignment mark (reference image) of the first device hole that has already been taught ( Normally, the tape clamper is fixed and the camera is moved), and the position of the TAB tape 12 on the tape clamper is detected from the amount of movement at that time. Similarly, the camera necessary for matching the binarization mark 11 of the chip to be aligned with the binarization mark (reference image) of the alignment mark of the first chip that has already been taught. The position of the chip 10 on the bonding stage is detected from the amount of movement.

Then, based on the data of the position of the TAB tape 12 on the tape clamper detected as described above and the data of the position of the chip 10 on the bonding stage, the relative teaching of the TAB tape and the chip which has been previously taught. When the distances and the rotation angles in the X-axis direction and the Y-axis direction of the bonding stage are corrected so that the position data becomes uniform, the alignment is completed, and the inner leads 3 of the TAB tape corresponding to the bumps 1 of the chip are positioned. Will be done.

Here, generally, in the method of aligning two objects, the two objects are first forcibly arranged so as to have a predetermined relative position, and then the two objects are moved from their initial positions. , The method of moving and aligning by a predetermined amount, or the initial placement of the two objects is not particularly forced, and the initial relative position is measured in a state where the two objects are placed, There is a method of determining the movement amount according to the measurement result, but as can be seen from the above description, the conventional alignment method in the inner lead bonding step is the latter method. When measuring the initial relative position between the TAB tape and the chip, the deviation from the reference position on the tape clamper is measured for the TAB tape and the reference position on the bonding stage is measured for the chip. It means that the relative position between the two is indirectly obtained, not directly, as in the case of measuring the deviation.

From this, in the context of the present invention,
Considering the alignment accuracy in the conventional alignment method, the alignment accuracy is determined by the T on the tape clamper.
It can be seen that the accuracy in detecting the position of the AB tape and the accuracy in detecting the position of the chip on the bonding stage have a great influence.

[0015]

As described above, the TA on the tape clamper is formed by the conventional alignment method.
In the pattern matching used to detect the position of the B tape and the position of the chip on the bonding stage, the bonder radiates light to the alignment mark of the chip or the TAB tape and its periphery to binarize the intensity of the reflected light strongly. By doing so, the alignment mark is captured as binarized image data. However, in that case, the alignment accuracy between the alignment marks used for teaching and the actual alignment marks that match the alignment marks, the processing precision such as line width and cross-sectional shape, and the finished state such as color tone and gloss. It is unavoidable that there will be a difference between the two, and the images of the two alignment marks (actual alignment marks aligned with the reference mark) cannot be perfectly matched in practice. And because of this, the TAB on the tape clamper
There is a limit to the accuracy of tape position detection and the accuracy of chip position detection on the bonding stage. That is, the conventional alignment method has a limit in the accuracy of the initial relative position detection between the TAB tape and the chip based on the above cause.

When teaching the relative position between the TAB tape and the chip, the operator aligns the inner lead and the bump, and then the recognition mark of the alignment mark of the TAB tape and the alignment mark of the chip at that time is recognized by the recognition camera. Pattern recognition is performed and relative position data of the TAB tape and the chip should be calculated from each position data and stored in the bonder, but at the time of teaching at this time,
Occurrence of the above error cannot be avoided.

From the above, in the conventional alignment in which the pattern matching method is used to perform the alignment by the pattern recognition using light, the limit of the detection accuracy of the initial relative position between the TAB tape and the chip and the alignment are performed. It is difficult to improve the alignment accuracy because of the limit of accuracy when teaching the relative positions of the two that should be later. For example, at present, when the lead pitch is about 60 μm or less, the occurrence of defects due to the positional deviation between the inner leads and the bumps becomes remarkable, and the non-defective rate in the inner lead bonding process sharply decreases. . Of course, by improving the processing accuracy of the alignment mark and tightening the management of the finished state lot by lot, for example, in the alignment of the mask and the wafer in the lithography process,
It would be possible to increase the alignment accuracy to sub-micron level. However, in order to do so, the performance of all the devices used for depositing the metal film, patterning, etching, etc. when forming the alignment mark must be adjusted to a high level that matches the required alignment accuracy. In addition, process control becomes complicated. For this reason, it is not easy to improve the alignment accuracy by the conventional alignment method.

Therefore, it is an object of the present invention to provide a method of manufacturing a TABLSI capable of easily performing bonding with higher precision than inner lead bonding by a conventional alignment method using light.

Another object of the present invention is TAB as described above.
A semiconductor chip necessary for implementing the LSI manufacturing method,
It is to provide a TAB tape and an inner lead bonder.

[0020]

A method of manufacturing a semiconductor device of the present invention is a method of manufacturing a TAB type semiconductor device, in which a semiconductor chip and a TAB tape are moved relative to each other to form bumps on the semiconductor chip. A method of manufacturing a semiconductor device, comprising: a step of aligning inner leads of the TAB tape with each other; and a bonding step of electrically fixing and connecting the bumps and the inner leads to each other. Of the semiconductor chip directly determined by bringing the positioning member provided on the TAB tape into contact with the positioning member provided on the TAB tape.
After the initial relative position with respect to the AB tape is set as a reference position for determining the movement amount, the semiconductor chip and the TAB tape are relatively moved to a position at the time of bonding.

Further, in the method for manufacturing a semiconductor device of the present invention, as the positioning member provided on the semiconductor chip, conductive dummy bumps dedicated to alignment provided on the surface of the chip are used, and the positioning provided on the TAB tape is performed. The inner lead is used as a member, and the contact between the dummy bump and the inner lead is electrically detected by the presence or absence of electrical conduction between the dummy dump and the inner lead. To do.

Further, in the method for manufacturing a semiconductor device of the present invention, instead of using the inner lead as the positioning member provided on the TAB tape, the alignment is provided so as to project into the device hole of the TAB tape. It is characterized by using a dedicated conductive dummy inner lead.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1A is a schematic plan view showing the semiconductor chip and the inner leads used in the first embodiment of the present invention in an overlapping manner. Further, FIG. 1B is a sectional view thereof. Incidentally, FIG. 1 shows a state in the initial stage of the process in which the alignment between the bump and the inner lead has not been completed yet. Comparing FIG. 1 and FIG. 7, the chip 20 used in this embodiment does not have the alignment mark 11 required for the conventional alignment method. Instead, each of the four sides of the chip 20 is provided with two dummy bumps 21 in addition to the normal (connection) bump 1 for exchanging a power source and a signal with the outside for signal processing. One dummy dump 21 is disposed on each side of the connection bump 1, and the height thereof is higher than that of the connection bump 1, as shown in FIG. Further, the TAB tape used in this embodiment is not provided with the alignment mark 13 which is conventionally required, and the normal (connection) inner lead 3 used for signal processing is projected in the device hole. Only.

In this embodiment, the chip and TA as described above are used.
Using the B tape, alignment is performed by the procedure described below. First, as shown in FIG. 1A, rough alignment is performed so that the inner leads 3 around the device hole are arranged between the dummy bumps 21 on both sides of each side of the chip 20. At the time of this rough adjustment, a conventional pattern recognition technique using light can be used. At this time, the connection bump 1 and the inner lead 3 may be displaced.

Next, when the bonding stage 4 which holds the chip 20 by suction is moved right by one pulse, as shown in the plan view of FIG. The lead 3 _AL comes into contact with the left dummy bump 21 _AL, and the leftmost inner lead 3 _CL comes into contact with the left dummy bump 21 _CL on the lower side of the chip. Here, the chip 20 is provided with wiring (not shown) that electrically short-circuits the dummy bumps 21 _AL and 21 _CL . Therefore, the inner lead 3 _AL → the dummy bump 21 _AL →
In-chip wiring → dummy bump 21 _CL → inner lead 3
An electric path called _CL is formed.

Here, in the TAB tape, as shown in the perspective view of FIG. 3, a test pad 5 corresponding to each inner lead is usually provided at an extension of each inner lead 3. The test pad 5 is used to electrically test the LSI by applying pogo pins 6 to the test pads 5 from the outside after the inner lead bonding is completed. In this embodiment, the test pad 5 is used to detect whether or not the above-mentioned electrical path is formed, in other words, whether or not the inner lead and the dummy bump are in contact with each other at the upper side and the lower side of the chip at the same time. ing. That is, in this embodiment, as shown in the schematic cutaway perspective view of FIG. 4, for each side of the device hole,
The pogo pin 6 that comes into contact with the two inner leads located at the outermost ends is built in the tape clamp par 23. By taking out a connection cable (not shown) from the pogo pin 6, the above-mentioned contact can be electrically detected. The bonder is the tip 20 and the T as described above.
It is detected that the AB tape and the tape are arranged as shown in FIG. 2A, and the data of the position of the bonding stage at that time is stored.

Similarly, the bonding stage 4 is moved leftward, and as shown in the plan view of FIG. 2B, the dummy bump 21 _AR on the right side of the upper side and the inner lead 3 _{AR on} the rightmost side.
, And at the same time, the dummy bump 21 _CR on the lower right side and the inner lead 3 _{CR on} the rightmost side are brought into contact with each other to electrically detect the contact, and the data of the position of the bonding stage 4 at that time is stored.

Next, from the position data of the two bonding stages in the X-axis direction (left and right direction of the paper) obtained as described above, the data of the intermediate position between these two positions is calculated, and the bonding stage 4 is moved to the intermediate position. When it is moved to the position, as shown in the plan view of FIG. 5, the inner leads 3 are arranged right above the connection bumps 1 on the upper and lower sides of the chip respectively, and the alignment in the X-axis direction is completed.

Then, also in the Y-axis direction (vertical direction in the plane of the drawing), the same operation as the above-mentioned alignment in the X-axis direction is performed to complete the alignment on the four sides.

As can be seen from the above description, in the present invention, the initial relative position between the chip and the TAB tape is
The placement of the dummy bumps 21 on the chip and the inner leads 3 of the TAB tape when they first contact each other is directly determined only by the chip and the TAB tape. Therefore, unlike the conventional alignment in which the initial relative position between the chip and the TAB tape is indirectly determined through the recognition camera by pattern matching using light, the alignment according to the present invention requires the chip. There is no decrease in the alignment accuracy due to the initial detection error of the relative position between the tape and the TAB tape. Further, in the conventional alignment method, an error occurs when teaching the relative position of each alignment mark to the bonder when the bump and the inner lead are completely aligned. The alignment accuracy does not decrease due to such a cause, and the alignment accuracy also improves in this respect. According to this embodiment, the conventional value is ± 7μ.
The alignment accuracy, which was only m, could be improved to ± 3 μm.

In the above description, two dummy bumps are provided on both sides of each side of the chip so as to sandwich a normal connection bump (for example, dummy bumps 21 _AL , 21 _{AR on the} upper side parallel to the X-axis direction). Although the example is provided, the number of dummy bumps is not limited to two and may be one for each side. The effect of improving the alignment accuracy in the present invention is brought about by directly determining the initial relative position between the chip and the TAB tape.
The number of dummy bumps does not affect the operation and effect of the present invention. However, if there are two dummy bumps, the deviation between the pitch of the connecting bumps and the pitch of the inner leads can be corrected more finely than in the case where there is only one dummy bump, so that more accurate alignment can be performed.

In the first embodiment described so far, the inner lead of the TAB tape is used to detect that the chip and the TAB tape are arranged at a predetermined initial relative position. That is, although the (connecting) inner lead 3 used for signal processing as the LSI was also used for alignment, a dummy inner lead dedicated for alignment should be provided as in the second embodiment described below. By
The positioning accuracy can be further improved.

FIG. 6 shows the second embodiment of the present invention.
FIG. 3 is a schematic plan view showing a layout of dummy bumps of a semiconductor chip and a layout of inner leads of a TAB tape,
It shows a state in which the alignment in both the X-axis direction and the Y-axis direction is completed. Referring to the figure, in the present embodiment, two dummy bumps 21 are arranged side by side on each side of the chip 20. On the other hand, T
The AB tape is provided with one dummy inner lead 24 corresponding to the two dummy bumps 21. In the present embodiment, as shown in FIG. 6, when the dummy inner lead 24 is at the center of the two corresponding dummy bumps 21, the connecting inner leads 3 are located directly above the corresponding connecting bumps 1. Is designed.

In the present embodiment, first, by the pattern recognition technique using light, each dummy inner lead 24 is inserted between the two corresponding dummy bumps 21.
Adjust roughly. In this case, the inner lead 24 does not have to be located in the middle of the two dummy bumps 21. Next, using the contact between the dummy bump and the dummy inner lead, as in the first embodiment, the X-axis direction and Y
Axial positioning is performed to complete the overall positioning as shown in FIG.

In the first embodiment described above, the connection inner lead 3 used for signal processing as the LSI and the dummy bump 21 are brought into contact with each other to set the initial relative position between the chip and the TAB tape. However, in an inner lead with a narrow pitch that accommodates a large number of pins, both the lead width and the lead thickness are reduced, so that the rigidity is reduced. Therefore, an error may occur in the initial relative position setting due to the deformation caused by the contact with the dummy bump or the subtle lead deformation of the TAB tape from the beginning, and the alignment accuracy as a whole may deteriorate. is there. On the other hand, unlike the connecting inner leads 3, the dummy inner leads 24 in this embodiment have no particular restrictions on the pitch, width, and thickness, and are therefore necessary for preventing deformation due to contact with dummy bumps. It can give rigidity. As a result, in this embodiment, the alignment accuracy can be further improved as compared with the first embodiment.

In the first and second embodiments so far, the height of the dummy bump 21 is higher than that of the connection bump 1. Although this makes the bump forming process more complicated than in the past, the dummy bump and the inner lead (or,
Since only the horizontal movement is required as the movement of the bonding stage for contacting with the dummy inner lead),
There is an advantage that the conventional bonding stage mechanism can be used as it is. On the other hand, the height of the dummy bump and the height of the connection bump may be the same. In that case, in addition to the horizontal movement of the bonding stage, an elevating operation is added. That is, the bonding stage is lowered to a height at which the bumps (dummy bumps) and the inner leads (dummy inner leads) do not come into contact with each other, and then horizontally moved in the X-axis (Y-axis) direction, and again.
Raise the bonding stage to a height where the bumps come into contact with the inner leads. By repeating this horizontal movement and elevation, even if the dummy bumps and the connection bumps have the same height, highly accurate alignment is possible without deformation of the inner leads.

It should be apparent from the above description that the present invention is applicable to square chips and rectangular chips.

[0038]

As described above, the present invention is based on the TAB
At the time of alignment in the inner lead bonding process in the LSI manufacturing, first, the arrangement of the chip and the TAB tape is set to a predetermined relative position, and the respective arrangement at that time is the chip and the TAB. I try to go directly with the tape. When setting the initial relative position, the chip and the TAB tape are electrically detected by detecting that the dummy bump for alignment provided on the chip and the (dummy) inner lead of the TAB tape are in contact with each other. Is detected at a predetermined relative position.

As a result, according to the present invention, it is possible to prevent the alignment accuracy from degrading due to an error in detecting the initial positions of the chip and the TAB tape. Moreover, unlike the conventional alignment method using the pattern recognition technique using light, the alignment accuracy does not decrease due to an error during teaching to the inner lead bonder. In the conventional alignment method using pattern recognition technology, in order to improve the alignment accuracy, a very large investment such as performance improvement of manufacturing equipment and sophistication of process control is required. According to this, the alignment accuracy can be easily increased.

[Brief description of drawings]

FIG. 1 is a perspective view of a chip according to a first embodiment of the present invention.
It is a schematic plan view and a schematic cross-sectional view showing a state in which the tape is arranged in a device hole of the B tape and roughly aligned.

FIG. 2 is a schematic plan view for explaining the manufacturing method of the first embodiment of the present invention in the order of steps, and is a diagram relating to steps after the step shown in FIG.

FIG. 3 is a schematic perspective view showing a test pad provided on an inner lead of a TAB tape.

FIG. 4 is a schematic cutaway perspective view showing the structure of the tape clamper in the bonder used in the first embodiment of the present invention.

FIG. 5 is a schematic plan view showing a state when the alignment in the X-axis direction is completed in the first embodiment of the present invention.

FIG. 6 is a schematic plan view showing a state in which the alignment in the X-axis direction and the Y-axis direction is completed in the second embodiment of the present invention.

FIG. 7 is a plan view of a chip used for manufacturing a conventional TAB LSI and a schematic plan view showing a state when the chip is arranged in a device hole of a TAB tape.

[Explanation of symbols]

1 Connection Bump 2 Device Hole 3,3 _AL , 3 _AR , 3 _CL , 3 _CR Inner Lead 4 Bonding Stage 5 Test Pad 6 Pogo Pin 10, 20 Chip 11, 13, Alignment Mark 12, 22 TAB Tape 21, 21 _AL , 21 _AR , 21 _CL , 21 _CR Dummy bump 23 Tape clamper 24 Dummy inner lead

Claims (7)

[Claims] 1. A method of manufacturing a TAB type semiconductor device, which comprises relatively moving a semiconductor chip and a TAB tape to align a bump on the semiconductor chip with an inner lead of the TAB tape. In a method of manufacturing a semiconductor device, which includes a bonding step of electrically fixing and connecting the bump and the inner lead, in the aligning step, the positioning member provided on the semiconductor chip and the TA
When the semiconductor chip and the TAB tape are bonded after the initial relative position between the semiconductor chip and the TAB tape, which is directly determined by contacting the positioning member provided on the B tape, is set as the reference position for determining the movement amount. A method for manufacturing a semiconductor device, characterized in that the semiconductor device is relatively moved to the position. 2. The method for manufacturing a semiconductor device according to claim 1, wherein when the shape of the semiconductor chip is a right-angled parallelogram, each of the vertical direction and the horizontal direction of the semiconductor chip,
A method of manufacturing a semiconductor device, wherein the setting of the initial relative position and the relative movement to the position at the time of bonding are executed. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the positioning dummy member provided on the semiconductor chip is a conductive dummy bump dedicated to alignment provided on the surface of the chip, and is used for the TAB tape. As the positioning member to be provided, the inner lead is used, and the contact between the dummy bump and the inner lead is electrically detected by the presence or absence of electrical conduction between the dummy dump and the inner lead. A method for manufacturing a characteristic semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 3, wherein instead of using the inner lead as a positioning member provided on the TAB tape, a position provided so as to project into a device hole of the TAB tape. A method of manufacturing a semiconductor device, comprising using a conductive dummy inner lead exclusively for alignment. 5. A semiconductor chip used in the method for manufacturing a semiconductor device according to claim 3, wherein at least one dummy bump is provided on each of the four sides of the chip, and each dummy bump comprises: The dummy bumps arranged on the opposite sides of the chip are combined so as to form a pair, and at least the dummy bumps forming the pair are electrically short-circuited by the wiring provided on the chip. A semiconductor chip characterized by the above. 6. The TAB tape used in the method for manufacturing a semiconductor device according to claim 4, wherein at least one dummy inner lead is provided on each of four sides of the device hole. . 7. An inner lead bonder used in the method for manufacturing a semiconductor device according to claim 3 or 4,
An inner lead bonder, wherein a tape clamper for fixing the TAB tape includes a test pad portion of an inner lead that contacts the dummy chip or a pogo pin that abuts on a test pad portion of the dummy inner lead.