JPS60119748A - Testing process of master slice wafer - Google Patents
Testing process of master slice waferInfo
- Publication number
- JPS60119748A JPS60119748A JP22763783A JP22763783A JPS60119748A JP S60119748 A JPS60119748 A JP S60119748A JP 22763783 A JP22763783 A JP 22763783A JP 22763783 A JP22763783 A JP 22763783A JP S60119748 A JPS60119748 A JP S60119748A
- Authority
- JP
- Japan
- Prior art keywords
- master slice
- wafer
- test
- slice wafer
- test site
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004020 conductor Substances 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 abstract description 40
- 239000000758 substrate Substances 0.000 abstract description 7
- 238000005259 measurement Methods 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000002184 metal Substances 0.000 description 4
- 239000002689 soil Substances 0.000 description 2
- 235000009508 confectionery Nutrition 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明はマスタスライス方式において、ウェーハ上に基
本機能パターンが形成され、配線される前のいわゆるマ
スタスライスウェーハの電気的特性をテストする、マス
タスライスウェーハのテスト方法に関する。Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a master slice method in which a basic functional pattern is formed on a wafer and the electrical characteristics of the so-called master slice wafer are tested before wiring. Concerning wafer testing methods.
マスタスライス方式はウェーハ上に、基本機能パターン
を形成し、必要に応じて素子間の接続方法を変えて一連
の製品を製作する方法である。基本機能パターンが形成
されアルミニウム配縁前のラニーハラマスタスライスウ
ェーハと呼んでいるが、このマスタスライスウェーハの
電気的特性をテストし、不良品を除く必要がある。The master slicing method is a method in which a basic functional pattern is formed on a wafer, and a series of products are manufactured by changing the connection method between elements as necessary. This is called a Ranihara master slice wafer, which has a basic functional pattern formed on it and is not yet aluminum-plated, but it is necessary to test the electrical characteristics of this master slice wafer and eliminate defective products.
従来はロットからコ枚程度のウェーハを抜き取シ、その
全面に電気的特性をテストするためのテストパターンを
形成して電気的測定をおこなっている。この測定結果は
このロットの他のウェーハについても同じ電気的特性を
有するものであるとし、図のＦで示すようにマスタスラ
イスウェーハを直ちに製品化プロセスへ送シ処理してい
た。しかしながら実際には同一ロット内でも電気的特性
が相違しており、従来のテスト方法で＆：ｊｉ品につい
ての特性がバラツク可能性があるという問題があった。Conventionally, approximately one wafer is extracted from a lot, a test pattern is formed on the entire surface of the wafer for testing electrical characteristics, and electrical measurements are performed. This measurement result indicates that the other wafers in this lot have the same electrical characteristics, and the master slice wafer was immediately sent to the production process as shown by F in the figure. However, in reality, electrical characteristics differ even within the same lot, and there is a problem in that the characteristics of &:ji products may vary when using conventional testing methods.
また電気的特性を測定したウェーハは製品化することが
できず無駄となっていた。このことは少址、多品種、短
期間開発を特徴とするマスタスライス方式で効率を下げ
る要因となって−だ。Furthermore, the wafers whose electrical characteristics were measured could not be commercialized and were wasted. This is a factor that reduces the efficiency of the master slicing method, which is characterized by a small footprint, a wide variety of products, and short development times.
本発明は上記事情を考慮してなされたもので、テスト用
ウェーハを無駄にすることなく、製品の特性のバラツキ
を防止できるマスタスジイスウェーハのテスト方法を提
供することを目的とする。The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to provide a test method for master wafers that can prevent variations in product characteristics without wasting test wafers.
この目的を達成するために本発明によるマスタスライス
ウェーハのテスト方法は、マスタスライスウェーハの一
部分のテストサイトに導電性材料の配線によりテストパ
ターンを形成し、このテストパターンによシマスタスラ
イスウェー−”の電ｉ的特性を測定し、測定後テストサ
イトを含むｉメタスライスウェーハ上の導電性材料を剥
離し、この剥離後のマスタスライスウェーハな製品化す
ることを特徴とする。To achieve this objective, the master slice wafer testing method according to the present invention involves forming a test pattern by wiring conductive material on a test site of a portion of the master slice wafer, and using this test pattern to test the master slice wafer. The method is characterized in that the electrical characteristics are measured, and after the measurement, the conductive material on the i-metaslice wafer including the test site is peeled off, and the peeled master slice wafer is manufactured as a product.
以下本発明を図示の一実施例に基づ−て説明する。基本
様能パターンが形成された半導体基板上に絶縁膜λが形
成されたマスタスライスウェーハ基板／に対し、テスト
パターンが形成されるテストサイト！にフォトエツチン
グプロセスでコンタクトホール３を形成する（プロセス
Ａ）。テストサイト！はマスタスライスウェーハ基板／
土の一部分とし、他の部分ｔば製品化に用いられるため
この段階ではコンタクトホールな形成しなり０次に絶縁
膜コ上にメタル層グを全回蒸着しくプロセスＢ）、次に
テストサイト！のみテストパターンを形成する（プロセ
スＣ）。このテストパターンとして例えばインバータが
飴状にｊ’ｌ： ａされたインバータチェインがある。The present invention will be explained below based on an illustrated embodiment. A test site where a test pattern is formed on a master slice wafer substrate/with an insulating film λ formed on a semiconductor substrate on which a basic pattern is formed! A contact hole 3 is then formed by a photoetching process (process A). Test site! is the master slice wafer substrate/
One part of the soil will be used as a part of the soil, and the other part will be used for commercialization, so at this stage a contact hole will be formed.Next, a metal layer will be deposited all over the insulating film (Process B), and then a test site! (process C). An example of this test pattern is an inverter chain in which the inverters are arranged like candy.
このようにして形成されたテストパターンの電気的特性
を測足し、このマスタスライスウェーハの特性をテスト
する。テスト後、テストパターンを形成したメタル層ダ
を剥離する（プロセスＤ）。The electrical characteristics of the test pattern thus formed are measured to test the characteristics of this master slice wafer. After the test, the metal layer on which the test pattern was formed is peeled off (process D).
本実施例ではその剥ｈ＆後のマスタスライスウェーハ基
板／を製品化することに特徴がある。すＩ工ゎち、テス
トサイトｊ以外の部分には、コンタクトホールをあけ電
気配線をすることによシ任意の製品のパターンを形成す
ることができるので、部分ｔを製品化するべくマスタス
ライスウェーハを通常ノ製品化プロセスへ移ス（プロセ
スＥ）。This embodiment is characterized by commercializing the master slice wafer substrate after the peeling process. In the I process, any product pattern can be formed by drilling contact holes and making electrical wiring in areas other than the test site j, so in order to commercialize part t, a master slice wafer is Transfer to the normal productization process (Process E).
なおコンタクトホール３をあけたテストサイトｊにつ込
ても、コンタクトホール３を５ｉｏ２等の絶縁性物質で
覆うことによシ製品のサイトとして用いることができる
。Note that even if the test site j with the contact hole 3 is inserted, it can be used as a site for a product by covering the contact hole 3 with an insulating material such as 5io2.
１だプロセスＣにお込てテストサイトｊにテストパター
ンを形成する際、テストサイトｊ以外の部分乙のメタル
層６をあらかじめ剥離してもよい。When forming the test pattern at the test site j in the first process C, the metal layer 6 in the portion B other than the test site j may be peeled off in advance.
以上の通シ本発明によればテストした後のマスタスライ
スウェーハを製品化できるため、ウェーハを無駄にする
ことがない。またウェーハ全数のテストが可能であるの
で製品の信頼性が向上し歩と一１’Ｊの向上および歩ど
まシの予測ができる。In summary, according to the present invention, a master slice wafer after testing can be commercialized, so that wafers are not wasted. In addition, since it is possible to test all wafers, product reliability is improved, yield improvement and yield prediction can be achieved.
またウェーハ全てにつｂて電気的特性が事前にわかるの
で、マスタスライスウェーハを電気的特性に応じて分類
することができ、Ｊ４適な特性のウェーハを用−て製品
を製造することができる。Furthermore, since the electrical characteristics of all wafers are known in advance, master slice wafers can be classified according to their electrical characteristics, and products can be manufactured using wafers with J4-appropriate characteristics.
また本発明によれば、テストによるウェーハの損失を低
くすることができる。すなわち、従来ではロフト（５枚
）あたり一枚程度の抜き取りをしていたため、約ｆ％の
損失となるが、本発明では、ウェーハあたジグロス数が
７３０チツプで、ｊチップをテストサイトとしてＭいた
場合でも、１％程度の損失で済む。その上全数チェック
であるので電気的特性の測定値の信頼性は従来と０１比
観にならない位高いものとなる。Further, according to the present invention, wafer loss due to testing can be reduced. In other words, in the past, about one chip was extracted per loft (5 chips), resulting in a loss of about f%, but in the present invention, the number of chip losses per wafer is 730 chips, and J chip is used as the test site. Even if it were, the loss would be around 1%. In addition, since all items are checked, the reliability of the measured values of electrical characteristics is much higher than that of the conventional method.
図は本発明によるマスタスライスウェーハのテスト方法
を従来のテスト方法と比較して示した工程図である。
／・・・マスタスライスウェーハ基板、コ・・・」１５
力依願、３・・・コンタクトホール、ｌ・・・メタル層
、！・・・テストサイト。The figure is a process diagram showing a comparison between the master slice wafer testing method according to the present invention and the conventional testing method. /...Master slice wafer substrate, co...''15
Power request, 3...contact hole, l...metal layer,! ...Test site.
Claims (1)
性材料の配線によシテストパターンを形成し、このテス
トパターンによシマスタスライスウエーハの電気的特性
を測定し、測定後テストサイトを含むマスタスライスウ
ェーハ上の導電性材料を剥離し、この剥離後のマスタス
ライスウェーハを製品化することを特徴とするマスタス
ライスウェーハのテスト方法。A test pattern is formed by wiring conductive material on a part of the test site of the master slice wafer, and the electrical characteristics of the master slice wafer are measured using this test pattern. A method for testing a master slice wafer, which comprises peeling off a conductive material and commercializing the master slice wafer after the peeling.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22763783A JPS60119748A (en) | 1983-12-01 | 1983-12-01 | Testing process of master slice wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22763783A JPS60119748A (en) | 1983-12-01 | 1983-12-01 | Testing process of master slice wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60119748A true JPS60119748A (en) | 1985-06-27 |
Family
ID=16864007
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22763783A Pending JPS60119748A (en) | 1983-12-01 | 1983-12-01 | Testing process of master slice wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60119748A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62188241A (en) * | 1986-02-13 | 1987-08-17 | Nec Corp | Manufacture of semiconductor device |
| US5039602A (en) * | 1990-03-19 | 1991-08-13 | National Semiconductor Corporation | Method of screening A.C. performance characteristics during D.C. parametric test operation |
| US5095267A (en) * | 1990-03-19 | 1992-03-10 | National Semiconductor Corporation | Method of screening A.C. performance characteristics during D.C. parametric test operation |
| JPH0474438U (en) * | 1990-11-09 | 1992-06-30 | ||
| JP2006120962A (en) * | 2004-10-25 | 2006-05-11 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
-
1983
- 1983-12-01 JP JP22763783A patent/JPS60119748A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62188241A (en) * | 1986-02-13 | 1987-08-17 | Nec Corp | Manufacture of semiconductor device |
| US5039602A (en) * | 1990-03-19 | 1991-08-13 | National Semiconductor Corporation | Method of screening A.C. performance characteristics during D.C. parametric test operation |
| US5095267A (en) * | 1990-03-19 | 1992-03-10 | National Semiconductor Corporation | Method of screening A.C. performance characteristics during D.C. parametric test operation |
| JPH0474438U (en) * | 1990-11-09 | 1992-06-30 | ||
| JP2006120962A (en) * | 2004-10-25 | 2006-05-11 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
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