JPS60119158U - Input signal disconnection detection device - Google Patents
Input signal disconnection detection deviceInfo
- Publication number
- JPS60119158U JPS60119158U JP1984004915U JP491584U JPS60119158U JP S60119158 U JPS60119158 U JP S60119158U JP 1984004915 U JP1984004915 U JP 1984004915U JP 491584 U JP491584 U JP 491584U JP S60119158 U JPS60119158 U JP S60119158U
- Authority
- JP
- Japan
- Prior art keywords
- detection device
- disconnection detection
- input signal
- clock signal
- signal disconnection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Dc Digital Transmission (AREA)
- Optical Communication System (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の入力信号断検出回路の例を示す図、第２
図は本考案の実施例の回路図である。 ′主要
部分の符号の説明、１・・・ディジタルデータ信号入力
端、２・・・クロック信号入力端、４・・・Ｄ型ＦＦ、
５・・・平均レベル検出回路、７・・・制御回路、８
・・・レーザダイオード駆動回路、１０・・・レーザダ
イオード、１１・・・オアゲート。Figure 1 is a diagram showing an example of a conventional input signal disconnection detection circuit;
The figure is a circuit diagram of an embodiment of the present invention. 'Explanation of symbols of main parts, 1...Digital data signal input terminal, 2...Clock signal input terminal, 4...D type FF,
5... Average level detection circuit, 7... Control circuit, 8
... Laser diode drive circuit, 10... Laser diode, 11... OR gate.
Claims (1)
込みつつ次に続くクロック信号の到来までの間この取込
みデータを葆持するよう構成されたディジタル回路にお
ける入力信号断検出装置であって、前記取込みデータの
保持出力信号と前記クロック信号との論理和を出力する
論理和ゲートと、前記論理和出力の平均レベルを検出す
る平均レベル検出手段とを含み、前記平均レベルに応じ
て前記ディジタル入力データ信号と前記クロック信号の
断状態を検出するよらにしてなる入力信号断検出装置。An input signal disconnection detection device in a digital circuit configured to capture a digital input data signal in synchronization with a clock signal and hold the captured data until the arrival of the next clock signal, the device comprising: an OR gate that outputs a logical sum of the holding output signal and the clock signal, and an average level detection means that detects an average level of the logical sum output, An input signal disconnection detection device configured to detect a clock signal disconnection state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984004915U JPS60119158U (en) | 1984-01-18 | 1984-01-18 | Input signal disconnection detection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984004915U JPS60119158U (en) | 1984-01-18 | 1984-01-18 | Input signal disconnection detection device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60119158U true JPS60119158U (en) | 1985-08-12 |
Family
ID=30480943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984004915U Pending JPS60119158U (en) | 1984-01-18 | 1984-01-18 | Input signal disconnection detection device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60119158U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003110505A (en) * | 2001-09-27 | 2003-04-11 | Sumitomo Electric Ind Ltd | Optical transmitter and wavelength division multiplexing transmission system |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58105689A (en) * | 1981-12-18 | 1983-06-23 | Fujitsu Ltd | Control channel selecting system |
-
1984
- 1984-01-18 JP JP1984004915U patent/JPS60119158U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58105689A (en) * | 1981-12-18 | 1983-06-23 | Fujitsu Ltd | Control channel selecting system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003110505A (en) * | 2001-09-27 | 2003-04-11 | Sumitomo Electric Ind Ltd | Optical transmitter and wavelength division multiplexing transmission system |
| JP4569064B2 (en) * | 2001-09-27 | 2010-10-27 | 住友電気工業株式会社 | Optical transmitter and wavelength division multiplexing transmission system |
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