JPS6011851B2 - Receiving machine - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AFT circuit for a receiver having a digital electronic channel selection device.

First, an example of such a digital electronic channel selection television receiver will be explained with reference to FIG.

In FIG. 1, reference numeral 1 indicates a fin-tuned tuner, which has a variable capacitance diode, for example, as a resonant element in each tuning circuit, and when a tuning voltage Vc, which will be described later, is supplied to this, the voltage Vc is changed. Channels compatible with the signal can be received. Further, 2 is a video intermediate frequency amplifier, 3 is a video detection circuit, 4' is a video amplifier, and 5 is a receiving tube. Furthermore, 10' is shown as a tuning control circuit that forms a tuning voltage Vc, and this includes "a tuning voltage Vc corresponding to a broadcast channel is preset in the state of a digital code, and at the time of reception, the preset selection voltage Vc is preset. The desired channel is selected from the local voltage Vc.

That is, 11 is a channel memory, which has a fixed address, for example 1, corresponding to the number of channels that can be received, and each address has an n-bit digital code A that indicates the channel selection voltage Vc corresponding to that channel. , ~An, and can be read out. Note that this memory 11 is a non-luminescent memory that retains its contents even if the power is turned off. Further, 12 is an addressing circuit, which includes channel selection switches S, -S,.

are connected, and switches S, ~S,. When any one of them is operated, the corresponding address in the memory 11 is specified. Furthermore, 13 is a reversible counter formed by the channel selection codes A, ~An at the time of presetting, 14 is a pulse oscillation circuit that generates a pulse Po which becomes the counter input, 15 is a memory control circuit, and Sm is a mode switch. By switching Sm, the memory 11 is switched between a pledge mode (preset mode) and a read mode (tuning mode). Furthermore, 16 is a write pulse forming circuit, 17
18 is a reset circuit, 18 is a D-A converter that converts the channel selection code A, ~An into a channel selection voltage Vc, Su is a switch that sweeps the receiving frequency in the upward direction when setting the pre-IJ, and S
Similarly, d is a switch for sweeping in the downward direction.

Further, AFT voltages Vu and Vd are formed by the circuits 21 to 23.

That is, a video intermediate frequency signal is taken out from the intermediate frequency amplifier 2, and this is supplied to the frequency discrimination circuit 22 through the band amplifier 21, and the so-called S-shaped voltage Vs as shown in FIG. 2A is taken out. is supplied to the shaping circuit 23, and the AFT voltage V, for example, as shown in FIG.
U and V eyes are formed. That is, the normal tuning point f. On the other hand, the fin pressure Vu is (f.-1.2MHZ) due to (f
. It becomes "1" in the frequency range (-50kHz), and becomes "0" in the other frequency ranges, and the voltage Vd is
(f.

It becomes "1" in the frequency range from 150 kHz to 1.2 MHz, and becomes "0" in the other frequency ranges. Note that this range ((f. 5 skin HZ) is the tuning range.Furthermore, 31 to 39 are logic circuits, which control the switch Su or S at the time of presetting.
When d is turned on, the pulse Po from the oscillation circuit 14 is supplied to the counter 13 as an addition input or a subtraction input.

Therefore, when presetting a broadcast channel, first the mode switch Sm is switched to the reset side contact P'.

Then, the counter 13 is reset by the reset circuit 17, and the memory 11 is placed in the write mode by the control circuit 15. Therefore, switch S, is turned on, and then switch Su is turned on.

Then, by turning on the switch S, the corresponding address in the memory 11 is designated through the designation circuit 12. Furthermore, by turning on the switch Su, the output of the inverter 31 becomes "1", and therefore the pulse P is generated from the oscillation circuit 14. is supplied to Kawanta 13 as an addition input through AND circuit 32 and further through OR circuit 33,
The contents of the counter 13 start from [00...0] and increase sequentially. Since the contents of this counter 13 are stored in the memory 11 and the ○1A converter 18, the channel selection voltage Vc corresponding to ~An is formed in the code of the counter 13, and this voltage Vc is counter 1
Each time the content of 3 increases by [1], it increases by ΔV, and therefore, the reception frequency of the tuner 1 gradually increases, and the reception frequency is adjusted. Therefore, in the Kanto region, when the broadcast of the first channel can be received, the switch Su is turned off.

At this time, if the switch Sd is turned on as necessary, the pulse P from the oscillation circuit 14 is generated by the output of the inverter 34.
. is supplied as a subtraction input to the memory 11 through the AND circuit and the OR circuit 36, and therefore, the tuning voltage Vc decreases, so that fine tuning of the receiving frequency can be achieved. Then, when the switch Su (or Sd) is turned off, the output of the AND circuit 37 becomes "1".

Therefore, at this time, if the AFT voltage Vu is "1",
Output pulse P of the oscillation circuit 14. is obtained through the AND circuit 38, and this pulse P. is supplied as an addition input through the OR circuit 33. Also, switch Su (or S
d) is turned off, if the AFT voltage Vd is "1", the output pulse P of the oscillation circuit 14. But, AND circuit 3
9 and is supplied to the counter 13 through the OR circuit 36. And this operation is Vui“0
”, is performed until Vd=“0”, therefore, Vu=V
When d=“0”, the reception frequency is f. soil 5
0kHz, that is, AFT was performed. Then, after a certain period of time after the switch Su (or Sd) is turned off, that is, when the AFT is in a steady state, the forming circuit 16 uses the output of the AND circuit 37 to
A write pulse is formed in the control circuit 1.
5 to the memory 11, the address of the memory 11 specified by the switch S, is erased, and the contents of the counter 13 at this point in time are written to the specified address of the memory 11.

Therefore, the tuning codes A, -An corresponding to the tuning voltage Vc of the first channel are written in the address of the memory 11 designated by the switch S,. Next, switch S2 is turned on, and then switch Su is turned on.

Then, another corresponding address in the memory 11 is specified by the switch S2, and the contents of the counter 13 are further increased by turning on the switch Su. Accordingly, the channel selection voltage Vc is further increased and the reception frequency is increased. The sweep continues. Therefore, when the third channel can be received, if the switch Su is turned off, the third channel tuning voltage Vc is written in the address corresponding to the switch S2 in the memory 11 with the tuning codes A, ~An. . Then, in the same manner, the tuning voltage V of the broadcast channel is
c can be preset in the memory 11.

On the other hand, when receiving a broadcast, the switch Sm is switched to the reception side contact R, and the switches S, to S. Turn on the desired channel among o. Then, the control circuit 15 sets the memory 11 to read mode, and if the switch S2 is turned on, the corresponding address in the memory 11 is designated and the third channel selection code corresponding to the switch S2 is set. A, ~An are read out,
This is supplied to the converter 18 through the counter 13, converted to the tuning voltage Vc, and supplied to the tuner 1. Therefore, the third channel can be received. In addition, in this case, since the switches Su and Sd are off, the AFT voltage V
If u or Vd is obtained, counter 1 is set correspondingly.
3, the tuning codes A, -An supplied from the counter 13 to the converter 18 are corrected, and therefore AFT is performed. In this manner, according to the channel selection control circuit 10, it is possible to electronically preset broadcast channels, and it is also possible to electronically select a desired channel from among the preset broadcast channels.

AFT can also be performed digitally. However, in such a channel selection control circuit 10, when selecting a channel, the AFT
may malfunction.

That is, although the level of the output voltage Vs of the frequency discrimination circuit 22 is constantly changing due to differences in the degree of modulation due to the input electric field and image components, the gain of the amplifier 21 decreases at both ends of the band of the amplifier 21. Therefore, the level fluctuation of the voltage Vs is large at both ends of this band. Therefore, when the frequency is at the edge of the band, the level of the voltage Vs fluctuates around the threshold levels V, V2 of the shaping circuit 23, so the AFT voltages Vu, Vd are as shown in FIG. 3A. It will be divided like this. Therefore, when tuning, for example, as shown in Figure 2C, if tuning is performed at the frequency f at the end of the band, Vu = "0" and Vd = "0" due to division. , AFT locks at this frequency as well.

Then, if the image changes and the modulation depth becomes deeper, or the input electric field increases and the division disappears, the AFT is pulled into the normal tuning point. Therefore, this AFT either locks to the wrong frequency or misses the normal tuning point f. Even if it locks, it will take a long time to lock. Therefore, the present invention aims to eliminate such AFT malfunctions. Therefore, in the present invention, as shown in FIG. 2D, for example, even if the tuning is detuned to the frequency f when selecting a channel, when the voltage Vu is obtained, the tuning point f is reached.

The receiving frequency is continuously swept in the direction of tuning point f. When the voltage Vd is obtained, the sweep is stopped and the tuning point f is reached. It is designed to return the reception frequency to . An example of this will be explained below.

In FIG. 6, 41 indicates a detection circuit, which in this example is connected to the addressing circuit 12 and switches S,
~S,.

It is designed to detect when any of these are manipulated. Reference numeral 42 denotes a switch circuit, which is controlled by a switch Sm, and is switched to the state shown in the figure when selecting a channel, and to the opposite state when presetting. Furthermore, 43 is a pulse forming circuit that forms the timing pulse Pt, 44 and 45 are RS flip-flop circuits, and 51 to 56 are logic circuits.

Note that the other circuits are configured similarly to the device shown in FIG.
Therefore, when the switch S, for example, is turned on at time t, the address corresponding to the switch S in the memory 11 is designated by the designation circuit 12, and the tuning codes A, to An of the first channel are transferred from the memory 11 to the counter 13. The tuning voltage V of the first channel is supplied to the converter 18 through
c is formed and supplied to the tuner 1.

Therefore, the reception state of the first channel starts from the time point 3. At this time, if the frequency is tuned to f, as shown in FIG. 2C, for example, as shown in FIG. The voltage Vu is obtained from .

When the switch S is operated at time t, this is detected by the detection circuit 41, and the detection output is sent to the reset terminal R of the flip-flop circuits 44 and 45 through the switch circuit 42 and the OR circuits 52 and 54. The output Pu of the flip-flop circuits 44 and 45
, Pd becomes “0” from time point et al., as shown in FIG. 4B and C.
” (actually, as will be clear from the description below, at time t
, previously it was also “0”). Furthermore, the detection output of the detection circuit 41 is supplied to the formation circuit 43, and as shown in FIG. 4D, a timing pulse Pt is formed at a time slightly later than time t.

Therefore, when Vu="1" and Pt="1",
In FIG. 4, the output of the logic AND circuit 51 becomes "1" at a time point, and this is supplied to the set terminal S of the flip-flop circuit 44, so that Pu="1" from time t2. Then, this output Pu is supplied to the AND circuit 38 through the OR circuit 55, and the output of the AND circuit 37 is "1".
” Therefore, as shown in FIG.
3 as a summation input. In this case, if the voltage Vu is obtained even once, the flip-flop circuit 44 is set, so even if the voltage Vu is divided thereafter, Pu=
The state of "1" continues, so the counter 13 receives the output pulse P of the oscillation circuit 14.

is continuously supplied, so the reception frequency of the tuner 1 continuously increases from the frequency at time t. Then, at time t3, the reception frequency becomes (f).

15 HZ), Vu becomes "0", but the receiving frequency further increases and reaches the normal tuning frequency f. After passing through, it reaches the riko frequency (f. 50kHz). Then, the AFT voltage Vd becomes "1" as shown in FIG.
, Pu="0" and the addition input to the counter 13 disappears. At this time, the voltage Vd is connected to the AND circuit 39 through the OR circuit 56, and the output of the AND circuit 37 is "1", so as shown in FIG. 4G, the output pulse P of the oscillation circuit 14 is . is passed through the AND circuit 39,
Furthermore, it is supplied as a subtraction input to the counter 13 through the OR circuit 36, and the reception frequency decreases. In this case, the pulses P are combined as addition inputs to the counter 13 during period songs 2 to t4'. (Fig. 4E), the last pulse sets Pu="0" and Vd="1", so the pulse P. is supplied to the counter 13 as a subtraction input, then the first pulse P. The receiving frequency is (f
. 150kHz), and Vd=“0”. Also, even if the voltage Vd becomes “1” at the moment, the Pt value becomes “0”.
”, the flip-flop circuit 45 is not set and the state of Pd="0" continues. Therefore, the first pulse P after time t4.

Accordingly, the receiving frequency is approximately pulse P than the frequency (f. 50kHz). The counter 13 is lowered by one cycle of , and the counter 13 stops in this state. Therefore, the tuner 1 is tuned to the frequency range of (f. 50 kHz) for the first channel. Then, in steady state, Pt="
0", even if the voltage Vu or Vd is obtained after tuning, the flip-flop circuits 44 and 45 are not set. Therefore, the state of Pu="0" and Pd="0" continues, and If the voltage Vu or Vd is obtained, it is passed through the OR circuit 55 or 66 to the AND circuit 38 or 3.
9, AFT is performed in the same way as in the case shown in FIG.

Furthermore, when selecting a channel, if the tuning is at the higher end of the band, contrary to the above, the voltage Vd is obtained, the flip-flop circuit 45 is set, and the counter 13 performs subtraction counting. When the voltage Vu is obtained, the flip-flop circuit 45 is reset and the pulse P is output.

Only one is supplied to the counter 13 as an addition input, resulting in a tuned state. On the other hand, during presetting, switch Su (
or Sd) to select the broadcast channel,
Next time the switch Su (or Sd) is turned off,
When the output of the AND circuit 37 becomes "1", it is supplied to the OR circuits 52, 54 and the forming circuit 43 through the switch circuit 42, so that AFT is performed in the same way as when selecting a channel.

In this way, AFT is performed when selecting a channel during reception and when selecting a channel during presetting. In this case, according to the present invention, if the AFT voltage Vu or Vd is obtained even once, the flip-flop circuit 44 or 4
5 is set and the oscillation pulse P is sent to the counter 13.

is supplied and the opposite AFT voltage Vd or Vu is obtained, the AFT locks. Therefore, even if the AFT voltage Vu or Vd is disconnected, the AFT locks reliably and rapidly. Additionally, in the past, if there was an audio (intermediate frequency) signal En of an adjacent channel below the desired channel as shown in Figure 5A, the AFT would sometimes lock to this when selecting a channel. However, according to the present invention, for the signal En of the adjacent channel, the AFT voltage En for upward sweep is obtained as shown in FIG. Therefore, it does not lock to the signal En.

The present invention can also be applied to a case where the memory 11 and the designation circuit 12 are not provided and the sweep selection is performed using the output of the counter 13, or to an FM receiver.

[Brief explanation of drawings]

FIG. 1 is a system diagram of an example of a channel selection device, FIGS. 2 to 5 are waveform diagrams for explaining this invention, and FIG. 6 is a system diagram of an example of this invention. 1 is an electronically tuned tuner, 11 is a memory, 12 is an addressing circuit, 13 is a counter, 14 is an oscillation circuit, and 18 is a DA converter. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1 Based on the reception operation, the contents of the counter are set to a value corresponding to the reception frequency, this value is converted from D to A to form a tuning voltage, and this tuning voltage is supplied to the electronically tuned tuner. In the receiver that receives the frequency specified in the above reception operation, an intermediate frequency signal is supplied to a frequency discrimination circuit to obtain an AFT voltage having a different polarity depending on the polarity of the deviation from the normal tuned frequency, and the above reception When the AFT voltage becomes one polarity due to operation, a bistable circuit is set, and based on the set output, counting input is continuously supplied to the counter to perform addition or subtraction counting. When the polarity of the AFT voltage is reversed, the above-mentioned bistable circuit is reset, and the addition count or subtraction count of the above-mentioned counter is reversed, and AFT is performed by performing this counting until the above-mentioned AFT voltage can no longer be obtained. Machine.