JPS5810889B2 - Senkiyokusouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tuning device for a so-called electronically tuned tuner using a voltage-controlled variable reactance element as a tuning element. For example, by converting this binary code into a pulse width modulation signal and smoothing it, a DC voltage whose magnitude changes depending on the selected channel is obtained.
This DC voltage is supplied to an electronic tuner to receive the selected channel, and in addition to realizing particularly simple and reliable AFT operation, when the AFT correction amount reaches a predetermined value or more, it is stored in the memory. The stored binary code is rewritten to one corresponding to the regular tuning point, so that the channel selection operation can be carried out smoothly.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings, taking the case of a channel selection device for a color television receiver as an example.

FIG. 1 shows the overall configuration of the channel selection device. Reference numeral 10 denotes a clock pulse generator, which generates a clock pulse A having a frequency of, for example, 4 MHz and a period τ of 0.25 μsec.

You can get it. 20 is this clock pulse A.

A timing counter that counts
sec, pulse A1 with pulse width τ=0.25μsec
The period is 4.096 m5ec and the pulse width is 2.048.
Sequentially frequency-divided pulses A up to pulse A14 of m5ec
1 to A14 form a 14-bit code, and therefore the state of the code changes in 214=16384 ways with T=4.096 m5ec as one round period.

30 is a channel memory, which has addresses corresponding to, for example, 16 receiving channels, and each address contains a 14-bit tuning code corresponding to that channel, and the fact that that channel is a low channel of VHF broadcasting. A band indication signal indicating whether it is a high channel or UHF broadcast can be stored in memory.

The channel memory 30 is configured such that, after the channel selection code and band instruction signal corresponding to the channel are stored in each address by a program operation described later, the contents are retained even if the power is cut off.

40 is an addressing circuit for addressing, that is, for example, 16 channels to be made to correspond to each desired channel.
switches 80 to S16, and each switch 81 to S16.
16, an address counter 41 that obtains an addressing signal consisting of a 4-bit code, and an address counter 41 that outputs 16 output lines L1 to L16 according to the addressing signal from the address counter 41. One end of the switches 81 to S16 is connected to the output lines L1 to L16 of the decoder 42, respectively.
The other end is connected in common to the switching transistor 43
The neon tubes N1 to N16 are connected to the output lines L1 to L16 of the decoder 42, respectively.
The collector output of the transistor 43 is supplied to an inverter 44, and the output of the inverter 44 is a pulse A9 with a period of 0.128 m5ec from the timing counter 20 mentioned above.
The output of the NAND circuit 45 is supplied to the address counter 41, and this becomes "0".
The counter 41 increments each time there is a yell.

The address designation signal from the address counter 41 is then supplied to the channel memory 30.

Reference numeral 50 denotes a band instruction signal forming circuit, in which one end of a VHF low channel switch SL, a high channel switch SH, and a UHF switch SU are grounded, and the signals obtained at the other end are connected to inverters 51L, 51H, and 51.
NAND circuits 52L, 52K and 52 through U respectively.
The band instruction signal is supplied from the memory 53 to the channel memory 30.

Reference numeral 60 denotes a channel memory control circuit, which is provided with a mode changeover switch 61 and a write switch 62. During programming, that is, the switch 61 stores a channel selection code and a band instruction signal corresponding to the channel in each address of the channel memory 30 in advance. This switch 61
One end of the write switch 62 is grounded, the signal obtained at the other end is supplied to the NAND circuit 63 through the inverter 64, and the output of the NAND circuit 63 is supplied to the NAND circuit 66. Supplied.

From the NAND circuit 66, a memory rewriting circuit 140, which will be described later, is connected.
The rewrite command PM is supplied from the NAND circuit 66, the output of the NAND circuit 66 is supplied to the command signal forming circuit 65 via the inverter 67, and the circuit 65 supplies a write or read command signal to the channel memory 30.

Further, the signal PA from the switch 61 is applied to the NAND circuit 52L of the band instruction signal forming circuit 50 described above.

52H and 52U.

70 is a channel selection code generation counter, which counts sweep pulses (described later) during programming, generates 14-bit channel selection codes B1 to B14, and stores them in the channel memory 3.
On the other hand, the signal PA from the mode changeover switch 61 of the channel memory control circuit 60 is supplied to the inverter 71.
The collector output of the switching transistor 43 of the addressing circuit 40 and the collector output of the transistor 74 of the time constant circuit 73 that detects the rise of the power supply voltage are supplied to the monostable multivibrator 75. The output of the multi-by-break 75 is supplied to a NAND circuit 72, and the output of the NAND circuit 12 is supplied to this channel selection code generation counter 70 through an inverter 76. The 14-bit channel selection codes C1 to C14 thus generated are supplied to the channel selection code generation counter 70, and are used as output codes B1 to B14 of the counter 70 as they are.

Further, the collector output of the transistor 43 and the collector output of the transistor T4 are supplied to the NAND circuit 77,
The monostable multivibrator 78 is triggered by the rise of the output of the NAND circuit 17, and its output is set to 10m5e, for example.
A positive pulse M1 having a pulse width of c is generated, and is further passed through the inverter 79 to generate a negative prohibition pulse PG, and while this negative prohibition pulse PG is generated, the AFT operation described later is stopped. .

80 is a sweep pulse generation circuit for generating the above-mentioned sweep pulses during programming; in this example, either an upward sweep or a downward sweep can be selected, and for each, either a low-speed sweep or a high-speed sweep can be selected. In this case, a low speed up sweep switch 81FU, a low speed down sweep switch 81FD, a high speed up sweep switch 81CU, and a high speed down sweep switch 81CD are provided, and each switch outputs a signal that becomes "0" when turned on. is obtained, and this switch 81FU.

Signals from 81FD, 81CU and 81CD are supplied to NAND circuits 821, 822, 871 and 872 through inverters 811, 812, 861 and 862, respectively.
On the other hand, the period from the timing counter 20 is T=4.09
Pulse A14 of 6 m5ec is supplied as a high-speed sweep pulse to NAND circuits 871 and 872, and pulse A14 is also supplied to frequency divider 86 and divided by, for example, 1/64, so that the divided period is 262.144 m5ec. The pulses are supplied to NAND circuits 821 and 822 as slow sweep pulses.

In this example, the configuration is such that a correction pulse for AFT is given to the channel selection code generation counter 0, and therefore the frequency divider 8
The output of 6 is also supplied to NAND circuits 881 and 882, and the NAND circuits 881 and 882 are connected to inverters 84 and 882, respectively.
A determination output EUED formed by an AFT circuit 130, which will be described later, is supplied through the AFT circuit 5.

Furthermore, sweep switch 81FU. 81FU, 81CU, 8
The output of 1CD is supplied to the NAND circuit 82, and the signal obtained by inverting the output by the inverter 83 is sent to the NAND circuit 881,
882.

The output of this NAND circuit 88L882 is the NAND circuit 821
, 822 are supplied to NAND circuits 831 and 832, and the outputs of NAND circuits 831 and 832 are supplied to NAND circuits 841 and 842 together with the outputs of NAND circuits 871 and 872 via inverters 891 and 892. The outputs of 841 and 842 are NAND circuits 851.85
2.

The NAND circuits 851 and 852 are supplied with the inhibit pulse PG generated when switching channels and turning on the power, as described above.

An upward sweep pulse and a downward sweep pulse are obtained from the outputs of the NAND circuits 851 and 852, and these pulses are supplied to the channel selection code generation counter 70, and the counter 70 is incremented in the addition direction or the subtraction direction.

If the counter 70 steps in the direction of addition, the receiving frequency becomes higher, and if it steps in the direction of subtraction, the receiving frequency becomes lower.

Further, the upward sweep pulse and the downward sweep pulse are supplied to the OFF circuit 87, and the output PUD of the OR circuit 87 is supplied to the NAND circuit 146 of the memory rewriting circuit 140, which will be described later.

Reference numeral 90 denotes a pulse width modulation circuit, for example, as shown in FIG. The period of T=4.
096m5ec's A14 is flip-flop circuit 9
1 is supplied to the set side of pulse A14, and the flip-flop circuit 91 enters the set state at the falling edge of pulse A14, and its output pulse Pw becomes "1". Circulating codes A1 to A14 and channel selection code generation counter 7
The same bits of each of the channel selection codes B1 to Bl4 starting from 0 are supplied, and these exclusive OR circuits 9
The outputs of 01 to 914 are supplied to the OR circuit 92, and the output Po of this OR circuit 92 is supplied to the reset of the flip-flop circuit 91, and when this falls from "1" to "0", the flip-flop circuit 91 is in the reset state. Then, the output pulse Pw becomes "0".

Therefore, as is clear from FIG. 3, the circular codes A1 to
A) When 4 returns from the state (11111111111111) to the state (00000000000000), the output pulse Pw becomes "1" and the cyclic code A1 to A1
4 does not match the channel selection codes B1 to B14, the output of one of the exclusive OR circuits 901 to 914 is "1", and therefore the output PO of the OR circuit 92 is "1", and the circulating codes A1 to A14 matches the channel selection codes B1 to B14 within the cycle period T, the outputs of the exclusive OR circuits 901 to 914 all become "0", and therefore the output PO of the OR circuit 92 becomes "0" and is output. Pulse Pw becomes "0", and output pulse Pw becomes (000
00000000000) until it matches the tuning codes B1 to B14, and the pulse width of the output pulse Pw changes when the tuning codes B1 to B14 change.

Reference numeral 100 denotes a low-pass filter that smoothes the output pulse Pw of the pulse width modulation circuit 90 and extracts the average value of the DC voltage.

110 is an electronically tuned tuner, which supports VHF tuner and UHF tuner.
A voltage-controlled variable reactance element such as a variable capacitance diode is used as each tuning element, and in the case of a VHF tuner, the tuning coil can be switched between a low channel and a high channel. There is.

Then, according to the band instruction signal from the channel memory 30, switching between the VHF tuner and the UHF tuner and VH
The F tuner is switched between a roll channel and a high channel, and a low pass filter 10 is installed in its tuning element.
A DC voltage from 0 is supplied as a tuning voltage, and the reception frequency is determined by this tuning voltage.

Reference numeral 120 denotes a video intermediate frequency amplification circuit, and although not shown in the figure, the output thereof is connected to a video detection circuit, etc., as in a normal color television receiver.

Further, 130 is an AFT circuit.

This AFT circuit 130 performs frequency discrimination on the image carrier wave taken out from the intermediate frequency amplification circuit 120 to obtain an AFT voltage.
Furthermore, the configuration is such that a discrimination output EUED is formed from the AFT voltage.

FIG. 4 is a connection diagram of a part of the AFT circuit 130, where 131 indicates an input terminal to which the AFT voltage VT is supplied from the frequency discrimination circuit, and 132U and 132D are output terminals of discrimination outputs EU and ED, respectively.

As shown in FIG. 5A, the AFT voltage vT becomes a predetermined voltage V0 at the video intermediate frequency f0, and when the frequency is higher or lower than this, the voltage changes in an S-shaped curve centered around V0. It is.

Further, a differential amplifier is configured by transistors 133A and 133B, and transistors 134A and 134
B constitutes a differential amplifier, and one transistor 133A of these differential amplifiers.

Reference voltages V1 and V2 (where Vl>V0>V2) are applied to the bases of the transistors 134A, respectively, and an AFT voltage VT is applied to the bases of the other transistors 133B and 134B.

The collector output of transistor 133B is supplied to the base of transistor 1350, the collector output is supplied to the base of transistor 136, and the collector output, that is, the discrimination output EU, is guided to output terminal 132U via a diode.

Further, the collector output of the transistor 134B is supplied to the base of the transistor 1370, and the collector output, that is, the discrimination output ED is connected to the output terminal 132 via a diode.
Guided by D.

Now, as shown in Figure 5, the frequency of the video carrier wave is (fo-
Δf) and the AFT voltage VT is greater than the reference voltages V1 and V2, transistor 133A is off and transistor 133B is on, so that transistor 1
35 is turned off and the transistor 136 is turned on, and the discrimination output EU is "0" as shown in FIG. “1” as shown in Figure C
It is.

Then, the frequency of the video carrier wave is (fo−Δf) and (f0
+Δf), that is, at the normal tuning point, the transistor 133B is turned off and the transistor 136 is turned off, so the discrimination output EU becomes "1".

At this time, the discrimination output ED remains "1".

When receiving color TV radio waves, Δf is 50 (KHz
) The reference voltages v1 and V2 are selected so that the voltages are approximately equal to .

Furthermore, the frequency becomes higher than (f0 + Δf), and AFT
When the voltage VT becomes smaller than V2, the discrimination output EU becomes “1”.
'', but the on/off states of transistors 134A and 134B are reversed, transistor 134B is turned off, and transistor 137 is turned on, so that the discrimination output E
D becomes "0".

When the discrimination output EU is "0", the local oscillation frequency is increased to the normal tuning point, and the discrimination output ED is
When is "0", on the contrary, the local oscillation local wave number is lowered to bring it to the normal tuning point.

Further, at the normal tuning point, the discrimination outputs EUED are both "1", and no correction is performed at this time.

For this purpose, a correction pulse (channel splitter 8
6 output).

If the discrimination output EU is "0", the NAND circuits 881, 83
1,841,851 and the inverter 891, and if the discrimination output ED is "0", the NAND circuits 882, 832°8
A downward correction pulse is applied to the counter 70 via 42.852 and an inverter 892.

Note that sweep switches 81FU, 81FD, and 81CU are operated by NAND circuits 881 and 882.

When any of 81CD is pressed, the discrimination output E
Priority is given to switch operation so that no correction pulse is generated even if U or ED becomes "0".

140 is a memory rewriting circuit which is a feature of the present invention.

The memory rewriting circuit 140 includes monostable multivibrators 141 and 142, a counter 143, and a decoder 144.
, a flip-flop circuit 145, and a NAND circuit 146
, 147, and an inverter 148.

The monostable multivibrator 141 is triggered by the output M1 of the monostable multivibrator 78, and the counter 14 is triggered by the output M2 of the monostable multivibrator 141.
3 is reset and the monostable multivibrator 142 is triggered.

The counter 143 is supplied with the sweep pulse PUD applied to the channel selection code generation counter 70 through the NAND circuit 146, and is counted.

In this case, the output M2 of the monostable multivibrator 141
A signal obtained by passing the signal PA through the inverter 148 is supplied to the NAND circuit 146, and at the time of channel selection and after the prohibition pulse PG disappears, the counter 143 receives the sweep pulse PU.
D is supplied.

Then, the flip-flop circuit 145 is set by the output generated on the n-th output line Ln of the decoder 144, the flip-flop circuit 145 is reset by the output M3 of the monostable multivibrator 142, and the output M4 of the flip-flop circuit 145 and the monostable The output M3 of the multi-by-break 142 is supplied to the NAND circuit 147,
A rewrite command PM is obtained as the output.

This rewriting command PM is sent to the channel memory control circuit 60.
, the command signal forming circuit 65 operates and the current contents of the counter 70 are written into the memory 30.

To program with the above device, reset the channel selection code generation counter 70, then switch the mode selector switch 61 to the contact a side, and if the channel allocation is in the Kanto region, first correspond to channel 11. The switch S1 for specifying the address to be set is turned on.

When the switch S1 is turned on, the transistor 43 in the addressing circuit 40 is turned on, and its collector output becomes "0". Therefore, the output of the inverter 44 becomes "1", and one pulse A9 from the timing counter 20 is output. Each time, the output of the NAND circuit 45 becomes "0" and the address counter 41 increments.

The 4-bit code from the address counter 41 is converted by the decoder 42, and when the code determined according to the switch S1 is reached, the output obtained on the output line L1 of the decoder 42 becomes "0", which causes the transistor 43 is turned off, the output of the NAND circuit 45 comes to hold "1", and the counter 41 stops advancing. From this, an addressing signal of the code corresponding to the switch S1 is supplied to the channel memory 30. An address corresponding to switch S1 is designated.

Next, the VHF low channel switch SL to which channel 1 belongs is turned on.

When switch SL is turned on, the output of inverter 51L becomes "1" in band instruction signal forming circuit 50,
Since the output PA of the mode changeover switch 61 is "1", the output of the NAND circuit 52L is "0", and this is supplied as a band instruction signal from the memory 53 to the tuner 110 via the channel memory 30, and the tuner 11
At 0, band switching is performed to the low channel of the VHF tuner.

Next, for example, the high-speed up sweep switch 81CU of the sweep pulse generation circuit 80 is pressed to turn it on.

When the switch 81CU is turned on, the output of the inverter 861 becomes "1", and the pulse A14 with a period of T=4.096 m5ec is sent to the channel selection code generation counter 70 as a high-speed rising sweep pulse via the NAND circuits 871, 841, 851. The tuning codes B1 to B14 from the counter 70 start from the state (00000000000000) as shown in FIG.
It changes sequentially in the upward direction every cycle period T=4.096 m5ec.

Therefore, since the circulation codes A1 to A14 change every time τ = 0.25 μsec, which is the pulse width of the pulse A1, the pulse width of the output pulse Pw of the pulse width modulation circuit 90 changes from zero as shown in the figure. Starting from the beginning, the tuning voltage increases by τ every cycle T, and accordingly, the tuning voltage from the low-pass filter 100 increases by, for example, about 2 mV every cycle T, and the reception frequency at the tuner 110 gradually increases.

For example, when the user is looking at the screen and is ready to receive channel 1, he or she releases the high-speed upward sweep switch 81CU to turn it off.

When the switch 81CU is turned off, the supply of high-speed upward sweep pulses to the counter 70 is cut off, and the counter 70 stops advancing.Then, the tuning codes B1 to B14 are set such that the tuner 110 receives one channel. Stops while the tuning voltage is supplied.

Then, the writing switch 62 is turned on.

When the switch 62 is turned on, the output of the inverter 64 becomes "1" in the channel memory control circuit 60, and since the mode changeover switch 61 is switched to the contact a side and its output PA is "1", the output of the NAND circuit 63 is turned on. Since the output becomes "0" and the rewrite command pM is "1", the output of the NAND circuit 66 changes from "0" to "1", the output of the inverter 67 changes from "1" to "0",
First, an erase pulse PE is supplied from the command signal forming circuit 65 to the channel memory 30.
As described above, the contents of the address designated as corresponding to channel 1 are erased, and then the write pulse PI is supplied to this address to select the state corresponding to channel 1 from channel selection code generation counter 70. The station codes B1 to B14 and the band instruction signal from the memory 53 of the band instruction signal forming circuit 50 are written.

Next, when writing "3 channels", the same thing is done. With the mode changeover switch 61 switched to the contact a side, first turn on the address designation switch S2 that should correspond to 3 channels, and then turn on the low channel switch. Turn on SL and then e.g. fast up sweep switch 8
1CU is turned on, and when it is ready to receive 3 channels, the switch 81CU is turned off, and then the writing switch 62 is turned on. In this case, the switch 81CU is turned on.
When 1CU is turned on, the tuning code generation counter 70 starts from the state where it generates the tuning code corresponding to the previous one channel, and reaches the state where it generates the tuning code corresponding to the next three channels. It becomes like this.

In this way, the channel selection code and band instruction signal corresponding to each channel can be sequentially written into each address of the channel memory 30.

When turning on the low-speed ascending sweep switch 81FU instead of turning on the high-speed ascending sweep switch 81CU, the channel selection code generation counter 70 selects the high-speed ascending sweep pulse 64.
Driven by a slow rising sweep pulse with twice the cycle, the tuning codes B1 to B14 from this are 64T = 262.144m
The pulse width modulation circuit 90 changes sequentially every 5ec.
The pulse width of the output pulse Pw increases by τ every 64T, the tuning voltage from the low-pass filter 100 increases by about 2 mV every 64T, and the time required to change the receiving frequency is 64 times that of the above case. .

When turning on the high-speed downward sweep switch 81CD or the low-speed downward sweep switch 81FD, the channel selection codes B1 to B14 from the channel selection code generation counter 70 sequentially change in the downward direction.
By appropriately operating the U, 81FD, 81CU, and 81CD, it is possible to write a channel selection code that will receive each channel in the best condition.

In one embodiment of the present invention, even during such programming, the AFT
is working, therefore the sweep switch 81FU,
If you bring it within the AFT loose pull-in range by turning on any one of 81FD, 81CU, and 81CD, it will automatically be pulled into the normal tuning point even if you turn off the sweep switch.

AFT is not necessarily required at the time of programming, and it is possible to set the normal tuning point by operating the sweep switch.

Further, while the sweep switch is turned on, the correction pulse for AFT is prohibited from being supplied to the counter 70 through the NAND circuits 881 and 882.

After completing the program operation in this way, the mode changeover switch 61 is switched to the contact side.

To select a channel, one of the switches S1 to S16 corresponding to the channel to be selected may be turned on while the power is turned on.

When the power is turned on, the mode selector switch 61 is switched to the contact side, so the signal PA from this is "0", while the switch 62 is off and the output of the inverter 64 is also "0".
Since it is "0", the output of the NAND circuit 63 is "1",
Since the rewriting command PM is "1", the output of the NAND circuit 66 is "0", and therefore the output of the inverter 67 is "1", and the command signal forming circuit 65 outputs the signal from the channel memory 3.
0 is supplied with a read pulse PR.

When the power is turned on, for example, the address counter 41 of the address designation circuit 40 is reset, and the code from this point on specifies an address corresponding to one channel, and therefore corresponds to one channel of the channel memory 30. A channel selection code corresponding to one channel and a band instruction signal indicating that it is a low channel of VHF are read from the address, and the band instruction signal is supplied to the tuner 110 to perform band switching. At the moment of input, transistor 7
4 is turned on and its collector output becomes "0", but after, for example, 50 m5ec has elapsed, the transistor 74 is turned off and its collector output rises to "1", and this rise causes the monostable multivibrator 75 to rise. When triggered, the output becomes "1" for a certain period of time. In this case, the signal PA from the mode changeover switch 61 is "0" and the output of the inverter 71 is "1", so the output of the NAND circuit 72 is "0" for this certain period of time. ”, therefore the inverter 76
output becomes "1", and the channel selection codes C1 to C14 corresponding to one channel read out from the channel memory 30 by this constant time width pulse PB are supplied to the channel selection code generation counter 70, and these are sent to the counter as they are. There are 10 output codes B1 to B14.

For example, when the switch S2 is turned on to receive 3 channels, an address designation signal designating an address corresponding to the 3 channels is sent from the address counter 41 to the channel memory 30 by the same operation as during programming.
The channel selection code and VH corresponding to the 3 channels are supplied to the memory 30 from the addresses corresponding to the 3 channels.
A band instruction signal indicating that the F channel is the low channel is read out, and the band instruction signal is supplied to the tuner 110 to perform band switching.

Then, when the address designation signal designating the address corresponding to the three channels is obtained from the address counter 41 in this way, the transistor 43 turns from on to off and its collector output rises from "0" to "1". The rising edge triggers the monostable multivibrator 75, which triggers the channel selection code generation counter 70 in the same way as described above.
The pulse PB is supplied to the channel memory 30, and the channel selection codes C1 to 3 corresponding to the three channels are read out from the channel memory 30.
C14 is supplied to the channel selection code generation counter 70, and becomes the output codes B1 to B14 of the counter 70 as is.

Therefore, the pulse width of the output pulse Pw of the pulse width modulation circuit 90 becomes a constant value corresponding to the 3 channels, and the tuning voltage from the low-pass filter 100 becomes a constant value corresponding to this, and the tuner 110 outputs the 3 channels. channel is received.

The same thing applies when trying to receive other channels.

In this tuning operation, when a channel corresponding to the tuning code C1 to C14 read out from the channel memory 30 is received, if the tuning point deviates from the normal tuning point due to temperature fluctuations, etc., the direction of the deviation A discrimination output EU or ED is generated from the AFT circuit 130, and a correction pulse is added or subtracted from the channel selection code transferred to the channel selection code generation counter 70 until a normal tuning point is reached.

Then, the transistor 4 when any of the switches S1 to S16 is turned on to switch channels when selecting a channel.
The monostable multivibrator 78 is triggered by the fall of the collector output of No. 3, and a prohibition pulse PG of, for example, 10 m5ec is generated. Therefore, after turning on the switches 81 to S16, the NAND circuits 851 and 8 are activated for 10 m5ec.
No pulse appears at the output of 52, and during this time the AFT described above
Operation is temporarily stopped.

By temporarily stopping the AFT operation at the time of channel switching in this manner, it is possible to avoid the inconvenience of being drawn to a point other than the desired normal tuning point.

That is, by operating the switches S1 to S16, the corresponding channel selection codes C1 to C14 are transferred from the channel memory 30 to the counter 70, and the outputs B1 to B14 of the counter 70 are transferred.
A predetermined tuning voltage is generated by using the switch S1 to S16, but there is always a time delay between when the switches S1 to S16 are operated and when the tuning voltage at the predetermined level corresponding to the operated switch is generated. When AFT operation is activated,
Although there is a risk of a malfunction in which the target channel is not drawn, such a risk can be eliminated by temporarily stopping the AFT operation.

For the same reason, the monostable multivibrator 78 is triggered by the output of the time constant circuit 73 during the period from when the power is turned on until the channel selection voltage corresponding to one channel is formed in this example. I am trying to generate this.

FIG. 6A shows that when any of the switches S1 to S16 is turned on during channel selection, the collector output of the transistor 43 falls and the output of the NAND circuit 77 rises, and at this rise, the monostable multivibrator 78 is triggered,
The output M1 shown in FIG. 6B is generated, and the above-mentioned inhibit pulse PG becomes that shown in FIG. 6C.

Then, the channel selection codes C1 to C14 are read out from the memory 30 by specifying the address by operating the switch.
The reception frequency of the electronic tuning tuner 110 is determined by the following steps. If the received frequency does not reach the regular tuning point at this time, the AFT operation is performed, and while the output M2 of the monostable multivibrator 141 is generated, the AFT operation is performed. The correction pulse PUD (FIG. 6F) is supplied to the counter 143 via the NAND circuit 146, and counted, and the output line of the decoder 144 becomes "1" one after another.

Although the tuning codes C1 to C14 are determined at the time of programming to be the regular tuning points, deviations from the regular tuning points may occur due to temperature drift of the electronic tuning tuner 110, changes over time, etc. That's what happens.

When n correction pulses PUD are applied to the counter 143, the output line Ln of the decoder 144 becomes "1" as shown in FIG. 142 output M3, the flip-flop circuit 1
45 is reset, its output signal will be as shown in FIG. 6H.

Since the signal M4 and the signal M3 are supplied to the NAND circuit 147, the rewriting command PM shown in FIG. 6 is generated at its output.

This rewriting command PM is sent to the channel memory control circuit 60.
is supplied to a NAND circuit 66.

This is substantially the same as turning on the write switch 62 during programming.

That is, in addition to the rewrite command PM, the erase pulse P
0 is generated, the contents of the specified address in the channel memory 30 are erased, and then a write pulse PI is generated, and the channel selection codes B1 to B14 are written from the channel selection code generation counter 70 to this address.

The written channel selection codes B1 to B14 are different from the previously programmed channel selection codes.

In other words, this is the channel selection code obtained by changing the original channel selection code by AFT.

For example, if (n+1) correction pulses for AFT are generated as shown in FIG. 6F, (n+1) pulses are added to the counter 70 where the original channel selection code is stored. Alternatively, the channel selection code resulting from the subtraction is rewritten.

Of course, if the number of correction pulses for AFT does not reach n, the flip-flop 145 will not be set and the memory 30 will not be rewritten.

As described above, according to the present invention, a simple and reliable AFT operation can be realized for an electronically tuned tuner.

In other words, in conventional electronic tuning tuners, the AFT
The frequency value corrected based on the voltage differs from channel to channel, so it is necessary to switch the correction sensitivity for each channel, and the configuration is also complicated.

However, in the present invention, it is only necessary to determine the direction of correction, and once the direction of correction is determined, it is possible to automatically bring the tuning point to the normal tuning point, and AFT can be performed easily and reliably. .

Further, according to the present invention, it is possible to solve the problem that the tuning point deviates from the AFT pull-in range due to temperature drift, aging, etc. of the electronic tuning tuner 110, and the program has to be re-programmed again.

In other words, when a channel corresponding to the channel selection code programmed in the memory 30 is received, it is detected that the amount of correction by AFT to make the tuning point a regular tuning point has reached a predetermined value or more. By this detection, the tuning code corresponding to the regular tuning point is automatically written into the memory 30 in place of the original tuning code, and the next tuning is performed. Sometimes they fall out of the AFT's pull range and are prevented from reprogramming the tuning code.

At the same time, since the tuning point is located at a lopsided point in the AFT pull-in range, it is possible to eliminate the drawback that a good reception condition cannot be obtained immediately after the channel selection operation.

In the embodiment of the present invention described above, the correction pulses PUD supplied to the channel selection code generation counter 70 are directly counted, and when the number reaches n, rewriting is performed. In addition to this, a buffer is prepared separately from the counter 70, and a channel selection code read from the channel memory 30 is set in this buffer.The contents of the counter 70 and the contents of the buffer are compared, and the difference between the two is determined. It is also possible to rewrite the memory 30 when the value exceeds a predetermined value.

In addition, in the embodiment of the present invention described above, a pulse signal whose pulse width is modulated by a tuning code is obtained, and this is smoothed to form an analog signal, that is, a tuning voltage. However, the present invention is not limited to this, and the channel selection code may be converted into a channel selection voltage using a DA converter including a switching element and a weighted resistor.

[Brief explanation of drawings]

FIG. 1 is a system diagram of an embodiment of the present invention, FIG. 2 is a system diagram of a pulse width modulation circuit, FIG. 3 is a time chart used for explanation, FIG. 4 is a partial connection diagram of an AFT circuit, and FIG. FIG. 5 is a waveform diagram used in the explanation, and FIG. 6 is a time chart used in the explanation of the memory rewriting circuit. 10 is a clock pulse generator, 20 is a timing counter, 30 is a channel memory, 40 is an addressing circuit, 60 is a channel memory control circuit, 70 is a channel selection code generation counter, 80 is a sweep pulse generation circuit, 90
110 is a pulse width modulation circuit, 110 is an electronic tuning tuner, 13
0 is an AFT circuit, and 140 is a memory rewriting circuit.

Claims (1)

[Claims] A memory in which a channel selection code corresponding to each station is stored, an addressing means for specifying an address of this memory, and a DA conversion means for converting the channel selection code read from the memory into an analog signal; An electronic tuning tuner whose receiving frequency is switched in accordance with this analog signal, a discrimination circuit which discriminates the tuning state of this electronic tuning tuner, and an output of this discrimination circuit that selects the above-mentioned tuning code only when the tuning state is out of alignment. A channel selection device comprising a correction means for changing, and a means for writing the changed channel selection code into the memory in place of the original channel selection code when the correction pulses reach a predetermined number.