JPS5950131B2 - television receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION When performing AFT on a television receiver, as shown by the solid line in FIG.
For p, the band can be expanded to about 2M)k on the lower side, but on the upper side, it is 1.5
The band can only be expanded to M1-k.

Therefore, even though the pull-in range of AFT can be widened to about 2Ml below the normal tuning point fp, it is only 1M wide above the normal tuning point fp.
．． 5MI-k, Th cannot be made very wide.

Therefore, when tuning, if the received frequency is largely detuned upward, the AFT may not operate and may not lock to the normal tuning point fp.

In view of these points, the present invention aims to widen the upper pull-in range of the AFT, particularly in a television receiver having a digital channel selection device.

Now, if we obtain an AFT voltage Vs with the characteristics shown by the solid line in Figure 2A for the video carrier signal, then by the audio carrier signal of the same channel we obtain the characteristic (fs is The AFT voltage Vs of the sound carrier frequency) is obtained, but from the frequency (fp11,5M)k), the frequency < f
In the band p+2.5M)k), Vs=Q.

Therefore, in the case of this AFT voltage Vs, when selecting a channel, the reception frequency (video carrier frequency) changes from frequency f2 to frequency (
fp+1.5MFk), a negative AFT voltage Vs is obtained, while if it is lower than the frequency fp, a positive AFT voltage Vs is obtained over a wide band from frequency Dp2M)k) to frequency f2. When selecting a channel,
If Vs=O, this means that the receiving frequency is equal to the frequency (fp
This is thought to be because it is higher than +1.5M)k).

This invention makes use of such a point. That is, when selecting a channel, if the AFT voltage Vs is not obtained even after a specified time has passed after switching channels, this means that the receiving frequency is It is assumed that the detuning is higher than (f, +1, 5MFk), and the receiving frequency is swept downward,
Once the AFT voltage Vs is obtained, AFT is performed using this AFT voltage Vs.

An example of this will be explained below.

In Fig. 1, 1 indicates an electronically tuned tuner---
- This has a variable capacitance diode, for example, as a resonant element in each tuning circuit, and by supplying a tuning voltage Vc, which will be described later, to this, a channel corresponding to the level of the voltage Vc can be received.

In addition, 2 is a video intermediate frequency amplifier, 3 is a video detection circuit, and 4 is a video intermediate frequency amplifier.
is a video amplifier, and 5 is a picture tube.

Further, numeral 10 indicates a tuning control circuit for forming a tuning voltage Vc, which includes a tuning voltage Vc corresponding to a broadcast channel.
c is preset in the form of a digital code, and at the time of reception, the one corresponding to the desired channel is extracted from the preset channel selection voltages Vc.

That is, 11 is a channel memory, which has, for example, 10 addresses corresponding to the number of channels that can be received, and each address can store the tuning voltage Vc corresponding to that channel in the form of a digital code Ai. , and can also be read out.

Note that this memory 11 is a nonvolatile memory that retains its contents even if the power is turned off.

Further, 12 is an addressing circuit, to which channel selection switches 81 to SIO are connected, and switches 81 to
When any of the SIOs is operated, the corresponding address in the memory 11 is specified.

Furthermore, 13 is a reversible counter that forms a channel selection code Ai during presetting, 14 is a pulse oscillation circuit that generates a pulse PO that is input to the counter, 15 is a memory control circuit, and Sm is a mode switch, which is operated by switching the switch Sm. Accordingly, the memory 11 is switched between a write mode (preset mode) and a read mode (tuning mode).

Furthermore, 16 is a write pulse forming circuit, 17 is a reset circuit, 18 is a D-A converter that converts the tuning code Ai into a tuning voltage Vc, Su is a switch that sweeps the receiving frequency in an upward direction during presetting, and Sd is the same. This is a switch that causes the switch to sweep in the downward direction.

Further, the circuits 21 to 23 control the AFT voltage Vu.

Vd is formed.

That is, a video intermediate frequency signal is taken out from the intermediate frequency amplifier 2, and is supplied to the frequency discrimination circuit 22 through the bandpass amplifier 21, where it is subjected to an AFT as shown in FIG. 2A.
A voltage Vs is taken out, and this voltage Vs is supplied to the shaping circuit 23, and the level v1. For example, the AFT command voltage Vu as shown in FIG. 2B is set as the threshold level of v2.
, Vd are formed.

That is, for the normal tuning point fp, the voltage Vu is "1" in the frequency range from (fp-2MHz) to (fp-50 &), and in other frequency ranges, it is "1".
“0”, and the voltage vd is (fp+50k)
k) It becomes "1" in the frequency range of Karahoho (fp+1, 5M) k), and becomes "0" in the other frequency ranges.

Note that this range (f2±50kFk) is the normal tuning range.

Furthermore, 31 to 37 are logic circuits, which supply the pulse Po from the oscillation circuit 14 to the counter 13 as an addition input or a subtraction input when the switch Su or Sd is turned on during presetting.

Further, 41 to 43 are rising trigger type RS flip-flop circuits, 45 to 47 are pulse forming circuits (delay circuits) that form an output pulse after a specified time when there is an input, and 49 is a detection circuit, which is In this example, it is connected to the addressing circuit 12 and detects when any of the switches 81 to S1o is operated.

Further, 51 to 59 are logic circuits.

These circuits 41 to 59 perform the operation at the time of channel selection described above.

That is, first, when presetting a broadcast channel, the mode switch Sm is switched to the preset side contact P.

Then, the counter 13 is reset by the reset circuit 17, and the memory 11 is placed in the write mode by the control circuit 15.

Therefore, switch S1 is turned on, and then switch Su is turned on.

Then, by turning on the switch S1, the designated circuit 1
2, the corresponding address of the memory 11 is designated.

In addition, by turning on the switch Su, the output of the inverter 31 becomes "1", and therefore, the pulse Po from the oscillation circuit 14 passes through the AND circuit 32 and further passes through the OR circuit 3.
3 as an addition input to the counter 13, and the contents of the counter 13 start from [00...0] and increase sequentially.

Since the contents of this counter 13 are supplied to the D-A converter 18, the code At of the counter 13 is
A channel selection voltage Vc corresponding to is formed, and this voltage Vc increases by ΔV each time the content of the counter 13 increases by [1]. Therefore, the receiving frequency of the tuner 1 gradually increases, and the sweeping of the receiving frequency is performed. It will be done.

Therefore, in the Kanto region, when the broadcast of the first channel can be received, the switch Su is turned off.

At this time, if the switch Sd is turned on as necessary, the pulse P from the oscillation circuit 14 is generated by the output of the inverter 34.
o is supplied to the memory 11 as a subtraction input through an AND circuit 35 and an OR circuit 36, and therefore, the channel selection voltage Vc
Since this decreases, fine tuning of the receiving frequency can be achieved.

Then, when the switch Su (or Sd) is turned off, the output of the AND circuit 37 becomes "1", so a write pulse is formed in the forming circuit 16, and this pulse is passed through the control circuit 15 to the memory 11. The address of the memory 11 specified by the switch S1 is erased, and this switch Su (or Sd
) is written to the specified address in the memory 11.

Therefore, the tuning code A1 corresponding to the tuning voltage Vc of the first channel is written to the address of the memory 11 specified by the switch S0.

Next, switch S2 is turned on, and then switch Su is turned on.

Then, another corresponding address in the memory 11 is specified by the switch S2, and the contents of the counter 13 are further increased by turning on the switch Su. Accordingly, the channel selection voltage Vc is further increased and the reception frequency is increased. The sweep continues.

Therefore, when the third channel can be received, switch S
When u is turned off, the tuning voltage Vc of the third channel is written in the address corresponding to the switch S2 of the memory 11 in the state of the tuning code A2.

Then, in the same manner, the tuning voltage Vc of the broadcast channel is
can be preset in the memory 11.

On the other hand, when receiving a broadcast, the switch Sm is switched to the reception side contact R, and among the switches 81 to SIO, one of the desired channel, for example, the switch S1, is turned on.

Then, the control circuit 15 sets the memory 11 to read mode, and the memory 1 corresponding to the switch S1
1 address is specified.

Further, the detection circuit 49 detects that the switch S1 is turned on.
As shown in FIG. is supplied as a read pulse.

Therefore, the channel selection code A1 of the address specified by the switch S0 is read out, and this code A1 is stored in the counter 1.
3 and its contents are set to A1, and
This is supplied to converter 18 and converted into channel selection voltage Vc.

Therefore, from time t2, which is slightly delayed from time t1, the first channel is selected.

In this case, with respect to the tuning state of the first channel, the reception frequency (video carrier frequency) is strictly speaking: i frequency (fp + 1.5M ratio) or more, ii frequency fp to (fp + 1.5M ratio) If between iii-
If it is between the frequency (fp-2M ratio) and f, it is either iv if it is below the frequency (fp-2M ratio), and depending on these cases i - iv, the following AF is performed.
T is done.

When the detection pulse Pd is obtained at time t1, this pulse Pd is supplied to the set terminal S of the flip-flop circuit 41.
The output Q1 is "1" from time t1 as shown in FIG. 3B.
", and since the pulse Pd is supplied to the reset terminal 7-R of the flip-flop circuit 42 through the OR circuit 59, its output Q2 is at the time t as shown in FIG. 3C.
Furthermore, since the pulse Pd is supplied to the set terminal S of the flip-flop circuit 43, its output Q3 becomes "1" from time t1 as shown in the third diagram (as will be clear from the description below). As such, before time t1, Ql
, Q2="0", Q3="1").

Then, at time t2, the first channel is selected, but in this case, the AFT voltage Vs cannot be obtained, so as shown in FIG. 3E and F, Vu, Vd="0". ”
It is.

Since the pulse Pd at the time t1 is also supplied to the forming circuit 45, the pulse P5 is taken out from the forming circuit 45 at the time t3 when a predetermined period τ5 has elapsed from the time t1, as shown in FIG. 3G. .

Since Q1="1" at time t3, this pulse P5 is supplied to the set terminal S of the flip-flop circuit 42 through the AND circuit 52, and Q2 becomes "1" from time t3.

Therefore, after time t3, Q2. Since Q3=“1”, the output pulse PO of the oscillation circuit 14 passes through the AND circuit 55 and further passes through the OR circuits 56 and 36 to the third pulse.
It is supplied as a subtraction input to counter 13 as shown in Figure H.

Therefore, the reception frequency for the first channel gradually decreases from time t3.

Then, at time t4, the receiving frequency changes to frequency (fp+1.5
Mf), a negative AFT voltage Vs is obtained,
Vd="1'".

Then, this voltage Vd is freely transmitted through the OR circuit 51.
Since it is supplied to the reset terminal R of the flip-flop circuit 41 and further supplied to the reset terminal R of the flip-flop circuit 42 through the OR circuit 59, Ql and Q2 become "0" from time t4.

Therefore, the output pulse Po of the oscillation circuit 14 is no longer supplied to the counter 13 through the AND circuit 55 from time t4.

However, since Vd = '1' at time t4 and Q3 = '1', the pulse PO is
, through an AND circuit 54, and further through an OR circuit 56, 36.
is supplied to the counter 13 as a subtraction input.

Therefore, even after time t4, the reception frequency continues to decrease.

Then, at time t5, when the receiving frequency drops to the frequency (fp + 50), Vd becomes "0".

Therefore, the pulse Po that had been supplied to the counter 13 through the AND circuit 54 is no longer supplied after time t5.

In this state, the receiving frequency is the frequency (f p-
50k)k) to (fp+50kI-k) and is therefore correctly tuned to the first channel.

ii. Frequency f, to (f, +1.5M)k) In this case, when the first channel is selected at time t2, Vd = "1" immediately, so as shown in Fig. 4. As shown, the operation after time t4 in case i is performed.

That is, since Vd becomes "1" at time t2, Q becomes "0" and the pulse Po is supplied as a subtraction input to the counter 13 through the AND circuit 54, and the reception frequency decreases.

Then, at time t6, the receiving frequency (f p+50k)k)
When it drops to 0, Vd becomes 0, so the pulse Po
is no longer supplied to the counter 13.

Therefore, from this point on, the device is correctly tuned to the first channel.

Incidentally, a pulse P5 is obtained from the forming circuit 45 after a period τ5 from time t1, but at this time, Q=“0”, so Q2=“0.” continues.

iii Case between frequency (fp-2M) and f In this case, when the first channel is selected at time t2, Vu=“1”, contrary to case ii.

Therefore, the pulse Po is supplied to the counter 13 as an addition input through the AND circuit 53, and the reception frequency increases.

Then, when the reception frequency reaches the frequency (fp-50k)k), Vu becomes "1", and the pulse PO is no longer supplied to the counter 13, so that from now on, it is correctly tuned to the first channel.

And in these cases 1-iii, at the time or -
When the reception frequency falls within the frequency band (fp ± 50 degrees), Q3 = "1", so if Vu or Vd = "1" due to detuning, AND circuit 53 or 54
The pulse PO is supplied to the counter 13 as an addition input or a subtraction input.

Therefore, the receiving frequency is locked within the frequency band (fp±501), that is, AFT is performed.

iv Frequency/wave number (fp-2M) or less In this case, AFT is not performed because it is outside the AFT pull-in range.

That is, although the first channel is received at time t2,
As shown in FIG. 5, since Vu and Vd="0", a pulse P5 is obtained at time t3, as in the case of i, and the reception frequency is lowered and detuned.

Then, at time t7 (that is, before the AFT voltage Vs is obtained by the audio carrier signal of the adjacent broadcast channel), as shown in FIG. 5I,
A pulse P6 is taken out from the forming circuit 46, and this pulse P6 passes through an AND circuit 57 to the flip-flop circuit 4.
3, so from time t7 to Q
3=“0”, and the counter 13 stops counting.

At the same time, the pulse P6 is output from the AND circuit 57 to
It is supplied as a read pulse to the memory 11 through the control circuit 58 and the control circuit 15.

Therefore, at time t7, the contents of the memory 11 are again supplied to the counter 13, and the contents of the counter 13 are made equal to the contents at time t1, so that from time t7 the first channel is again received.

However, even in this case, the receiving frequency is the frequency (fp-2
M&) below.

Further, since the pulse P6 is also supplied to the forming circuit 47 through the AND circuit 57, as shown in FIG. 6J,
Pulse P7 is taken out at time t8, which is a little later than time t7, and this pulse P7 is supplied to the reset terminal R of the flip-flop circuit 42 through the OR circuit 59, and after time t8, Q2 becomes "O".

In other words, in the case of iv, when the first channel is selected, the downward sweep is performed only once, but it returns to the receiving frequency at the time of channel selection, and from then on, the operation stops in that state, and the AF
T is not done.

Tuning and AFT are performed as described above, but in this case, according to the present invention, even if the reception frequency is largely detuned toward the higher side at the time of tuning, as indicated by i, the AFT
It is possible to perform AFT over a wide band.

Moreover, in that case, it is possible to quickly lock to the normal tuning point without requiring a special signal detection circuit.

Furthermore, as shown in iv, even if the channel is tuned outside the lower band of the AFT band, a detuned black and white image is immediately played back at time t3, making it easy for the viewer to play back. Can be adjusted.

Furthermore, this operation does not cause channel skipping when the broadcast ends.

Moreover, not only a signal detection circuit is not required, but also adjustment and assembly are not required.

Furthermore, it is easy to integrate into an LSI, and it is possible to realize a television receiver with low cost increase and high marketability.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of an example of this invention, and FIGS. 2 to 5 are waveform diagrams for explaining this invention. 1 is an electronic tuning tuner, 11 is a memory, 12 is an addressing circuit, 13 is a counter, 14 is an oscillation circuit, and 18 is a D
-It is an A converter.

Claims (1)

[Claims] 1 Based on the tuning operation, the contents of the counter are set to a value corresponding to the selected channel, this value is converted from D to A to form a tuning voltage, and this tuning voltage is supplied to the electronically tuned tuner. In the television receiver that selects the channel specified by the channel selection operation, the intermediate frequency signal is frequency-discriminated to obtain an AFT voltage, and AFT is performed using this AFT voltage. A television receiver in which when the voltage is at a predetermined value, the reception frequency is lowered to be within the pull-in range of the AFT.