JPS5929413Y2 - Preset receiver with clock - Google Patents

Description

[Detailed description of the invention] The present invention relates to a preset receiver with a clock that is configured to switch between displaying received frequency and time on one display, and in particular, the present invention relates to a preset receiver with a clock that is configured to switch between displaying received frequency and time on one display. The present invention relates to a novel memory status display device that is configured to release the memory status by a display switching signal and that also has a display function to identify the memory status.

In conventional preset receivers equipped with storage devices,
The memory key that controls writing to the storage device uses a non-locking switch such as a push key, and is configured to be automatically released after a predetermined period of time after the key is operated. A commonly used display means is to turn on an indicator lamp by operating a memory key.

Therefore, this invention focuses on the point that the reception frequency display and the time display are switched and displayed on one display, and by canceling the memory state with a display switching signal to the time display, the reception frequency display after the memory key operation is To provide a preset receiver with a clock, which is configured to display that the receiver is in a memory state while the receiver is displayed.

Embodiments of the present invention will be described below with reference to the drawings.

1 consists of a PLL synthesizer, etc., and is a part of a digital tuner that performs a sweep operation by counting the sweep pulses from a sweep pulse generator 2. The frequency display output is led to a display 5 via a gate circuit 3 and a decoder 4. It is configured so that

6 is set to the memory state by the write signal W from the flip-flop 9 which is set by the control signal S3 generated by the key human control circuit 8 by operating the memory key 1, and is specified by the preset keys 10, 10°10. This is a storage device that stores received frequency data at an address.

In addition, if the memory key 1 is not operated, the reception frequency data is read out from the storage device 6 to the tuner part 1 by selection of the preset keys 10, 10.10, and preset tuning is performed. .

Reference numeral 11 denotes a clock section whose time display output is inputted to a decoder 4 via a gate circuit 12 and also guided to a display 5.

8 is a key manual control circuit for radio operation and time setting, and is configured to control the sweep pulse generator 2, the digital tuner part 1, the storage device 6, and the clock section 11.

13 is a flip-flop that controls the gate circuit 3.12; a set terminal is connected to a pulse generator 14 that generates a pulse train at predetermined intervals (for example, 5 seconds); and a reset terminal is connected to the output of the sweep pulse generator 2. and the output S2 of the key manual control circuit 8 are connected via an OR gate 15.

The output of the OR gate 15 is also connected to the reset terminal of the pulse generator 14.

The output Q of the flip-flop 13 is connected to the reset terminal of the flip-flop 9.

FIG. 2 is a diagram showing in detail an example of the Mars generator 14 shown in FIG. 1, in which a reference potential is applied to one input and a time constant circuit consisting of a resistor 16 and a capacitor 11 is connected to the other input. 1 by the comparator 18 and the output generation of the comparator 18
One-shot multi-by-break that generates pulses
19, and a transistor 20 which becomes conductive when the one-shot multi-by-break 19 generates an output and when a reset signal is generated from the OR gate 15 to discharge the charge of the capacitor 11.

That is, when the charged potential of the capacitor 11 gradually rises and reaches the reference potential (2) of the voltage comparator 18, an output is obtained from the voltage comparator 18 and one pulse is generated by the one-shot multi-by-break 19.

When this pulse is generated, the transistor 20 is made conductive via the diode 21, and after the charge in the capacitor 17 is discharged, the charge rises again, thereby generating a pulse train at a predetermined interval (see FIGS. 3a and 3b).

The pulse generation interval is determined by the time constant of the resistor 16 and capacitor 17, and is currently set to 5 seconds.

Next, the operation of the present invention having such a configuration will be explained.

First, if no radio operation is being performed, the flip-flop 1 is activated by the pulse generated by the pulse generator 14.
3 is in the set state, and when the gate circuit 12 is opened by the set signal n Q p+, the time display output is applied to the display 5 via the decoder 4 to display the time.

Therefore, the time is displayed even when listening to the radio.

Next, when the preset key 10 is operated in this state, the key manual control circuit 8 sends a control signal S2. S4. S5
is generated, the flip-flop 13 is reset, the gate circuit 3 is opened, and the frequency display output selected by the preset key 10 is guided from the digital tuner part 1 to the display 5 via the decoder 4. Displays the frequency.

At this time, the transistor 20 of the pulse generation circuit 14 is turned on by the control signal S2, and the charge in the capacitor 1γ is discharged, so that the pulse generation circuit 14 does not generate a pulse until 5 seconds after the preset key 10 is operated. Therefore, during this time, the flip-flop 13 maintains a reset state, and the display 5 displays the reception frequency.

However, after 5 seconds have elapsed, the flip-flop 13 is set by the pulse generated by the pulse generating circuit 14, so the gate circuit 12 is opened again and the time is displayed on the display 5.

Next, the case of automatic sweep will be explained.

When performing automatic sweeping, press t, UP or DOWN sweep key 2
2, 23 is operated, control signals S, , S2 . With the occurrence of S5, the sweep pulse generation circuit 2
A sweep pulse is generated from and input to the digital tuner part 1, thereby performing a sweep operation.

Further, by resetting the flip-flop 13 by generating the sweep pulse, the gate circuit 3 is opened and the reception frequencies being swept are sequentially displayed on the display 5.

At this time as well, the pulse generation circuit 14 causes the transistor 20 to conduct due to the generation of the sweep pulse, so that the capacitor 17
Since the charge is discharged, pulse generation is stopped and the flip-flop 13 is held in a reset state.

When operating the preset key mentioned above, the time display was automatically restored by the pulse generated after 5 seconds, but the sweep pulse was 100 m5ec to 500 m5 as shown in Figure 3d.
Since the sweep pulses are generated at intervals of ec +, the transistor 20 also repeats conduction and non-conduction at these intervals while the sweep pulses are being generated, and the potential of the capacitor 17 does not rise (
(See FIG. 3C), no set pulse is generated from the pulse generator 14, and the flip-flop 13 continues to be in the reset state, and the frequency is displayed.

However, the reception detection signal S is received.

When the generation of the sweep pulse is stopped, the transistor 20 becomes non-conductive and the potential of the capacitor 17 rises.
As mentioned above, after 5 seconds, a pulse is generated, the flip-flop 13 is set, and the display is switched to the time display (see FIG. 3C).

In this way, the frequency can be displayed continuously during the sweep and for 5 seconds after reception.

Next, we will ask questions about the write operation of the storage device.

When the memory key 7 is operated, the control signal S2. When S3 occurs, one flip-flop 13 is reset and switched to frequency display, and the other flip-flop 9 is set to generate a write signal W and set the storage device 6 to a memory state.

Then, by operating the UP or DOWN sweep keys 22 and 23, a receiving station is searched for in the same manner as described above.

During this time, since the flip-flop 13 is held in the reset state, the other flip-flop 9 is not reset and continues in the memory state.

Then, when the preset key P1 is operated after receiving the data, the storage device 6 specified by the preset key P1 is
The reception frequency data of that station is stored at the address.

If the sweep keys 22 and 23 are operated again within 5 seconds after reception, one of the flip-flops 13 will still be held in the reset state, so the reception frequency will be displayed on the display 5 and the memory state will continue. By operating another preset key when the data is received again, the data can be preset in the storage device 6 in the same manner as described above.

After all the presets are sequentially completed by the same means, one of the flip-flops 13 is connected to the pulse generating circuit 1.
By being set by a pulse from 4, the display switches to time display, and the other flip-flop 9 is reset to release the memory state.

Thus, while the reception frequency is displayed on the display 5 after operating the preset key, it can be identified that the device is in the memory state.

Conversely, if the time is displayed on the display 5 after the memory key 7 is operated, the time cannot be stored in memory.

As mentioned above, the preset receiver with clock of the present invention is configured so that the memory state is canceled by switching from the receiving frequency display to the time display, and the memory state can be identified by also using the display function of the display. , there is no need to provide a separate memory status display means, and this is of great practical value.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the configuration of the present invention, and Figure 2 is a block diagram showing the configuration of the present invention.
A detailed view of the covering portion, and FIG. 3 is a waveform diagram of the second fixed portion. 1...Digital tuner part, 2...
・Sweep pulse generation circuit, 5...Display device, 6...
...Storage device, 7...Memory key, 8.
...Key human control circuit, 10...Preset key, 11...Clock section, 14...
pulse generator.

Claims (1)

[Scope of utility model registration request] A part of the digital tuner that performs a sweep operation by counting sweep pulses, a sweep pulse generator that supplies sweep pulses to the part of the digital tuner, a clock part that generates a clock display output, and a part of the digital tuner. A decoder that selectively encodes the frequency display output and the clock display output from the clock section, a display that provides digital display based on the output of this decoder, and a parallel cable between the part of the digital tuner and the clock section. A signal is applied to the first and second gates interposed in the clock section, and in the first state, the second gate corresponding to the clock section is opened to control the digital tuner. The first gate corresponding to the part is closed, and the second gate is closed.
In this state, the first gate is opened and the second gate is opened.
a pulse generator that generates a pulse having a period slower than the sweep pulse to bring the flip-flop circuit into a first state after a predetermined period in response to application of a trigger signal; The radio has a sweep control key for performing an up or down sweep, a preset key, and a memory key for setting a storage device for storing reception station data into a writable state, In response to operation of a memory key of the operation key means, the storage device is set to a writable state, the flip-flop circuit is set to a second state, and the pulse generator is triggered for the predetermined period of time. After that, the flip-flop circuit is returned to the first state, a second gate corresponding to the clock section is opened, and a clock display output is guided to the display, and the first state return output of the flip-flop circuit is used to return the memory device to the first state. A preset receiver with a clock, comprising means for canceling the memory state of the receiver.