KR830001982B1 - Tuning data storage - Google Patents

Abstract

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Description

Tuning data storage

1 is an explanatory diagram of a configuration of a conventional tuned data storage device.

2 is a diagram illustrating the configuration of an embodiment of the present channel selection data storage device.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to tuning data storage devices related to the improvement of electronic tuning politics such as color television receivers.

In the electron beam station value of a television receiver, as a means for varying the frequency of the local oscillator of the tuner circuit, the duty of the cycle pulse is varied and converted into an analog voltage, and applied to the terminal of the variable capacitance diode by the voltage. There is something designed to do. In such a device, if various kinds of settings can be made for the cycle pulse duty corresponding to each channel, it is not necessary to perform the same duty sweeping for each station. Therefore, the data of the duty setting is stored in advance in each position of the memory circuit. That is done. When the desired position is designated and the data is read out and applied to these tuning pulse generating circuits, a channel corresponding to the data stored in the position can be received.

As such a device, there is a device as shown in FIG. 1 conventionally. In Fig. 1, reference numeral 11 denotes a position designation device. When a desired position switch provided in this operation is operated, data in the memory circuit 12 corresponding to the switch is read out, and the data is synchronized with the pulse. Is applied to the generating circuit 13. The tuning pulse generating circuit 13 generates pulses of the duty based on the read data from the memory circuit 12. This tuning pulse is applied to the digital analog conversion circuit 14 and converted into a DC voltage. The converted voltage is then applied to the tuner circuit as the tuning voltage.

In this case, the apparatus has the mode switch 15 switched to the contact point 15, that is, the read mode, and the position designating apparatus 11, the memory circuit 12, and the tuning pulse generating circuit 13 described above. , The digital analog conversion circuit 14 operates as a path.

Next, when the mode switch 15 is switched to the write mode and connected to the contact 152 side, the device can change the data content of each position of the memory circuit 12. The sequence of this rewrite operation is as follows.

end. First, the mode switch 15 is switched to the write mode. I. Operate the designation device to select the position to be stored in the memory circuit. All. Next, the sweep switch 16 is operated so that the tuning voltage starts from zero. la. If a predetermined intermediate frequency is obtained from the tuner circuit in the middle of this sweeping operation, the sweeping stop signal is applied at the sweeping stop signal input terminal 17, and the sweeping operation is stopped. hemp. If the screen being won is that of a desired channel, the memory switch 18 is operated ON, and the data setting the pulse duty at this time is written into the memory circuit 12. When writing the data of the other channel in the other position, the above-described operation is repeated. Finally, the mode switch 15 is returned to the read mode.

According to the above-described apparatus, the operation procedure is complicated, and there is a disadvantage that an operation mistake such as forgetting of data is caused.

SUMMARY OF THE INVENTION The present invention has been made to cope with the above circumstances, and provides a tuning data storage device which can prevent a mistake in operation by forgetting to store the tuning data in a memory circuit, and can simplify the storage operation procedure. It aims to provide.

Hereinafter, an embodiment of the present invention will be described with reference to FIG. 2 as follows.

In the figure, A is a memory circuit, and the data reading and data writing lines A ₁ in this circuit are connected to the channel selection data input terminal B ₁ of the tuning pulse generating circuit B. FIG. The tuning pulse output stage of the tuning pulse generator circuit B described above is connected to the digital analog converter circuit C. The output terminal of the digital analog converter circuit C is connected to the tuning voltage input terminal of the tuner section.

The tuning pulse generating circuit B described above is provided with a sweep stop signal input terminal B ₂ for stopping the change in the duty of the pulse generated here. In addition, in this tuning pulse generating circuit B, the data of the previously selected tuning data input terminal B ₁ is switched to the input / output mode. Data input / output mode switching control stage B ₃ is installed. The tuning pulse generating circuit B described above is provided with a sweep signal input terminal B ₄ for varying the duty of the tuning pulse generated therefrom.

The aforementioned sweep signal input terminal B ₄ is connected to the sweep switch circuit E via the gate circuit D. The sweep switch circuit E can apply a sweep start pulse to the sweep signal input terminal B ₄ , which has been passed through one input terminal of the gate circuit, when the gate circuit D is open when it is turned on. The above-described gate circuit D is controlled by the mode switch circuit F for switching the above-described memory circuit A into a write mode and a read mode. One input terminal of this mode switch circuit F is connected to a power supply, the other input terminal is connected to a reference potential terminal, and an output terminal of which one is selected is the other input terminal of the electric gate circuit D as the inverter D. _It is connected through ₁ .

In addition, the output terminal of the mode switch circuit F described above is connected to the data input / output switching control means B ₃ of the tuned pulse generating circuit B described above, and also to the write and read mode control stage A ₂ of the memory circuit A described above. It is. Again, the output end of this mode switch circuit F is also connected to the write signal generation circuit G.

In addition to the data read and data write lines A ₁ , the above-described memory A is provided with an address specifying control terminal A _{3 for} rewriting an instruction signal input terminal A ₄ for specifying an address in the memory circuit. The foregoing addressing control stage A ₃ is connected to the designation signal output terminal H ₁ of the position designating apparatus H.

The memory circuit A reads data stored at the address based on an address designation signal from the position designation device H when the read mode, that is, the mode control stage A ₂ is at a high level. It can be read out by the data writing line A ₁ . When the write mode control stage A ₂ is at the low level, the memory circuit A reads data and writes data when there is a write command signal at an address based on the address designation signal from the position designating device H. Write the data from A ₁ .

Next, generation of the write command signal described above is obtained through two paths and is derived through the OR circuit I. The sseoneotgi command signal, the first path occurs when the address specified state by the designation of designated keys (not shown value> switching in the specified electrical position device H. This sseoneotgi command signal output terminal H _2, the gate circuit It is connected to one input terminal of J, and the output terminal of the gate circuit J is connected to one input terminal of the electric circuit I. The second path of the write command signal is from the electric write signal generation circuit G. That is, the output end of the write signal generation circuit G is connected to one pressure end of the gate circuit K, and the output end of the gate circuit K is connected to the other input end of the OR circuit I described above. The write command signal for the memory circuit A described above can be written from either the write signal generation circuit G or the position designating device H if the gate gates J and K are opened. Can be added.

Next, the gate circuits J and K described above close their gates so that a write signal is not applied in the case where the memory circuit A read-out mode. That is, the output terminal of the latch circuit L is connected to the other input terminal of the gate circuits J and K. The output terminal of the AND circuit M is connected to the set input terminal of the latch circuit L. The sweep stop signal input terminal B _{2 described above} is connected to one input terminal of the AND circuit M, and the output terminal of the latch circuit N is connected to the other input terminal. The output terminal of the aforementioned gate circuit D is connected to the set input terminal of the latch circuit N described above. Therefore, the latch circuit N described above is set by the output of the gate gate D described above, and the latch circuit L described above is set by the logical product of the output of the latch circuit N and the signal level of the sweep stop signal input terminal B ₂ . do.

The output terminal of the OR circuit O is connected to the reset input terminals of the latch signals N and L described above. The write command signal output terminal is connected to one input terminal of the aforementioned OR circuit O via a delay circuit P, and the output terminal of the appropriate write signal generation circuit G is connected to the other input terminal. Therefore, the paths capable of resetting the latch signals N and L described above include a path from the write signal generation circuit G, a path from the position designation device H and the delay circuit P.

The tuning data storage device of the present invention is configured as described above, and the tuning pulse generating circuit B can generate a pulse having a duty based on the tuning data binary code given to the tuning data input terminal B ₁ . The output pulse of this tuning pulse generating circuit B is applied to the DA conversion circuit C and converted into a DC voltage. The output of this DA converter circuit C applies the variable capacitance of the tuner device as the terminal voltage of the diode, the local oscillation frequency is varied by the capacitance change, and the new frequency is set. Therefore, if the tuning frequency and the tuning data of each of the memory circuits A described above are respectively associated with each other, the desired tuning data can be read by the key of the position designation device, thereby receiving a channel corresponding thereto.

In the case of the reception mode described above, the mode switch circuit F switches to the high level. The latch circuits N and L are in a reset state. Gate circuits D, J, and K are closed. Again, also with respect to the memory circuit A, only the data read line is turned on.

Next, a case of rewriting the data stored in the above-described memory circuit A will be described. In this case, the mode switch circuit F is first switched to the write mode, that is, the low level. As a result, the gate circuit D is opened, and the output of the sweep switch circuit E can be applied to the sweep signal input terminal B ₄ of the tuning field generating circuit B. When the sweep switch circuit E is operated so that the sweep start pulse is applied to the sweep signal input terminal, the tuning pulse generating circuit B converts the output pulse duty every suitable cycle and applies it to the DA converter circuit C. As a result, a frequency sweep of the tuner device is performed, and when a station is received in the middle, a pulse is obtained at the sweep stop signal input terminal B ₂ and the pulse duty of the tuning pulse generating circuit B is fixed at the same time.

The channel selection data corresponding to the pulse duty at this time is also set in the channel selection data input / output terminal B ₁ . Here, if the station being received needs a station, the operator can store the tuning data in the memory circuit A. It is possible to designate the address of the memory circuit A corresponding to this key by operating the key to which the position designation H value is desired. In this case, the memory circuit A is set to the writing mode because the mode switch circuit F described above is at a low level. When the key of the position designating device H is pressed, a write pulse is obtained from the write command signal output terminal H ₂ , and is applied to the write command signal input terminal A ₄ of the memory circuit A via the gate circuit J and the OR circuit I, thus, the memory. The circuit A can write the tuning data set in the tuning data input / output terminal B ₁ of the tuning pulse generating circuit B to the designated address. In the previous date, J and K are opened when the postmark stops. This is because the latch circuit N is in a set state when the sweep start pulse is applied to the tuning pulse generating circuit B to which the sweep start pulse is applied, and the latch circuit L is in a set state when the sweep stop signal is applied to one input terminal of the AND circuit M. Is caused.

However, when the above-described writing is performed on the memory circuit A, the latch circuit L is reset through the delay circuit P and the OR circuit O, so that the gate circuits J and K are closed soon after the writing is completed.

If the station received by the above-described sweeping operation is unnecessary, the tuning pulse generating circuit B continuously starts to change the pulse duty by operating the sweeping switch circuit E again.

In the above description, the reception is obtained as the operation of the desired key of the position designating device corresponding to the reception, but the key of the desired address to be stored in advance may be operated.

In this case, the write command signal must be generated when the desired station is received. As such a write command signal generating means, this apparatus has a feature, and it is possible to generate a write command signal from two paths.

The first path of the write command signal generation is a path to be used for the write command signal generated by manipulating the next desired key in the position designating apparatus. The second path is the output of the write signal generation circuit G obtained when the mode switch circuit F is switched to the read mode since other stations are unnecessary when this reception is obtained.

It is also possible to write by the output of the write signal generating circuit G being applied to the write command signal input terminal of the memory circuit A via the gate circuit K and the OR circuit I. In this case, the time constant of the mode control voltage for the mode control stage of the memory circuit A is set, and is set so as not to be switched immediately.

According to the tuning data storage device according to the present invention described above, writing tuning data to the memory circuit is surely obtained, which is caused by the write command signal being automatically obtained. Further, the write command signal is opened only when the sweep circuit has a sweep stop signal as the write circuit, and the wrong write operation is prevented by being applied to the write command signal input terminal. Again, the automatic generation means for the write command signal as described above is generated when a signal is generated when the next designated key in the position designating device H is operated and the mode switch circuit F is switched to the read mode. Since either signal is used, there is an advantage that a malfunction such as forgetting of writing can be prevented. In addition, there is no need to provide a separate operation switch for writing, and the operation procedure can be simplified. In addition, since the write command signal is obtained also in switching only the mode switch circuit F, only one channel can be written.

As described above, the present invention can provide the tuning data storage device which can prevent the memory forgetting of the tuning data and can simplify the procedure of the storage operation.

Claims (1)

Memory A for providing pulse duty data for corresponding tuning of a channel to be read or written, positioning means H for addressing the memory to generate an address signal during operation, and pulse duty data in the memory are written Mode selection means F for selecting a read mode in which a lost write mode or pulse duty data is read out from the memory, and the tuner data corresponding to the pulse duty being output in the write mode is popular with the tuning data input / output stage. The readout mode includes a generating circuit B for generating a tuning pulse for outputting a pulse of a duty based on tuning data applied to a writing data input / output terminal to the memory circuit, wherein the positioning data memory operates the positioning means H. The first summer signal generated when A first sump signal supply means J for applying a second sump signal, a sump signal generation means G for generating a second sump signal when the door selecting means F is switched to a read mode, and the second And a second writing signal supply means K for supplying the memory from the writing signal generating means G of the writing signal of the writing signal.

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