KR830003986A - Tuning data storage - Google Patents

Tuning data storage Download PDF

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Publication number
KR830003986A
KR830003986A KR1019800001570A KR800001570A KR830003986A KR 830003986 A KR830003986 A KR 830003986A KR 1019800001570 A KR1019800001570 A KR 1019800001570A KR 800001570 A KR800001570 A KR 800001570A KR 830003986 A KR830003986 A KR 830003986A
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South Korea
Prior art keywords
circuit
pulse
input terminal
input
gate
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KR1019800001570A
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Korean (ko)
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KR830001982B1 (en
Inventor
마사히로 후지다
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이와다 가즈오
도오쿄오 시바우라 덴기 가부시기 가이샤
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Priority to KR1019800001570A priority Critical patent/KR830001982B1/en
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
    • H03J7/18—Automatic scanning over a band of frequencies
    • H03J7/20—Automatic scanning over a band of frequencies where the scanning is accomplished by varying the electrical characteristics of a non-mechanically adjustable element
    • H03J7/28—Automatic scanning over a band of frequencies where the scanning is accomplished by varying the electrical characteristics of a non-mechanically adjustable element using counters or frequency dividers

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  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

내용 없음No content

Description

선국데이터 기억장치Tuning data storage

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 선국데이터 기억장치의 구성 설명도. 제2도는 본 발명 선국데이터 기억장치의 일실시예를 나타낸 구성 설명도이다.1 is an explanatory diagram of a configuration of a conventional tuned data storage device. 2 is a block diagram showing an embodiment of the tuned data storage device of the present invention.

Claims (2)

복수의 지정키이를 가진 포지션 지정장치와, 전기한 복수의 지정키이에 대응한 어드레스를 가짐과 함께 써넣기 읽어내기 라인을 가지며, 써넣기 모우드에 있어서 전기한 지정키이 조작에 의하여 이에 대응하는 어드레스에 그 라인의 선국디이터를 써넣기가 가능하며, 읽어내기 모우드에 있어서 전기한 지정키의 조작에 의하여 이에 대응하는 어드레스의 선국데이터를 그 라인으로 읽어내기 가능한 메모리 회로와, 이 메모리 회로의 전기한 전국디이터 써넣기 읽어내기 라인이 선국디이터 입출력단에 접속되며, 소인개시펄스가 소인신호 입력단에 가하여지므로서 연속추력 펄스의 펄스듀티를 적합한 사이클로서 가변이 가능하며, 전기한 써넣기 모우드에 있어서는 출력중의 펄스의 펄스듀티에 대응하는 선국디이터를 전기한 선국디이터입출력단에 설정하고, 읽어내기 모우드에 있어서는 전기한 메모리회로에서 전기한 선국디이터 입출력단에 가하여진 선국데이터에 의거한 듀티의 펄스를 출력하는 동조펄스 발생회로와, 전기한 메모리회로의 써넣기 지령신호 입력단에 오어회로의 제1,제2입력단을 통해서 접속된 제1,제2의 게이트회로와, 전기한 제1의 게이트회로의 한쪽의 입력단에 접속되며, 전기한 포지션 지정장치의 지정키이가 절환되었을때에 발생하는 신호를 써넣기 지령회로로서 이 제1의 게이트회로에 가해지는 제1의 수단과, 전기한 제2의 게이트회로의 한쪽의 입력단에 접속되며, 전기한 메모리회로, 동조펄스 발생회로의 모우드를 절환하는 모우드스위치회로가 써넣기 모우드에서 읽어내기 모우드를 절환되었을 때에 발생하는 신호를 써넣기 지령신호로 하여 이 제2의 게이트회로에 가하는 제2의 수단과, 전기한 제1,제2의 게이트회로의 다른 쪽의 입력단(개폐제어단)에 접속되며, 전기한 동조펄스 발생회로에 대한 소인개시펄스에 이어서 소인정지신호의 2개의 신호가 있을 경우에 그 논리적(論理積)을 취하고 전기한 제1, 제2의 게이트회로를 개폐제어하는 제3의 수단과를 구비한 것을 특징으로 하는 선국데이터 기억장치.A position designation device having a plurality of designation keys, and a write-out line having an address corresponding to the plurality of designation keys described above, and a line to be read at the corresponding address by an operation of the designation key described in the writing mode. A memory circuit capable of writing a presetting indicator of the memory and capable of reading out the presetting data of the corresponding address to the line by operating a designated key read in the read mode, and a nationwide indicator of this memory circuit. The write-read line is connected to the tuning indicator input / output terminal, and the sweep duty pulse is applied to the sweep signal input terminal, so that the pulse duty of the continuous thrust pulse can be varied as a suitable cycle. The tuning indicator corresponding to the pulse duty of the In the read mode, a synchronization pulse generation circuit for outputting a pulse of duty based on tuning data applied to the tuning data input / output terminals transmitted by the electrical memory circuit, and a write command signal input terminal of the electrical memory circuit. Is connected to the first and second gate circuits connected through the first and second input terminals of the circuit and to one of the input terminals of the first gate circuit. The first signal applied to the first gate circuit and the input terminal of the second gate circuit described above are connected to the input terminal of the first gate circuit as a write-in command signal. The switching mode switch circuit reads from the write mode and applies the signal generated when the switching mode is switched to the second gate circuit as a write command signal. The second means and the other input terminals (opening and closing control stages) of the first and second gate circuits described above, and two signals of the sweep start signal following the sweep start pulse for the tuned pulse generation circuit described above. And third means for taking the logical position and opening and closing the first and second gate circuits, if any. 전기한 제1,제2의 게이트회로를 개폐제어하는 제3의 수단은, 전기한 동조펄스 발생회로에 가해지는 소인개시펄스에 의해서 세트상태로 되는 제1의 래치회로와, 이 제1의 래치회로의 출력단이 제1의 입력단에 접속되며, 제2의 입력단에는 전기한 소인정지신호의 입력단이 접속된 앤드회로와, 이 앤드회로의 논리적으로 만족시의 출력에 의해서 세트상태로 되는 제2의 래치회로와를 가지며, 이 제2의 래치회로의 출력단을 전기한 제1,제2의 게이트회로의 각 다른쪽의 입력단에 접속한 것을 특징으로 하는 특허청구의 범위 제1항 기재의 선국데이터 기억장치.The third means for opening and closing the first and second gate circuits described above includes a first latch circuit which is set by a sweep start pulse applied to the tuning pulse generator circuit described above, and the first latch circuit. The output terminal of the circuit is connected to the first input terminal, and the second input terminal is connected to the input circuit of the pre-minus stop signal and the second input terminal is set by the logically satisfied output of the AND circuit. The tuned data storage according to claim 1, wherein the output terminal of the second latch circuit is connected to the other input terminal of the first and second gate circuits. Device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019800001570A 1980-04-16 1980-04-16 Tuning data storage Expired KR830001982B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019800001570A KR830001982B1 (en) 1980-04-16 1980-04-16 Tuning data storage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019800001570A KR830001982B1 (en) 1980-04-16 1980-04-16 Tuning data storage

Publications (2)

Publication Number Publication Date
KR830003986A true KR830003986A (en) 1983-06-30
KR830001982B1 KR830001982B1 (en) 1983-09-29

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ID=19216266

Family Applications (1)

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KR1019800001570A Expired KR830001982B1 (en) 1980-04-16 1980-04-16 Tuning data storage

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KR830001982B1 (en) 1983-09-29

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