JPS5941648Y2 - receiver with clock - Google Patents

Description

[Detailed description of the invention] The present invention relates to a receiver with a clock that switches between time and frequency display on a single display.Usually, the time is displayed and the desired frequency is displayed by sweeping up or down. To provide a receiver with a clock that automatically returns to displaying the time after displaying the frequency for a predetermined period both when receiving and receiving a frequency selected in advance by a preset operation.

Conventionally, as shown in Japanese Utility Model Application Publication No. 52-6402, this type of clock-equipped receiver normally displays the time on a single display, and automatically switches to frequency display only during sweep operation. A receiver with a clock has been proposed.

The configuration of such a receiver with a clock includes a keyboard and a flip-flop circuit that uses the keyboard input to switch between frequency input and time input to a single display.Normally, the time is displayed, and the input is automatically performed only during sweep operations. The frequency display can be switched to the frequency display.

Then, during operations such as auto manual and auto tuning, a flip-flop is set via a gate circuit, and the data input to the display is switched between frequency input and time input to decode and display the frequency, and during tuning, the flip-flop is set. It is configured to reset the input data to the display and switch to time input, and to receive the preset station, the receiving station is set by inputting from the keyboard, but the data input to the display is not switched, and the input data to the display is changed by means such as a lamp. The display is configured to display a clock.

However, in such a conventional receiver with a clock, after tuning by tuning operation, it is necessary to reset the flip-flop circuit via a delay circuit and switch the input data to the display to the time input.

For this reason, if the frequency data is set in advance, such as preset tuning, the tuning will be instantaneous by pressing the preset button, so even if the above conventional receiver with a clock is operating the preset tuning, the frequency will not be displayed. In order to do this, as in the case of auto manual and auto tuning, after tuning, the flip-flop is inverted via a delay circuit and the display is switched to the clock display, and the frequency display of the preset station is As the time becomes shorter, the setting becomes more difficult, and when the delay time of the delay circuit is lengthened, the frequency display when tuning during channel selection becomes longer, making it impossible to set the display times of the two properly.

Therefore, the present invention has been developed by focusing on the above-mentioned points, and when selecting a preset channel, the frequency is forcibly displayed on the display for a predetermined period of time, and the display automatically returns to the time display. The present invention provides a receiver with a clock configured to continue displaying a frequency upon detection of a pulse.

Embodiments of the present invention will be described below with reference to the drawings.

1 is a part of a digital tuner that is composed of a PLL synthesizer, etc., and performs a sweep operation by counting sweep pulses from a sweep pulse generator 2, and the frequency display output is sent to a display 5 via a gate circuit 3 and a decoder 4. It is designed to be guided.

Reference numeral 6 denotes a clock section whose time display output is inputted to a decoder 4 via a gate circuit 1 and also led to a display 5.

8 is a key manual control unit for radio operation and time setting;
It is configured to control a sweep pulse generator 2, a digital tuner part 1, and a clock part 6.

9 is a flip-flop that controls the gate circuits 3 and 7; a set terminal is connected to a pulse generator 10 that generates a pulse train at a predetermined interval (for example, 5 seconds); a reset terminal is connected to a sweep pulse generator 2; The output of the key manual control section 8 is connected via an OR gate 11.

The output of the OR gate 11 is also connected to the reset terminal of the pulse generator 10.

FIG. 2 is a diagram showing in detail an example of the pulse generator 10 shown in FIG. 1, in which a reference potential is applied to one input and a time constant circuit consisting of a resistor 12 and a capacitor 13 is connected to the other input for voltage comparison. a one-shot multivibrator 1 that generates one pulse by generating the output of the comparator 14;
5, and a transistor 16 which becomes conductive when the one-shot multivibrator 15 generates an output and when a reset signal is generated from the OR gate 11 to discharge the charge in the capacitor 13.

That is, when the charging potential of the capacitor 13 gradually increases and reaches the reference potential V) of the voltage comparator 14, an output is obtained from the voltage comparator 14 and the one-shot multivibrator 15
One pulse is generated.

When this pulse is generated, the transistor 16 is made conductive via the diode 17, and the charge in the capacitor 13 is discharged and then rises again, thereby generating a pulse train at a predetermined interval (see FIGS. 3a and 3b).

The pulse generation interval is determined by the time constants of the resistor 12 and capacitor 13, and is currently set to 5 seconds.

Next, the operation of the present invention having such a configuration will be explained.

First, when no radio operation is being performed, the flip-flop 9 is set by the pulse generated by the pulse generator 10, and when the gate circuit 7 is opened by the set signal "Q", the time display output is sent to the decoder. 4 to the display 5 to display the time.

Therefore, the clock is displayed even when listening to the radio.

Next, when the preset key 18 is operated in this state, the control signals S2 and S3 are generated from the key control unit 8, so that the flip-flop 9 is reset and the gate circuit 3 is opened. The frequency display output selected at 18 is guided from the digital tuner part 1 via the decoder 4 to the display 5 to display the frequency.

At this time, the transistor 16 of the pulse generation circuit 10 is turned on by the control signal S2, and the charge in the capacitor 13 is discharged, so that the pulse generation circuit 10 generates a pulse only 5 seconds after the preset key 18 is operated. During this period, the flip-flop 9 maintains its reset state and the display 5 displays the reception frequency.

However, after 5 seconds have elapsed, the flip-flop 9 is set by the pulse generated by the pulse generating circuit 10, so the gate circuit 7 is opened again and the time is displayed on the display 5.

Next, the case of automatic sweep will be explained.

UP or D OWH sweep key 19 for automatic sweep
20 is operated, a control signal S1. Upon generation of SS, a sweep pulse is generated from the sweep pulse generation circuit 2 and inputted to the digital tuner part 1, thereby performing a sweep operation.

Furthermore, by resetting the flip-flop 9 by generating the sweep pulse, the gate circuit 3 is opened and the reception frequencies being swept are sequentially displayed on the display 5.

At this time as well, the pulse generating circuit 10 causes the transistor 16 to conduct due to the generation of the sweep pulse, so that the capacitor 13
Since the charge is discharged, pulse generation is stopped and the flip-flop 9 is held in a reset state.

When operating the preset key mentioned above, the time display was automatically returned to by the pulse generated after 5 seconds, but the sweep pulse was 100 m5ec to 500 m as shown in Figure 3d.
Since the sweep pulses are generated at intervals of 5 ec, the transistor 16 also repeats conduction and non-conduction at this interval while the sweep pulses are being generated, and the potential of the capacitor 13 does not rise (see FIG. 3C). Since no set pulse is generated, the flip-flop 9 continues to be in the reset state and the frequency is displayed.

However, the reception detection signal S is received.

When the generation of the sweep pulse is stopped, the transistor 16 becomes non-conductive and the potential of the capacitor 13 increases,
As mentioned above, after 5 seconds, a pulse is generated and the flip-flop 9 is set to switch to the time display (see FIG. 3C).

In this way, the frequency can be displayed continuously during the sweep and for 5 seconds after reception.

As described above, the clock receiver of the present invention is equipped with a time display priority function that automatically returns to time display after frequency display is performed for a predetermined period of time by radio operation.

During the sweep period in the up or down direction, the detection of the sweep pulse repeatedly resets the pulse generation circuit that sets the flip-flop that switches between the clock display output of the clock section and the frequency display output of a part of the digital tuner. In addition, when receiving a preset frequency such as a preset operation, the previous pulse generation circuit is reset only once by the preset operation, so it is possible to perform up/down sweep tuning and Even if the radio is operating in a preset tuning state,
This has the advantage that the frequency can always be displayed for a predetermined period from the time of reset, which is extremely effective for this type of receiver with a clock.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of the present invention, FIG. 2 is a detailed view of the first securing section, and FIG. 3 is a waveform diagram of the second securing section. 1...Digital tuner part, 2...
・Sweep pulse generation circuit, 3, 7... Gate circuit, 4... Decoder, 5... Display, 6
...Clock part, 8...Key manual control part,
10...Pulse generation circuit.

Claims (1)

[Scope of Claim for Utility Model Registration] A part of a digital tuner that performs a sweeping operation by counting sweep pulses, a sweep pulse generator that supplies sweep pulses to this part of the digital tuner, and a clock part that generates a clock display output. a decoder that selectively encodes the frequency display output and the clock display output from the digital tuner part and the clock section; a display device that provides a digital display based on the output of the decoder; and the digital tuner part and the clock part. The first and second
and the eleventh second gate, and the first
In the second state, the second gate corresponding to the clock part is opened and the first gate corresponding to a part of the digital tuner is closed, and in the second state, the first gate is opened and the second gate is closed. a closing flip-flop circuit; a pulse generator for generating a pulse having a slower period than the sweep pulse to bring the flip-flop circuit into a first state after a predetermined period in response to application of a trigger signal; The radio operating key means includes a sweep control key and a preset key for performing a down sweep, and the part of the digital tuner is set to a preset state in response to the operation of the preset key of the radio operating key means. and setting the flip-flop circuit to a second state and triggering the pulse generator to return the flip-flop circuit to the first state after the predetermined period of time has elapsed; The sweep pulse generator is driven in response to an operation of a sweep control key of the means, and the sweep pulse sets a part of the digital tuner to a sweep operation state and sets the flip-flop circuit to a first state. A receiver with a clock, characterized in that the pulse generator is set to a non-operating state so that the second state is continuously maintained during sweeping.