JPS6338582Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic tuning frequency control device for a tuner, and more particularly to an automatic tuning frequency control device for a tuner capable of automatic search and tuning.

There is an auto-search type automatic tuning tuner as a tuner that uses an electronic tuning method. Such a tuner has an automatic tuning frequency control device including a reversible counter capable of up and down counting, and pulse sending means for supplying clock pulses of a constant frequency to the reversible counter until a tuning detection signal is generated by an up or down command. The analog (tuning) voltage based on the count contents of the reversible counter is used as the tuning control voltage.

In such a conventional automatic tuning frequency control device, when the search switch is pressed, an up or down command signal is output to start automatic tuning, but since the frequency of the clock pulse sent from the pulse sending means is constant, The search speed was also constant. Therefore, when a long sweep is desired, a large amount of time is required.
Furthermore, when the search speed is increased by setting the frequency of the clock pulse high, there is a drawback that accurate tuning cannot be performed because the search stops after passing the tuning point.

An object of the present invention is to provide an automatic frequency tuning control device for a tuner that can quickly and reliably perform channel selection.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of an automatic tuning frequency control device according to the present invention. In the figure, 1 is a command signal generation means for instructing the start and stop of the automatic channel selection operation, and resistors R ₁ and R ₂ are connected between the power supply +V _DD and the ground.
and _R3 , respectively, are connected in series with an up command switch _S1 , a down command switch _S2 , and a stop command switch _S3 . Reference numeral 2 denotes a control signal generating means for generating an up or down control signal, which includes a set reset flip-flop 5 constituted by NAND gates 3 and 4, and a set reset flip-flop 8 constituted by NAND gates 6 and 7. It has The flip-flop 5 is set by closing the up command switch _S1 to generate an up control signal, and is reset by the closing of the down command switch _S2 or the stop command switch _S3 . The flip-flop 8 is set by closing the down command switch _S2 to generate a down control signal, and is set by the closing of the up command switch _S1 or the stop command switch _S3 . The up and down control signals are exclusive via inverters 9 and 10, respectively.
This becomes two inputs to the OR gate 11.

12 is a clock pulse generation circuit that generates clock pulses for tuning, and includes a NAND gate 13, inverters 14 and 15, and resistors R ₄ and R ₅
and a capacitor _C1 , which generates a clock pulse at a first frequency determined by the capacitor _C1 . Furthermore, the clock pulse generating circuit 12 has a capacitor _C2 connected in series with a bidirectional switch 16, which will be described later, and when the bidirectional switch 16 is turned on, the capacitor C2 is
The first because C ₂ is connected in parallel with capacitor C ₁
A clock pulse of a second frequency determined by capacitors _C1 and _C2 , which is lower than the frequency, is generated.

₁₇ generates the clock pulse of the first frequency only after a predetermined time has elapsed from the time when the up command switch _S1 or the down command switch _S2 is closed and only while these switches S1 and _S2 are closed. This is a control circuit that controls the clock pulse generator 12 to achieve the desired output, and is a simple circuit whose trigger input is the output of an AND gate 18 whose two inputs are the bidirectional switch 16 and the outputs of the up and down command switches _S1 and _S2 . Stable multi 19 and this monostable multi 1
9 and the output of AND gate 18 supplied via inverter 20 as two inputs.
The bidirectional switch 16 is turned off by the low level output of the NAND gate 21. The pulse width of the monostable multi-19 output is the resistance
Determined by R ₆ and capacitor C ₃ .

Reference numeral 32 denotes a tuning detection means for detecting the tuning state of the tuner, and includes, for example, a well-known frequency discriminator whose output voltage exhibits so-called S-curve characteristics with respect to changes in frequency, and a well-known frequency discriminator whose output voltage exhibits so-called S-curve characteristics with respect to changes in frequency, and a frequency discriminator that smooths this S-curve output to obtain an average voltage. It includes a smoothing circuit that generates a voltage, and a waveform shaping circuit that converts this smoothed voltage into a digital signal, and outputs a high-level tuning detection signal when tuning the tuner. This tuning detection signal is AND gate 1
This is the other input of the AND gate 33 which has the output of 8 as one input. The output of the AND gate 33 serves as one input of the NOR gate 34 and also serves as a trigger input of the monostable multi 23 via the inverter 22. The output of the monostable multi 23 has a pulse width equal to the resistance R ₇
and capacitor _C4 , and serves as one input of an AND gate 24 which receives the clock pulse as one input, and during its generation period, blocks input of the clock pulse to a reversible counter 25, which will be described later, to stop the change in the tuning voltage. The AND gate 24 uses the output of the exclusive OR gate 11 as one input, and its output as one input of the OR gate 26.
The OR gate 26 has the output of the NOR gate 34 and the output of the AND gate 27 whose two inputs are the clock pulse as other inputs, and supplies the output to the reversible counter 25.

28 is a reversible counter 25 which is turned up and down in accordance with the output of the monostable multi 23 in order to change the tuning voltage up and down by a set step to re-tune when the radio wave is interrupted due to detuning, tunneling, fading, etc. Up/down command signal generation means uses clock pulses to sequentially generate up and down command signals to control operation. The output of this command signal generating means 28 is an exclusive OR signal applied via an inverter 29.
AND gate 3 with the output of gate 11 as one input
Input other than 0. The output of the AND gate 30 becomes the other input of a NOR gate 31 whose one input is the output of the inverter 10. The output of this NOR gate 31 becomes an up and down command signal for the reversible counter 25. This reversible counter 25 then passes through a pulse synthesizer 40 to a D/A converter 41.
The voltage is converted into an analog voltage and supplied as a tuning voltage to a tuning circuit (not shown).

In this configuration, the operation will be explained using the timing waveform diagram shown in FIG. First, at time _t1 , the UP or DOWN command switch _S1 or
By pressing S ₂ to turn on, the output a of the AND gate 18 becomes a low level, and since the monostable multi 19 operates on the fall of the output of the AND gate 18, the output b becomes a low level T for a predetermined time. . The output c of the NAND gate 21, which has this output and the inverted output of the AND gate 18 as its two inputs, maintains a high level, and at time _t2 , when a predetermined time T has elapsed from time _t1 , the output of the AND gate 18 is still at a low level, i.e. When the switch _S1 or _S2 is pressed, the output of the monostable multi 19 becomes high level, and therefore becomes low level. This NAND gate N2
The bidirectional switch 16 controlled by the output of
When the NAND gate 21 outputs a high level, it becomes an on state, and when it outputs a low level, it becomes an off state. Therefore, when the switch 16 is on, the oscillation frequency of the clock pulse is determined by C=C ₁ +C ₂ , and when the switch 16 is off, C=C ₁ and the oscillation frequency becomes high. Therefore, as shown in e, by pressing the up or down switch _S1 or _S2 , a low frequency clock pulse is sent to the reversible counter 25.
By continuing to press the switch _S1 or _S2 after the predetermined time T has elapsed, a high frequency clock pulse is supplied to the reversible counter 25 from time _t2 , thereby increasing the search speed.

Also, the time t ₃ when the station reaches the vicinity of the broadcast station you want to receive.
By turning off switch _S1 or _S2 , the output of AND gate 18 becomes high level.
Since the output of the NAND gate 21 also becomes high level, the bidirectional switch 16 is turned on. Therefore, since a low frequency clock pulse is supplied to the reversible counter 25, the search speed becomes low.
In a low-speed search state, the output of the monostable multi 23 becomes low level by outputting a tuning detection signal from the tuning detection means 32, and the input of the clock pulse to the reversible counter 25 is stopped, so that the clock pulse is surely stopped at the tuning point. Furthermore, if the command switch S ₁ or S ₂ is turned off within a predetermined time T after being turned on, the output of the AND gate 18 will be at a high level from that point on, and the output of the NAND gate 21 will be at a high level even after the elapse of the predetermined time T. Even if the high level is maintained and the low-speed search is continued, and the desired broadcasting station is present within the predetermined time T, it can be reliably stopped at the tuning point as in the case described above. Furthermore,
While the command switch S ₁ or S ₂ is in the ON state,
Since the output of the AND gate 18 is at a low level, even if the tuning detection signal is output from the tuning detection means 32,
The output of AND gate 33 is always at a low level,
Since the clock pulse continues to be input to the reversible counter 25, even if a broadcast is received, it passes without stopping.

Note that when the monostable multi 23 receives a broadcast in a low-speed search state, its output becomes low level for a certain period of time, stopping the search, and then restarting the search, but if you want to receive that broadcast, the above-mentioned constant Stop command switch S ₃ in time
By turning on, flip-flop 5 or 8 is reset and the output of exclusive OR gate 11 becomes low level, so that the search is stopped even after the above-mentioned predetermined time has elapsed.

FIG. 3 is a circuit diagram of another embodiment of the pulse sending means in FIG. 1, in which parts equivalent to those in FIG. 1 are designated by the same reference numerals. In the figure, the pulse generation circuit 12a includes a pulse generator 35 that generates pulses of a constant frequency, and a pulse generator 35 that generates pulses of a constant frequency.
5 output pulses are divided into the first and second frequencies ₁
and a frequency dividing circuit 36 which outputs ₂ ( ₁ > ₂ ) clock pulses. On the other hand, the control circuit 17a includes a monostable multi 19 whose trigger input is the output of the AND gate 18 as in FIG.
The output of this monostable multi 19 and the invanter 20
NAND gate 21 which has two inputs as the output of AND gate ₁₈ applied via and a clock pulse with a second frequency of ₂ as two inputs, and each output of the NOR gate 37 and the AND gate 38 as two inputs.
The output of the OR gate 39 becomes one input of the AND gates 24 and 27.

As detailed above, according to the present invention, by keeping the search switch (up and down command switch) on, the search speed increases and unnecessary stations can be passed through, allowing for quick and reliable tuning. It becomes possible. By being able to appropriately select a high-speed search speed in this way, the normal search speed can be set to a certain degree of low speed, so that the search can be more reliably stopped at the optimum tuning point.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of one embodiment of the automatic tuning frequency control device according to the present invention, FIG. 2 is a timing waveform diagram for explaining the operation of FIG. 1, and FIG. 3 is a diagram of the pulse sending means in FIG. 1. FIG. 6 is a circuit diagram of another embodiment. Explanation of symbols of main parts: 1... Command signal generating means, 2... Control signal generating means, 12, 12a...
Pulse generation circuit, 16...Bidirectional switch, 1
7, 17a... Control circuit, 19, 23... Monostable multivibrator, 25... Reversible counter, 2
8...Up/down command signal generation means, 36...
...Frequency divider circuit.

Claims (1)

[Claims for Utility Model Registration] (1) A start operation section for starting an automatic channel selection operation, a stop operation section for stopping the automatic channel selection operation, and an automatic operation section for stopping the automatic channel selection operation; command signal generation means for generating a stop command signal for generating a tuning operation command signal and stopping the automatic tuning operation by operating the stop operation section; a control signal generating means that generates a control signal that disappears upon generation of a stop command signal; a synchronization detection means that detects a synchronization state and generates a synchronization detection signal; a counter; a tuner that controls the tuning frequency of the tuning circuit according to the count contents of the counter, the tuner comprising pulse sending means that supplies the signal and stops supplying the pulse signal to the counter when the tuning detection signal is generated during the period; In the automatic tuning frequency control device, the pulse sending means includes a pulse generating circuit capable of generating pulses of a first frequency and a second frequency lower than the first frequency, and a pulse generating circuit capable of generating pulses of a first frequency and a second frequency lower than the first frequency, and generating a pulse of the second frequency for a predetermined period of time; generating a pulse of the first frequency only after the elapse of the predetermined period and while the automatic tuning operation command signal is being generated; A tuning frequency automatic control device for a tuner, comprising: a control circuit that controls the pulse generation circuit to generate a pulse of the second frequency when a command signal disappears. (2) The pulse generation circuit has first and second capacitors connected in parallel or series, and the control circuit includes switching means connected in series or parallel to the second capacitor, and the automatic channel selection. a monostable multivibrator whose trigger input is an operation command signal; and an AND gate circuit whose two inputs are the automatic channel selection operation command signal and the output signal of the monostable multivibrator; The automatic tuning frequency control device for a tuner according to claim 1, wherein the switching means is controlled by an output. (3) The pulse generating means includes a pulse generator that generates pulses of a constant frequency and a frequency dividing circuit that divides the output pulse of the pulse generator to output pulses of the first and second frequencies, The control circuit includes a monostable multivibrator having the automatic tuning operation command signal as a trigger input, and an AND gate circuit having two inputs of the automatic tuning operation command signal and the output signal of the monostable multivibrator. , and gate means for outputting a pulse of the first or second frequency according to the output of the AND gate circuit. Device.