JPS60117764A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device wherein a high speed N-P-N transistor and a resistor suitable for high speed operation are commonly provided, by providing the resistor comprising a polycrystalline semiconductor and a single crystal semiconductor region, in which element regions are formed, on a semiconductor substrate. CONSTITUTION:An N type embedded layer 302 is formed on a P type silicon substrate 30. A silicon oxide film 30, a polycrystalline silicon film 304, a silicon oxide film 305, and a silicon nitride film 306 are sequentially formed. Then, with a plurality of parts of the oxide film 305 and the nitride film 306, which are to be used as resistors, being made to remain, the other parts of the oxide film 305 and the nitride film 306 are removed. The polycrystalline silicon film other than the resistor is converted into an oxide film 307. Then, impurities are introduced into remaining polysilicon layer films 304 and 305 so that they are converted into the first or second conductive type. Thereafter, an opening is provided so that it reaches the substrate in the oxide films 303 and 307 on the N type embeded layer 302. Thus the opening part 308 is formed. Then, an epitaxial layer 309 is formed in the opening part 308 up to the same height as that of the oxide layer 307. Thereafter, an oxide film 310 is attached. The device is completed in accordance with well known processes hereinafter.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a semiconductor device, and particularly to a transistor and a resistor in an integrated circuit that requires high frequency and high speed operation.

(Prior art) Recent semiconductor devices have become increasingly integrated to reduce the number of parts and high speed to reduce power consumption. This is because resistors with junctions using the method have junction capacitance and are therefore slow.

Junctionless resistors using polycrystalline silicon are increasingly being used.

FIG. 1 shows a partial structural sectional view of a conventional device having a diffused resistance. In FIG. 1, 101 is a P-type substrate, 102 is an N-type buried layer, 103 is an N-type epitaxial layer, 104
105 is a P-type insulating layer, 105 is a P-type resistance region and the base of an NPN transistor, 106 is an emitter and collector contact of an NPN transistor, 107 is an isolation film, and 108 is an aluminum electrode. As described above, since the P-type impurity is diffused into the N-type epitaxial layer 103 to form the P-type resistance region 105, there is a junction capacitance, and even if the transistor operates at high speed, the resistor 105 The problem arises of limiting the

An example of using polycrystalline silicon to improve this drawback is shown in FIG. 2. In FIG. 2, 201 is a P type substrate, 202 is an N+ type buried layer, 203 is an N type epitaxial layer, and 204 is an N type buried layer.
is a P-type isolation layer% 205 is an insulating oxide film, 206 is a NPfl
2o8 is a P-type or N-type resistor made of polycrystalline silicon, 2o9 is an insulating oxide film, 2
10 each indicates an aluminum electrode.

In the case of such a structure, it is true that the polycrystalline silicon resistor 208
Since it is surrounded by the insulating films 205 and 209, it has a junction capacitance, and since it has no voltage dependence, it is excellent as a high-speed resistor. However, in this structure, after forming each region of the NPN transistor on the polycrystalline silicon body 208, for example, a step is created on the surface to make the resistor 208 by dry etching, and as a result, aluminum wiring is formed on the resistor 208. If you place a line, a break will occur. Therefore, in order to smooth the side surfaces of the polycrystalline silicon 208, it is necessary to process the polycrystalline silicon 208 by a method such as attaching phosphorus glass and performing heat source treatment to smooth the surface. Moreover, this high-temperature heat treatment changes the element area of the previously formed N P N transistor, resulting in changes in its characteristics, resulting in a drawback that manufacturing conditions are limited. Furthermore, although it is desired to increase the speed by forming a shallow junction in the NPN transistor, there is a drawback in that the junction speed is slow due to the addition of heat treatment later.

(Objective of the Invention) An object of the present invention is to provide a semiconductor device in which a high-speed NPN transistor coexists with a resistor suitable for high-speed operation.

(Structure of the Invention) In order to achieve this object, a resistor using polycrystalline silicon is completed before forming an NPN transistor, and an insulating film on a substrate is anisotropically dried. The method is characterized in that an opening is formed by etching and selective epitaxial growth is performed in the opening in an atmosphere containing hydrogen chloride gas to form a transistor in one selective epitaxial region.

(Example) An embodiment of the invention will be described in detail below using one drawing.

FIGS. 3(a) to 3(f) show an embodiment of the invention in the order of manufacturing steps. That is, the P-type silicon substrate 3
01 has an N-type buried layer 30 with a layer resistance of about 10 to 30 rl/mouth.
2 (FIG. 3(a)), a silicon oxide film 30 is formed.
3 to 500OA-1000OA, polycrystalline silicon 304
approximately 500OA, silicon oxide film 305. are sequentially formed (Fig. 3 (bl)). Next, leave the oxide film 305 and nitride film 306 in multiple parts that you want to use as a resistor, and remove the oxide film 305 and nitride film 306 in other parts. Then, heat treatment is performed in an oxygen atmosphere to transform it into a polycrystalline silicon oxide film 307 other than the resistor (Figure 3, tel).The remaining polycrystalline silicon 304 and 305 are made with a cine dulling material by thermal diffusion or ion implantation. After introducing the oxide film 303 on the N-type buried layer 302 and converting it into the first conductivity type or the second conductivity type.
and 307 are opened by anisotropic dry etching until the substrate is reached.

Opening 308f: Formed (FIG. 3). After this, epitaxial growth is performed under reduced pressure in an atmosphere containing hydrogen chloride gas to selectively grow an epitaxial layer 309 of about 1Ω-cm in the opening 308 to the same extent as the surface of the oxide film 307, and then an oxide film 310 is formed. (FIG. 3(e)). Before this epitaxial growth, a nitride film or polycrystalline silicon is grown and selectively etched by anisotropic dry etching, leaving the nitride film or polycrystalline silicon only on the sides of the opening 308. The epitaxial layer 309 may be epitaxially grown, and then the base region 311 . Emitter”? A collector contact region 312 is then formed.

1. A window for electrode extraction is opened in the oxidized film 310, and an aluminum electrode 313 is attached to complete the process.

The uninvented semiconductor device formed by the above-mentioned manufacturing method uses polycrystalline silicon 304 and 305 as resistors and is surrounded by an insulating film, so it has no junction capacitance. meet the requirements for resistance and Moreover, since the resistors 304 and 305 are formed before epitaxial growth, the heat treatment for forming the resistors does not affect the formation of the base and emitter of the transistor, and high-speed transistors can be manufactured independently. Also, in order to selectively perform epitaxial growth and flatten the surface height, aluminum is placed on the resistors 304 and 305! There is no need to worry about run-offs even if you run the whole thing through. Furthermore, the insulation isolation between devices is not by junction isolation but by oxide film, resulting in lower capacitance and faster speed! , ::'T ah. coyo, ni, *'iF,II;tJ,:m)￥>o*This is an extremely excellent device for flattening the surface and increasing speed, which are problems with conventional structures when forming integrated circuit devices. I can say that there is.

In another embodiment of the present invention, the polycrystalline silicon resistor may have a mixture of the first conductivity type and the second fourth conductivity type, or may contain impurities of the same conductivity type but different concentrations. Also good, board 301
．． Embedded layer 3021 Selection Ebitital layer 309. ) Pace area 311, emitter, collector area 3 of transistor
Of course, the conductivity types of 12 may be reversed and used, and a nitride film may be formed on the insulating oxide film 310 and used as a passivation group.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a conventional example of a device for removing a resistor. 101...P-type silicon substrate, 102...N+
Type buried layer, 103...N type epitaxial layer. 104...P-type insulating separation layer, 105...P-type NPN transistor base region and resistance region, 106
...N-type NPN transistor emitter, collector region, 107...Insulating film, 108...
- Aluminum electrode FIG. 2 is a sectional view showing another conventional example. 201...P-type silicon substrate, 202...
N+ type buried layer, 203...N type epitaxial layer, 204...P type insulating separation layer% 205...
...Insulating oxide film, 206...P-type NPN) transistor base region M, 207...N-type NPN tranny/distor emitter and collector region, 208...
Polycrystalline silicon resistor, 209...Insulating oxide film,
210...Aluminum electrode. FIGS. 3(a) to 3(f) are cross-sectional views showing one embodiment of the present invention along the manufacturing process order. 301...P-type silicon substrate, 302...N+
Mold embedding layer, 303... Insulation baranomata, 304...
... Polycrystalline silicon, 305 ... Insulating oxide j model, 306 ... Nitride film, 307 ... Insulating oxide film % 308 ... Opening, 309 ...・・・・・・
Selective epitaxial layer, 310...insulating oxide film, 3
11...P-type NPN transistor base region,
312...N type NPN) transistor emitter, collector region, 313. ,,,・Aluminum electrode.

Claims (1)

[Claims] A single crystal semiconductor resistor formed on a semiconductor substrate and insulated from the single crystal semiconductor, and a single crystal semiconductor region formed on the semiconductor substrate in contact with the single crystal semiconductor region, in which an element region is formed. A semiconductor device comprising a crystal 21 and a conductor region.